阅读说明：本技术 电容检测电路、传感器、芯片以及电子设备 (Capacitance detection circuit, sensor, chip, and electronic device ) 是由 蒋宏 于 2020-03-03 设计创作，主要内容包括：本申请提供了一种电容检测电路、传感器、芯片以及电子设备。电容检测电路包括相互连接的电容控制模块(1)、电荷转换模块(2)以及滤波模块(3)；电容控制模块(1)控制待测电容(C<Sub>x</Sub>)进行多次充放电,并根据接收到的电荷量,产生数字电压信号；其中待测电容(C<Sub>x</Sub>)在每次充放电的过程中,被充电至预设电压后释放存储的全部电荷；电荷转换模块(2)在数字电压信号为高电平时,输出预设电荷量的负电荷至电容控制模块(1),预设电荷量大于或等于待测电容(C<Sub>x</Sub>)被充电至预设电压时存储的电荷量；滤波模块(3)根据待测电容(C<Sub>x</Sub>)多次充放电后产生的数字电压信号,得到表征待测电容(C<Sub>x</Sub>)的电容值的数值。采用上述方案,无需通过模数转换器等模拟电路便可以将待测电容的电容值数字化,电路结构简单,降低了功耗和成本。(The application provides a capacitance detection circuit, a sensor, a chip and an electronic device. The capacitance detection circuit comprises a capacitance control module (1), a charge conversion module (2) and a filtering module (3) which are connected with each other; the capacitance control module (1) controls the capacitance (C) to be measured x ) Performing charge and discharge for multiple times, and generating a digital voltage signal according to the received charge quantity; wherein the capacitance (C) to be measured x ) In the process of each charge and discharge, all stored charges are released after being charged to a preset voltage; when the digital voltage signal is at high level, the charge conversion module (2) outputs negative charge of a preset charge amount to the capacitor control module (1), wherein the preset charge amount is greater than or equal to the capacitor (C) to be tested x ) An amount of charge stored when charged to a preset voltage; the filter module (3) is based on the capacitance (C) to be measured x ) The digital voltage signal generated after charging and discharging for many times is used to obtain the characteristic capacitance (C) to be measured x ) The value of the capacitance of (c). Adopt the above-mentioned schemeThe capacitance value of the capacitor to be measured can be digitalized without analog circuits such as an analog-to-digital converter, the circuit structure is simple, and the power consumption and the cost are reduced.)

1. A capacitance detection circuit, comprising: the capacitor control module, the charge conversion module and the filtering module are connected with each other;

the capacitance control module is used for controlling the capacitor to be tested to carry out charging and discharging for multiple times and generating a digital voltage signal according to the received charge quantity; the capacitor to be tested is charged to a preset voltage in the process of charging and discharging each time, and then all stored charges are released;

the charge conversion module is used for outputting negative charges of a preset charge amount to the capacitor control module when the digital voltage signal is at a high level, wherein the preset charge amount is larger than or equal to the charge amount stored when the capacitor to be detected is charged to a preset voltage;

the filtering module is used for obtaining a numerical value representing the capacitance value of the capacitor to be tested according to the digital voltage signal generated after the capacitor to be tested is charged and discharged for multiple times.

2. The capacitance detection circuit of claim 1, wherein the capacitance control module comprises: the charge transfer module, the voltage conversion module and the comparison module are connected in sequence; the comparison module is connected with the filtering module, and the charge conversion module is connected with the voltage conversion module;

the charge transfer module is used for controlling the capacitor to be tested to carry out charging and discharging for multiple times, wherein during each charging and discharging, the capacitor to be tested is charged to a preset voltage and then releases the stored charge to the voltage conversion module;

the voltage conversion module is used for converting the received charges into analog voltage signals;

the comparison module is used for outputting a digital voltage signal according to a preset voltage threshold and the analog voltage signal;

the charge conversion module is used for outputting negative charges with preset charge quantity to the voltage conversion module when the digital voltage signal is at a high level.

3. The capacitance detection circuit of claim 2, wherein the charge transfer module comprises a first switch, a second switch, and a first power supply;

the first power supply is connected to a first end of the first switch, a second end of the first switch is connected to a first end of the second switch, a second end of the second switch is grounded, a joint of the first switch and the second switch is connected to a first end of the capacitor to be tested, a second end of the capacitor to be tested is connected to the voltage conversion module, and a control end of the first switch and a control end of the second switch are respectively used for receiving driving signals;

the first switch is used for being closed when the capacitor to be tested is charged according to the driving signal and being opened when the capacitor to be tested is discharged;

the second switch is used for being switched off when the capacitor to be tested is charged according to the driving signal and being switched on when the capacitor to be tested is discharged.

4. The capacitance detection circuit of claim 2, wherein the charge transfer module comprises a third switch, a fourth switch, and a second power supply;

the second power supply is connected to a first end of the third switch, a second end of the third switch is connected to a first end of the fourth switch, a second end of the fourth switch is connected to the voltage conversion module, a joint of the third switch and the fourth switch is connected to a first end of the capacitor to be tested, a second end of the capacitor to be tested is grounded, and a control end of the third switch and a control end of the fourth switch are respectively used for receiving driving signals;

the third switch is used for being switched off when the capacitor to be tested discharges and being switched on when the capacitor to be tested charges according to the driving signal;

and the fourth switch is used for being switched on when the capacitor to be tested discharges and being switched off when the capacitor to be tested charges according to the driving signal.

5. The capacitance detection circuit of claim 2, wherein the voltage conversion module comprises: the operational amplifier, the first reference capacitor and the fifth switch;

the charge transfer module and the charge conversion module are respectively connected to an inverting input end of the operational amplifier, a non-inverting input end of the operational amplifier is grounded, two ends of the first reference capacitor are respectively connected to the inverting input end of the operational amplifier and an output end of the operational amplifier, two ends of the fifth switch are respectively connected to two ends of the fifth reference capacitor, and a control end of the fifth switch is used for receiving a reset signal;

and the fifth switch is used for keeping closed within a preset time length before the charge transfer module controls the capacitor to be tested to charge and discharge for multiple times according to the reset signal.

6. The capacitance detection circuit of claim 2, wherein the comparison module comprises: a voltage comparator and a first trigger;

a positive phase input end of the voltage comparator is connected to the voltage conversion module, an inverted phase input end of the voltage comparator is grounded, an output end of the voltage comparator is connected to a first input end of the first trigger, a second input end of the first trigger is used for receiving an output control signal, a third input end of the first trigger is used for receiving a driving signal, and an output end of the first trigger is connected to the filtering module;

the voltage comparator is used for outputting a high level when the voltage value of the analog voltage signal is greater than the voltage threshold value, and outputting a low level when the voltage value of the analog voltage signal is less than the voltage threshold value;

the first flip-flop is configured to, when the driving signal is on a rising edge, output the level of the digital voltage signal as the current level of the voltage comparator, and when the driving signal is on a falling edge, keep the level of the output digital voltage signal unchanged.

7. The capacitance detection circuit of claim 1, wherein the filtering module comprises a counter and a second flip-flop, the comparing module is connected to an input of the counter, an output of the counter is connected to a first input of the second flip-flop, and a second input of the second flip-flop is configured to receive an output control signal;

the driving end of the counter is used for receiving a driving signal, and the counter is used for adding 1 to the current count value when the driving signal is at a rising edge and the digital voltage signal is at a high level;

and the second trigger is used for outputting the count value of the counter as a numerical value for representing the capacitance value of the capacitor to be detected when the output control signal is at a rising edge.

8. The capacitance detection circuit of claim 2, wherein the charge transfer module comprises: the first end of the logic controller is connected to the comparison module, and the second end of the logic controller is connected to the voltage conversion module through the charge output submodule;

the logic controller is used for controlling the charge output submodule to output negative charges with preset charge quantity to the voltage conversion module when the digital voltage signal is at a high level.

9. The capacitance detection circuit of claim 8, wherein the charge output submodule comprises a sixth switch, a seventh switch, an eighth switch, a ninth switch, a third power supply, and a second reference capacitance;

a first end of the sixth switch is connected to the voltage conversion module, a second end of the sixth switch is connected to a first end of the eighth switch, a second end of the eighth switch is grounded, a connection point of the sixth switch and the eighth switch is connected to a first end of the second reference capacitor, a first end of the seventh switch is connected to the third power supply, a second end of the seventh switch is connected to a first end of the ninth switch, a second end of the ninth switch is grounded, and a connection point of the seventh switch and the ninth switch is connected to a second end of the second reference capacitor;

the control end of the sixth switch, the control end of the seventh switch, the control end of the eighth switch and the control end of the ninth switch are respectively connected to the logic controller;

the logic controller is configured to control the sixth switch and the ninth switch to be both closed and control the seventh switch and the eighth switch to be both opened when the digital voltage signal is at a low level;

and the logic controller is used for controlling the sixth switch and the ninth switch to be both switched off and controlling the seventh switch and the eighth switch to be both switched on when the digital voltage signal is at a high level.

10. The capacitance detection circuit of claim 1, further comprising a decimation module; the capacitance control module is connected to the filtering module through the decimation module;

the decimation module is used for outputting the digital voltage signal in a preset time period to the filtering module.

11. The capacitance detection circuit of claim 10, wherein the decimation module is an and gate circuit; the first input end of the AND gate circuit is connected to the capacitance control module, and the output end of the AND gate circuit is connected to the filtering module;

and the second input end of the AND gate circuit is used for receiving an output control signal, and the time length of the output control signal at a high level in one period is the preset time period.

12. A sensor, comprising: the capacitance detection circuit of any one of claims 1 to 11.

13. A transmitter chip, comprising: the capacitance detection circuit of any one of claims 1 to 11.

14. An electronic device, comprising: the capacitance detection circuit of any one of claims 1 to 11.

15. The electronic device of claim 14, wherein the electronic device further comprises a processor;

the processor is used for obtaining the capacitance value of the capacitor to be detected according to the numerical value which is output by the capacitance detection circuit and is used for representing the capacitance value of the capacitor to be detected.

Technical Field

The present application relates to the field of circuit technologies, and in particular, to a capacitance detection circuit, a sensor, a chip, and an electronic device.

Background

The capacitance sensor is a common sensing device, and can reflect parameters to be measured through a stored charge value after being fully charged so as to realize various parameter detection, such as pressure detection, liquid level detection, distance sensing, impurity detection, touch detection and the like.

Disclosure of Invention

An object of the embodiment of the application is to provide a capacitance detection circuit, a sensor, a chip and an electronic device, which can digitize the capacitance value of a capacitor to be detected without analog circuits such as an analog-to-digital converter, and have a simple circuit structure, and reduce power consumption and cost.

The embodiment of the application provides a capacitance detection circuit, including: the capacitor control module, the charge conversion module and the filtering module are connected with each other; the capacitance control module is used for controlling the capacitor to be tested to carry out charging and discharging for multiple times and generating a digital voltage signal according to the received charge quantity; the capacitor to be tested is charged to a preset voltage in the process of charging and discharging each time, and then all stored charges are released; the charge conversion module is used for outputting negative charges with preset charge quantity to the capacitor control module when the digital voltage signal is at a high level, wherein the preset charge quantity is larger than or equal to the charge quantity stored when the capacitor to be detected is charged to a preset voltage; the filtering module is used for obtaining a numerical value representing the capacitance value of the capacitor to be measured according to the digital voltage signal generated after the capacitor to be measured is charged and discharged for multiple times.

The embodiment of the application also provides a sensor which comprises the capacitance detection circuit.

The embodiment of the application also provides a chip which comprises the capacitance detection circuit.

The embodiment of the application also provides electronic equipment which comprises the capacitance detection circuit.

Compared with the prior art, the capacitor control module controls the capacitor to be tested to perform charge and discharge for multiple times, when the capacitor to be tested is charged and discharged each time, the capacitor to be tested is charged to a preset voltage and then releases the stored charges, the capacitor control module can output a corresponding digital voltage signal according to the received charge amount, and when the digital voltage signal is at a low level, the capacitor control module only receives the charges released by the capacitor to be tested; when the digital voltage signal is at a high level, the charge conversion module outputs negative charges with a preset charge amount to the capacitor control module, namely the capacitor control module simultaneously receives the charges output by the capacitor to be detected and the charge conversion module, and then after the capacitor to be detected is charged and discharged for multiple times, the filtering module can obtain a numerical value representing the capacitance value of the capacitor to be detected according to the digital voltage signal generated after the capacitor to be detected is charged and discharged for multiple times, the capacitance value of the capacitor to be detected can be digitized without analog circuits such as an analog-to-digital converter and the like, the circuit structure is simple, and the power consumption and the cost are reduced; and the anti-interference capability of the capacitance detection circuit can be improved by increasing the charging and discharging times of the capacitance to be detected.

For example, the capacitance control module includes: the charge transfer module, the voltage conversion module and the comparison module are connected in sequence; the comparison module is connected with the filtering module, and the charge conversion module is connected with the voltage conversion module; the charge transfer module is used for controlling the capacitor to be tested to carry out charging and discharging for multiple times, wherein during each charging and discharging, the capacitor to be tested is charged to a preset voltage and then releases the stored charge to the voltage conversion module; the voltage conversion module is used for converting the received charges into analog voltage signals; the comparison module is used for outputting a digital voltage signal according to a preset voltage threshold and the analog voltage signal; the charge conversion module is used for outputting negative charges with preset charge quantity to the voltage conversion module when the digital voltage signal is at a high level. The embodiment provides a specific structure of the capacitance control module.

For example, the charge transfer module includes a first switch, a second switch, and a first power supply; the first power supply is connected to the first end of the first switch, the second end of the first switch is connected to the first end of the second switch, the second end of the second switch is grounded, the joint of the first switch and the second switch is connected to the first end of the capacitor to be tested, the second end of the capacitor to be tested is connected to the voltage conversion module, and the control end of the first switch and the control end of the second switch are respectively used for receiving a driving signal; the first switch is used for being closed when the capacitor to be tested is charged according to the driving signal and being opened when the capacitor to be tested is discharged; the second switch is used for being switched off when the capacitor to be tested is charged according to the driving signal and being switched on when the capacitor to be tested is discharged. The embodiment provides a specific structure of a charge transfer module applied to self-contained detection.

For example, the charge transfer module includes a third switch, a fourth switch, and a second power supply; the second power supply is connected to the first end of the third switch, the second end of the third switch is connected to the first end of the fourth switch, the second end of the fourth switch is connected to the voltage conversion module, the joint of the third switch and the fourth switch is connected to the first end of the capacitor to be tested, the second end of the capacitor to be tested is grounded, and the control end of the third switch and the control end of the fourth switch are respectively used for receiving a driving signal; the third switch is used for being switched off when the capacitor to be tested discharges and being switched on when the capacitor to be tested charges according to the driving signal; the fourth switch is used for being closed when the capacitor to be tested discharges and being opened when the capacitor to be tested charges according to the driving signal. The embodiment provides a specific structure of a charge transfer module applied to mutual capacitance detection.

For example, the voltage conversion module includes: the operational amplifier, the first reference capacitor and the fifth switch; the charge transfer module and the charge conversion module are respectively connected to the inverting input end of the operational amplifier, the non-inverting input end of the operational amplifier is grounded, two ends of the first reference capacitor are respectively connected to the inverting input end of the operational amplifier and the output end of the operational amplifier, two ends of the fifth switch are respectively connected to two ends of the fifth reference capacitor, and the control end of the fifth switch is used for receiving a reset signal; and the fifth switch is used for keeping closed within a preset time length before the charge transfer module controls the capacitor to be tested to carry out charging and discharging for multiple times according to the reset signal. The present embodiment provides a specific structure of the voltage conversion module.

For example, the comparison module includes: a voltage comparator and a first trigger; the positive phase input end of the voltage comparator is connected to the voltage conversion module, the negative phase input end of the voltage comparator is grounded, the output end of the voltage comparator is connected to the first input end of the first trigger, the second input end of the first trigger is used for receiving an output control signal, the third input end of the first trigger is used for receiving a driving signal, and the output end of the first trigger is connected to the filtering module; the voltage comparator is used for outputting a high level when the voltage value of the analog voltage signal is greater than the voltage threshold value and outputting a low level when the voltage value of the analog voltage signal is less than the voltage threshold value; the first trigger is used for keeping the level of the output digital voltage signal unchanged when the driving signal is at a rising edge and the level of the output digital voltage signal is the current level of the voltage comparator when the driving signal is at a falling edge. The embodiment provides a specific structure of the comparison module.

For example, the filtering module includes a counter and a second flip-flop, the comparing module is connected to an input end of the counter, an output end of the counter is connected to a first input end of the second flip-flop, and a second input end of the second flip-flop is used for receiving the output control signal; the driving end of the counter is used for receiving a driving signal, and the counter is used for adding 1 to the current count value when the driving signal is at a rising edge and the digital voltage signal is at a high level; the second trigger is used for outputting the count value of the counter as a numerical value representing the capacitance value of the capacitor to be measured when the output control signal is at the rising edge. The embodiment provides a specific structure of the filtering module.

For example, the charge conversion module includes: the first end of the logic controller is connected to the comparison module, and the second end of the logic controller is connected to the voltage conversion module through the charge output submodule; the logic controller is used for controlling the charge output submodule to output negative charges with preset charge quantity to the voltage conversion module when the digital voltage signal is at a high level. The present embodiment provides a specific structure of the charge conversion module.

For example, the charge output submodule comprises a sixth switch, a seventh switch, an eighth switch, a ninth switch, a third power supply and a second reference capacitor; the first end of the sixth switch is connected to the voltage conversion module, the second end of the sixth switch is connected to the first end of the eighth switch, the second end of the eighth switch is grounded, the connection position of the sixth switch and the eighth switch is connected to the first end of the second reference capacitor, the first end of the seventh switch is connected to the third power supply, the second end of the seventh switch is connected to the first end of the ninth switch, the second end of the ninth switch is grounded, and the connection position of the seventh switch and the ninth switch is connected to the second end of the second reference capacitor; the control end of the sixth switch, the control end of the seventh switch, the control end of the eighth switch and the control end of the ninth switch are respectively connected to the logic controller; the logic controller is used for controlling the sixth switch and the ninth switch to be both closed and controlling the seventh switch and the eighth switch to be both opened when the digital voltage signal is at a low level; and the logic controller is used for controlling the sixth switch and the ninth switch to be both opened and controlling the seventh switch and the eighth switch to be both closed when the digital voltage signal is at a high level. The embodiment provides a specific structure of the charge output submodule.

For example, the capacitance detection circuit further comprises a decimation module; the capacitance control module is connected to the filtering module through the extraction module; the extraction module is used for outputting the digital voltage signal in the preset time period to the filtering module. In this embodiment, an extraction module is added to the capacitance detection circuit, so that the capacitance to be detected can be periodically detected, and the power consumption is reduced.

For example, the decimation module is an and circuit; the first input end of the AND gate circuit is connected with the capacitance control module, and the output end of the AND gate circuit is connected with the filtering module; and the second input end of the AND gate circuit is used for receiving an output control signal, and the time length of the output control signal at a high level in one period is a preset time period. The embodiment provides a specific implementation manner of the extraction module.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.

FIG. 1 is a schematic diagram of a capacitance detection circuit according to a first embodiment of the present application;

FIG. 2 is a schematic diagram of a capacitance detection circuit according to a first embodiment of the present application, wherein the capacitance control module includes a charge transfer module, a voltage conversion module, and a comparison module;

FIG. 3 is a block diagram of a charge transfer module in a second embodiment of the present application, wherein the charge transfer module is used in a mutual capacitance detection mode;

FIG. 4 is a timing diagram of driving signals as clock signals according to a second embodiment of the present application;

FIG. 5 is a block diagram of a charge transfer module in a second embodiment of the present application, wherein the charge transfer module is used in a self-contained test mode;

FIG. 6 is a block diagram of a voltage conversion module according to a second embodiment of the present application;

FIG. 7 is a block diagram of a voltage conversion module according to a second embodiment of the present application;

FIG. 8 is a block diagram of a comparison module according to a second embodiment of the present application;

fig. 9 is a structural diagram of a charge conversion module according to a third embodiment of the present application;

fig. 10 is a structural diagram of a charge output sub-module according to a third embodiment of the present application;

FIG. 11 is a schematic diagram of a capacitance detection circuit according to a fourth embodiment of the present application;

FIG. 12 is a timing diagram of output control signals according to a fourth embodiment of the present application;

fig. 13 is a block diagram of a filter module according to a fourth embodiment of the present application.

DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION

In order to make the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application are described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

When the capacitance sensor is used for parameter detection, the measurement of the capacitance value of the capacitance sensor is a core step, and the measurement of the capacitance value is generally realized by an analog circuit including an analog-to-digital converter (ADC for short), so that the power consumption and the cost are high. Based on this, the inventor proposes the technical scheme of the application.

The first embodiment of the present application relates to a capacitance detection circuit, which is applied to a sensor, a chip or an electronic device, for example, a capacitance sensor, a capacitance detection chip, a mobile phone tablet computer, and the like. The capacitance detection circuit can measure the capacitance value of the capacitor, and then parameter detection, such as pressure detection, liquid level detection, distance sensing, impurity detection, touch detection and the like, is realized by utilizing the measured capacitance value.

Referring to fig. 1, the capacitance detection circuit includes: a capacitor control module 1, a charge conversion module 2 and a filter module 3 which are connected with each other, and a capacitor C to be tested_xConnected to the capacitance control module 1 in a serial or parallel manner, for example, in the figure, the capacitor C to be measured_xOne end of the capacitor C is connected to the capacitor control module 1_xAnd the other end of the same is grounded to GND.

The capacitance control module 1 is used for controlling the capacitance to be measured to carry out charging and discharging for multiple times and generating a digital voltage signal according to the received charge quantity; the capacitor to be tested is charged to a preset voltage in the process of charging and discharging each time, and then all stored charges are released.

The charge conversion module 2 is used for outputting negative charges of a preset charge amount to the capacitor control module 1 when the digital voltage signal is at a high level, wherein the preset charge amount is greater than or equal to the capacitor C to be detected_xThe amount of charge stored when charged to a preset voltage.

The filter module 3 is used for measuring the capacitance C_xObtaining a digital voltage signal generated after multiple charging and discharging to represent the capacitor C to be measured_xThe value of the capacitance of (c).

In the embodiment of the application, the capacitance control module controls the capacitor to be tested to perform charging and discharging for multiple times, when the capacitor to be tested is charged and discharged each time, the capacitor to be tested is charged to the preset voltage and then releases the stored charges, the capacitance control module can output a corresponding digital voltage signal according to the received charge amount, and when the digital voltage signal is at a low level, the capacitance control module only receives the charges released by the capacitor to be tested; when the digital voltage signal is at a high level, the charge conversion module outputs negative charges with a preset charge amount to the capacitor control module, namely the capacitor control module simultaneously receives the charges output by the capacitor to be detected and the charge conversion module, and then after the capacitor to be detected is charged and discharged for multiple times, the filtering module can obtain a numerical value representing the capacitance value of the capacitor to be detected according to the digital voltage signal generated after the capacitor to be detected is charged and discharged for multiple times, the capacitance value of the capacitor to be detected can be digitized without analog circuits such as an analog-to-digital converter and the like, the circuit structure is simple, and the power consumption and the cost are reduced; and the anti-interference capability of the capacitance detection circuit can be improved by increasing the charging and discharging times of the capacitance to be detected.

The following describes the implementation details of the capacitance detection circuit of the present embodiment in detail, and the following is only provided for the convenience of understanding and is not necessary for implementing the present embodiment.

Referring to fig. 2, the capacitance control module 1 includes a charge transfer module 11, a voltage conversion module 12, a comparison module 13, and a capacitor C to be measured connected in sequence_xConnected to the charge transfer module 11 (as shown in FIG. 2) or the capacitor C to be measured_xAnd is connected to the charge transfer module 11 and the voltage conversion module 12.

The charge transfer module 11 is used for controlling the capacitor C to be tested_xCharging and discharging for multiple times, wherein the capacitor C to be measured_xDuring each charging and discharging, the capacitor C to be measured_xIs charged to a preset voltage V_txThen the stored charge is released to the voltage conversion module 12, that is, the process of charging and discharging each time is equivalent to the process of charging and discharging the capacitor C to be tested_xPerforming a charge transfer to the capacitor C to be measured_xCharging to a predetermined voltage V_txAt this time, the capacitor C to be measured_xAmount of stored charge Q_Cx＝V_tx*C_xThen controlling the capacitor C to be measured_xAnd discharging, and releasing all the stored charges to the voltage conversion module 12.

The voltage conversion module 12 is used for converting the received charges into analog voltage signals. In particular, in the capacitor C to be measured_xIn the process of charging and discharging at each time, the voltage conversion module 12 can receive the capacitor C to be measured_xAnd will flowThe charge is converted into voltage output due to the capacitor C to be measured_xAfter each charge and discharge, the charge amount received by the voltage conversion module 12 changes, which also changes the voltage output by the voltage conversion module 12, and the voltage changes at the capacitor C to be measured_xAfter being controlled to be charged and discharged for a plurality of times, the plurality of voltages output by the voltage conversion module 12 can form a continuous analog voltage signal.

The comparing module 13 is configured to output a digital voltage signal according to a preset voltage threshold and the analog voltage signal. Specifically, after receiving the analog voltage signal sent by the voltage conversion module 12, the comparison module 13 compares the voltage value at the current moment with a preset voltage threshold, and when the voltage value is greater than the voltage threshold, the output digital signal is a high level 1; when the voltage value is smaller than the voltage threshold value, the output digital signal is low level 0; therefore, after receiving the analog voltage signal, the comparing module 13 outputs a high-low level signal according to the voltage values at different times (different charging and discharging times), thereby forming a digital voltage signal. In one example, the voltage threshold of the comparing module 13 may be a preset voltage V_txHalf of that.

The charge conversion module 2 is configured to output negative charges of a predetermined charge amount to the voltage conversion module 12 when the digital voltage signal is at a high level, where the predetermined charge amount is greater than or equal to the capacitor C to be measured_xThe amount of charge stored when charged to a preset voltage. It should be noted that, in the embodiment, the charge conversion module 2 outputs negative charges as an example, but is not limited to this, and the charge conversion module 2 may output positive charges and the voltage conversion module 12 may be provided with an inverse adder.

The filter module 3 is used for measuring the capacitance C_xObtaining a digital voltage signal generated after multiple charging and discharging to represent the capacitor C to be measured_xThe value of the capacitance of (c). Specifically, from the above, the capacitor C to be measured_xEach charge and discharge corresponds to a value of the digital voltage signal, which may be 0 or 1, and then the number of the digital voltage signal median values 1 corresponding to the multiple charges and discharges may be counted, which is the number representing the capacitor C to be measured_xCapacitor ofThe value of the value can be input into a processor of the electronic equipment after the value is obtained, so that the processor can obtain the capacitor C to be detected according to the preset measuring range of the capacitor detection circuit_xThe capacitance value of (2). For example, the capacitance detection circuit has a range of 0-10pF, and the capacitance C to be measured_xThe number of charging and discharging times is 1000 times, if the number of the digital voltage signal median value 1 corresponding to 1000 charging and discharging times is 500 times, the capacitor C to be measured_xThe capacitance value of (d) is 500 ÷ 1000 × 10pF ═ 5 pF.

In this embodiment, the capacitance C to be measured_xWhen the capacitance value is digitized, firstly, the capacitor C to be measured is measured_xPerforming multiple charge transfers on the capacitor C to be measured_xThe voltage conversion module 12 can receive the capacitor C to be measured transferred by the charge transfer module 11 each time charge transfer is performed_xThe charge per discharge; the voltage conversion module 12 is used for accumulating the charge quantity not reaching the critical value Q_maxIn the meantime, the voltage value of the analog voltage signal output by the voltage conversion module 12 is smaller than the voltage threshold, the digital voltage signal output by the comparison module 13 is at a low level, and the charge received by the voltage conversion module 12 is only from the capacitor C to be measured_xWhen the amount of charge accumulated in the voltage conversion module 12 reaches the threshold Q along with the accumulation of charge in the voltage conversion module 12_maxWhen the voltage value of the analog voltage signal output by the voltage conversion module 12 is greater than the voltage threshold, the digital voltage signal output by the comparison module 13 is at a high level, and at this time, the negative charge of the charge amount preset by the charge conversion module 2 is transferred to the voltage conversion module 12, that is, the voltage conversion module 12 receives the capacitor C to be measured at the same time_xThe discharged charges and the negative charges sent by the charge conversion module 2, and the amount of charges stored when the preset amount of charges is greater than or equal to the preset voltage charged by the capacitor Cx to be tested, consume the charges accumulated in the voltage conversion module 12, so that the amount of charges accumulated in the voltage conversion module 12 is less than the critical value Q_maxThen, the voltage value of the analog voltage signal output by the voltage conversion module 12 is smaller than the voltage threshold, the digital voltage signal output by the comparison module 13 is at a low level, and the voltage conversion module 12 continues to accumulate the charges until the accumulated charge amount reaches the critical Q again_maxThen repeat the aboveProcedure until the capacitor C to be measured_xWhen the charge transfer is finished, counting the number of high levels in the digital voltage signal in multiple charge transfers, namely representing the capacitor C to be measured_xThe value of the capacitance of (c).

In this embodiment, after receiving the driving signal, the charge transfer module controls the capacitor to be tested to perform multiple charging and discharging according to the driving signal, and when the capacitor to be tested is charged and discharged each time, the capacitor to be tested is charged to a preset voltage and then releases the stored charge to the voltage conversion module; therefore, after the capacitor to be measured is charged and discharged for many times, quantitative charges can be output to the voltage conversion module for many times, the voltage conversion module can convert the charges into analog voltage signals according to the output voltage corresponding to the amount of the received charges and send the analog voltage signals to the comparison module, the comparison module converts the analog voltage signals into digital voltage signals according to the preset voltage threshold and the received analog voltage signals and inputs the digital voltage signals into the charge conversion module, the charge conversion module can output negative charges with preset charge amount to be fed back to the voltage conversion module when the digital voltage signals are at a high level, then after the capacitor to be measured is charged and discharged for many times, the filtering module can obtain a numerical value representing the capacitance value of the capacitor to be measured according to the digital voltage signals generated after the capacitor to be measured is charged and discharged for many times, the capacitance value of the capacitor to be measured can be digitized without analog circuits such as an analog-, the circuit structure is simple, and the power consumption and the cost are reduced; and the anti-interference capability of the capacitance detection circuit can be improved by increasing the charging and discharging times of the capacitance to be detected.

A second embodiment of the present application relates to a capacitance detection circuit, and the present embodiment is mainly different from the first embodiment in that: the specific structure of a part of modules in the capacitance detection circuit is provided.

In this embodiment, the circuit structure of the charge transfer module 11 can be set according to a required detection mode, which is specifically as follows:

referring to fig. 3, the charge transfer module 11 is applied to a mutual capacitance detection method, and the charge transfer module 11 includes: a first switch SW1, a second switch SW2, and a first power supply V1.

The first power supply V1 is connectedA first end connected to the first switch SW1, a second end of the first switch SW1 connected to the first end of the second switch SW2, a second end of the second switch SW2 connected to GND, and a connection point between the first switch SW1 and the second switch SW2 connected to the capacitor C to be tested_xFirst terminal of (C) capacitor to be measured_xThe control terminal of the first switch SW1 and the control terminal of the second switch SW2 are respectively used for receiving a driving signal (not shown in the figure); the driving signal is a signal sent by a signal generator, and the signal generator may be an RC oscillator, a processor, a crystal oscillator circuit, and the like.

The first switch SW1 is used for testing the capacitance C according to the driving signal_xClosed during discharge and in the capacitor C to be measured_xAnd is disconnected during charging.

The second switch SW2 is used for testing the capacitance C according to the driving signal_xIs disconnected during discharging and is in the capacitor C to be measured_xAnd is closed during charging.

Referring to the timing chart of fig. 4, the first switch SW1 is turned on when the driving signal is at a high level and turned off when the driving signal is at a low level after receiving the driving signal; the second switch SW2 is opened when the drive signal is at a high level and closed when the drive signal is at a low level after receiving the drive signal. Therefore, in each period of the driving signal, when the driving signal is at a high level, the first switch SW1 is opened, the second switch SW2 is closed, and the capacitor C to be tested is connected to the second switch SW2_xConnected to GND and capacitor C to be measured_xThe charges in the charge storage unit are all released, and the charge quantity is 0; when the driving signal is at low level, the first switch SW1 is closed, the second switch SW2 is opened, and at the moment, the capacitor C to be tested is connected_xIs connected to a first power supply V1 and is charged to a preset voltage V_txCapacitor C to be measured_xAmount of stored charge Q_Cx＝V_tx*C_xThen, when the driving signal is at the high level in the next period, the first switch SW1 is closed, the second switch SW2 is opened, and the capacitor C to be tested is connected_xThe charge stored in (b) is all released to the voltage conversion module 12.

Referring to fig. 5, the charge transfer module 11 is applied to a self-capacitance detection method, and the charge transfer module 1 includes a third switch SW3, a fourth switch SW4 and a second power source V2.

The second power source V2 is connected to the first end of the third switch SW3, the second end of the third switch SW3 is connected to the first end of the fourth switch SW4, the second end of the fourth switch SW4 is connected to the voltage conversion module 12, and the connection position of the third switch SW3 and the fourth switch SW4 is connected to the capacitor C to be tested_xFirst terminal of (C) capacitor to be measured_xAnd the control terminal of the third switch SW3 and the control terminal of the fourth switch SW4 are respectively used for receiving the driving signal.

The third switch SW3 is used for being disconnected when the capacitor to be tested discharges according to the driving signal and for being disconnected when the capacitor to be tested C_xAnd is closed during charging.

The fourth switch SW4 is used for being closed when the capacitor to be tested discharges according to the driving signal and is arranged on the capacitor C to be tested_xAnd is disconnected during charging.

In this embodiment, referring to fig. 4, the driving signal may also be a clock signal, and after receiving the driving signal, the third switch SW3 is turned on when the driving signal is at a high level and turned off when the driving signal is at a low level; the fourth switch SW4 is turned off when the drive signal is at a high level and turned on when the drive signal is at a low level after receiving the drive signal. Therefore, in each period of the driving signal, when the driving signal is at a high level, the third switch SW3 is closed, the fourth switch SW4 is opened, and at the moment, the capacitor C to be tested is connected_xIs connected to a second power supply V2 and is charged to a preset voltage V_txCapacitor C to be measured_xAmount of stored charge Q_Cx＝V_tx*C_xWhen the driving signal is at a low level, the third switch SW3 is turned off, the fourth switch SW4 is turned on, and the capacitor C to be tested is connected_xConnected to GND and capacitor C to be measured_xThe electric charges in (2) are all released, and the electric charge amount is 0.

Referring to fig. 6, the voltage conversion module 12 includes: operational amplifier AMP, first reference capacitance C_ref1And a fifth switch SW 5.

The charge transfer module 11 and the charge conversion module 2 are respectively connected to the inverting input terminal of the operational amplifier AMPThe positive phase input end of the first reference capacitor C is grounded to the GND_ref1Are respectively connected to the inverting input terminal of the operational amplifier AMP and the output terminal of the operational amplifier AMP, and both ends of the fifth switch SW5 are respectively connected to the first reference capacitor C_ref1And a control terminal of the fifth switch SW5 is for receiving a reset signal.

The fifth switch SW5 is used to keep closed for a preset time period when receiving a reset signal. Specifically, referring to the waveform diagram of the reset signal in fig. 4, the capacitance detection circuit detects the capacitance C to be detected_xBefore the detection is performed, the reset signal is input to the fifth switch SW5, the fifth switch SW5 is in a closed state when the reset signal is at a high level, and the duration of the high level of the reset signal is a preset duration so that the fifth switch SW5 is kept in the closed state for the preset duration, thereby releasing the first reference capacitor C_ref1All charges at both ends; the fifth switch SW5 is in an off state when the reset signal is at a low level, so that after a preset time period, the fifth switch SW5 is turned off, and then the capacitance detection circuit can detect the capacitance C to be detected_xAnd (6) detecting.

In-pair capacitor C to be measured_xWhen detecting, the capacitor C to be detected_xMultiple charge transfers, hereinafter with Q_{Product of large quantities}Representing the amount of charge received by the operational amplifier AMP, the operational amplifier AMP output voltage Vout Q_{Product of large quantities}/C_ref1When the output voltage Vout of the operational amplifier AMP is less than a predetermined voltage threshold V_xThe output of the comparison module 13 is 0, and only the capacitor C to be measured is present_xThe released charges are transferred to the operational amplifier AMP, and as the amount of charges received by the operational amplifier AMP increases, the output voltage Vout of the operational amplifier AMP increases gradually until Vout is greater than the preset voltage threshold V in the comparing module 13_xAt this time, the operational amplifier AMP receives the charge amount Q_{Product of large quantities}Reaches a critical value Q_max，Q_max＝C_ref1*V_xThe output of the comparing module 13 changes from 0 to 1, and the charge converting module 2 outputs negative charge Q of a predetermined charge amount₄To the operational amplifier AMP, the output Vout ═ (Q) of the operational amplifier AMP_{Product of large quantities}-Q₄)/C_ref1(ii) a After a plurality of charge transfers, the output Vout Q of the operational amplifier AMP_Cx/C_ref1+ Vout ', where Vout' represents the output of the operational amplifier AMP at the previous charge transfer.

It should be noted that, in the embodiment, the function of the voltage conversion module 12 is implemented by one circuit in fig. 6, but not limited thereto, please refer to fig. 7, the voltage conversion module 12 includes a summing submodule 121, an integrating submodule 122 and a conversion submodule 123 connected in sequence, and the summing submodule 121 is connected to the charge transfer module 11 and the charge conversion module 2 respectively. The summing submodule 121 is configured to calculate an algebraic sum of received charges, the integrating submodule 122 is configured to capture charges output by the summing submodule 121 and sum the charges, and the converting submodule 123 is configured to convert the charges output by the integrating submodule 122 into an analog voltage signal.

In this embodiment, referring to fig. 8, the comparing module 13 includes: the voltage comparator 131 and the first flip-flop 132, and the first flip-flop 132 may be a D flip-flop (for example).

A positive phase input end of the voltage comparator 131 is connected to the voltage conversion module 12, an inverted phase input end of the voltage comparator is grounded GND, an output end of the voltage comparator 131 is connected to a first input end of the first flip-flop 132, a second input end of the first flip-flop 132 is used for receiving a driving signal, and an output end of the first flip-flop 132 is connected to the filtering module 3; the driving signal may be the clock signal in fig. 4.

The voltage comparator 131 is configured to output a high level when the voltage value of the analog voltage signal is greater than the voltage threshold, and output a low level when the voltage value of the analog voltage signal is less than the voltage threshold.

The first flip-flop 132 is configured to output the digital voltage signal with the current level of the voltage comparator 131 when the driving signal is at a rising edge, and maintain the level of the output digital voltage signal unchanged when the driving signal is at a falling edge. That is, the first flip-flop 132 takes the current level of the voltage comparator 131 as the level of the output digital voltage signal when the driving signal is at the high level; the first flip-flop 132 keeps the level of the output digital voltage signal unchanged when the driving signal is at a low level.

Compared with the first embodiment, the present embodiment provides specific structures of the charge transfer module, the voltage conversion module and the comparison module in the capacitance detection circuit.

A third embodiment of the present application relates to a capacitance detection circuit, and the main differences of this embodiment with respect to the second embodiment are as follows: a specific structure of a charge conversion module is provided.

In this embodiment, referring to fig. 9, the charge conversion module 2 includes: a logic controller 21 and a charge output submodule 22. A first terminal of the logic controller 21 is connected to the comparing module 13, and a second terminal of the logic controller 21 is connected to the voltage converting module 12 through the charge output submodule 22.

The logic controller 21 is configured to control the charge output submodule 22 to output negative charges of a predetermined charge amount to the voltage conversion module 12 when the digital voltage signal is at a high level.

In one example, referring to fig. 10, the charge output submodule 22 includes a sixth switch SW6, a seventh switch SW7, an eighth switch SW8, a ninth switch SW9, a third power supply V3 and a second reference capacitor C_ref2。

A first terminal of the sixth switch SW6 is connected to the voltage conversion module, a second terminal of the sixth switch SW6 is connected to a first terminal of the eighth switch SW8, a second terminal of the eighth switch SW8 is grounded, and a connection point of the sixth switch SW6 and the eighth switch SW8 is connected to the second reference capacitor C_ref2A first terminal of the seventh switch SW7 is connected to the third power supply V3, a second terminal of the seventh switch SW7 is connected to a first terminal of the ninth switch SW9, a second terminal of the ninth switch SW9 is grounded, and a junction of the seventh switch SW7 and the ninth switch SW9 is connected to the second reference capacitor C_ref2A second end of (a); the control terminal of the sixth switch SW6, the control terminal of the seventh switch SW7, the control terminal of the eighth switch SW8, and the control terminal of the ninth switch SW9 are connected to the logic controller 21, respectively.

The logic controller 21 is used for controlling the sixth switch SW6 and the ninth switch SW9 to be turned off and controlling the seventh switch to be turned on when the digital voltage signal is at a high levelThe switch SW7 and the eighth switch SW8 are both closed, and the second reference capacitor C is turned on_ref2A charged reference voltage V connected to a third power supply V3_ref2A second reference capacitor C_ref2Amount of stored charge Q_ref2＝-V_ref2*C_ref2I.e. a predetermined amount of charge, and a second reference capacitor C_ref2The stored charge is discharged to the voltage conversion module 12.

The logic controller 21 is configured to control the sixth switch SW6 and the ninth switch SW9 to be closed, and control the seventh switch SW7 and the eighth switch SW8 to be opened, and control the second reference capacitor C to be at a low level_ref2Ground GND, a second reference capacitor C_ref2The stored charge is entirely discharged to ground.

The present embodiment provides a specific structure of the charge conversion module, compared to the first embodiment.

A fourth embodiment of the present application relates to a capacitance detection circuit, and the main differences of this embodiment with respect to the first embodiment are as follows: referring to fig. 11, the capacitance detection circuit further includes a decimation module 4. The comparison module 13 is connected to the filtering module 3 via the decimation module 4.

The decimation module 4 is configured to output the digital voltage signal within a preset time period to the filtering module 3.

In one example, the decimation block 4 is an and circuit; the first input end of the AND gate circuit is connected to the comparison module, the output end of the AND gate circuit is connected to the filtering module 3, the second input end of the AND gate circuit is used for receiving the output control signal, and the time length of the output control signal in a high level in one period is a preset time period. That is, referring to fig. 12, the output control signal is a periodic signal, and in one period of the output control signal, the output control signal is at a high level in a preset time period T, so that a digital voltage signal in the preset time period T can be extracted and input to the filtering module 3, and the filtering module 3 can obtain a value representing a capacitance value of the capacitor to be measured in the period according to the digital voltage signal in the preset time period T; therefore, the value of the capacitance value of the capacitor to be measured can be periodically acquired.

In an example, referring to fig. 13, the filtering module 3 includes a counter 31 and a second flip-flop 32, and the second flip-flop 32 may be a D flip-flop.

The comparing module 13 is connected to an input terminal of the counter 31, an output terminal of the counter 31 is connected to a first input terminal of the second flip-flop 32, and a second input terminal of the second flip-flop 32 is configured to receive the output control signal (please refer to fig. 12).

The driving end of the counter 31 is configured to receive a driving signal (please refer to fig. 4), and the counter 31 is configured to increment a current count value by 1 when the driving signal is at a rising edge and the digital voltage signal is at a high level.

The second flip-flop 32 is configured to output a count value of the counter 31 as a representation of the capacitor C to be measured when the output control signal is at a rising edge_xThe value of the capacitance of (c).

In this embodiment, the counter 31 counts when the driving signal is at a high level, and adds 1 to the count value when the digital voltage signal is at a high level, and the count value is unchanged when the digital voltage signal is at a low level, and the second flip-flop 32 outputs the count value accumulated by the counter 31 as the representation of the capacitor C to be measured when the output control signal is at a rising edge_xAnd clears the count value of the counter 31.

Compared with the first embodiment, the embodiment adds the extraction module in the capacitance detection circuit, so that the capacitance to be detected can be periodically detected, and the power consumption is reduced.

A fifth embodiment of the present application relates to a sensor, which may be a capacitive sensor, which may be applied to an electronic device, the sensor including the capacitance detection circuit according to any one of the first to fourth embodiments.

The sixth embodiment of the present application relates to a chip, which may be a capacitance detection chip, and which may be applied to an electronic device, and the chip includes the capacitance detection circuit according to any one of the first to fourth embodiments.

A seventh embodiment of the present application relates to an electronic device, including the capacitance detection circuit in any one of the first to fourth embodiments, where the electronic device is, for example, a mobile phone, a tablet computer, or the like.

In one example, the electronic device further includes a processor, where the processor is configured to obtain a capacitance value of the capacitor to be detected according to a value, output by the capacitance detection circuit, that represents the capacitance value of the capacitor to be detected; specifically, the capacitor C to be measured is obtained according to the preset measuring range of the capacitor detection circuit_xThe capacitance value of (2). For example, the capacitance detection circuit has a range of 0-10pF, and the capacitance C to be measured_xThe number of charging and discharging times is 1000 times, if the number of the digital voltage signal median value 1 corresponding to 1000 charging and discharging times is 500 times, the capacitor C to be measured_xThe capacitance value of (d) is 500 ÷ 1000 × 10pF ═ 5 pF.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the present application, and that various changes in form and details may be made therein without departing from the spirit and scope of the present application in practice.