阅读说明：本技术 使用线性反馈移位寄存器的紧凑时间戳系统以及相关系统和方法 (Compact time stamping system using linear feedback shift registers and related systems and methods ) 是由 J·萨奇斯 于 2019-03-06 设计创作，主要内容包括：本发明描述了紧凑时间戳以及相关的方法、系统和设备。编码器被配置为通过对线性反馈移位寄存器(LFSR)的状态进行采样来生成本公开的紧凑时间戳。解码器可被配置为响应于该紧凑时间戳而确定定时信息。(Compact timestamps and related methods, systems, and devices are described. The encoder is configured to generate the compact time stamp of the present disclosure by sampling the state of a Linear Feedback Shift Register (LFSR). The decoder may be configured to determine timing information in response to the compact timestamp.)

1. An encoder for providing timing information for associating groups of data, the encoder comprising:

one or more Linear Feedback Shift Registers (LFSRs) configured to store N bits of LFSR state information for each of a plurality of LFSR states, wherein each of the plurality of LFSR states is associated with timing information;

one or more sample output registers configured to store N of LFSR state sample information for each of a plurality of LFSR state samples_yA bit; and

one or more samplers configured to reduce N bits of LFSR state information to N bits of LFSR state sample information_yA bit.

2. The encoder of claim 1, wherein the one or more samplers comprise digital logic circuitry configured to:

operatively coupling a sampling register unit of the one or more LFSRs to a sample output register unit of the one or more sample output registers, wherein the sampling register unit is a subset of all register units of the one or more LFSRs; and

providing output bits derived from the bits of the sampling register unit to the sample output register unit.

3. The encoder of claim 2, wherein the digital logic circuit is configured to:

performing one or more XOR operations on the bits of the sampling register unit; and

providing one or more results of the XOR operation to the sample output register unit.

4. The encoder of claim 2, wherein the digital logic circuit is configured to provide the output bits to the sample output register cell in response to every d updates of the LFSR, where d is a sampling interval.

5. The encoder of claim 1, wherein the one or more samplers are configured to provide at least m consecutive LFSR state samples, where m x N_y>N, and timing information is recoverable from the at least m consecutive LFSR state samples.

6. The encoder of claim 1, wherein the one or more samplers are configured to provide at least m consecutive LFSR state samples, where m x N_yN, and timing information is recoverable from the at least m consecutive LFSR state samples.

7. The encoder of claim 4, wherein a sampler of the one or more samplers is configured to reduce N bits of LFSR state information to N of LFSR state sample information in response to a sampling matrix_yA bit.

8. According to claimThe encoder of claim 4, wherein the samplers of the one or more samplers are configured to reduce the N bits of LFSR state information to N of LFSR state sample information in response to at least one bit mask_yA bit.

9. The encoder of claim 4, wherein a sampler of the one or more samplers is configured to reduce N bits of LFSR state information to N of LFSR state sample information in response to a Run Length Encoding (RLE) definition_yA bit.

10. The encoder of claim 1, wherein the one or more LFSRs comprise a single LFSR.

11. The encoder of claim 1, wherein the one or more LFSRs comprise at least a first sampling register unit and a second sampling register unit, the one or more sample output registers comprise at least a first sample output register unit and a second sample output register unit, and the one or more samplers comprise at least a first digital logic circuit and a second digital logic circuit, wherein:

the first digital logic circuit operably couples the first sampling register unit to the first sample output register unit; and

the second digital logic circuit operably couples the second sampling register unit to the second sample output register unit.

12. The encoder of claim 11, wherein the one or more samplers are configured to sample the first sampling register unit and the second sampling register unit during the same sampling interval.

13. The encoder of claim 11, wherein a period of the first and second sampling register units of the one or more LFSRs is relatively dominant.

14. The encoder of claim 11, wherein the first digital logic circuit is configured according to a first sampling function and the second digital logic circuit is configured according to a second sampling function different from the first sampling function.

15. The encoder of claim 1, wherein the one or more sample output registers are operably coupled to a data bus configured to receive output bits of the one or more sample output registers.

16. The encoder of claim 15, wherein at least some of the plurality of LFSR states are associated with a transmission interval of a data transmission system, and at least some of the plurality of LFSR state samples at the one or more sample output registers are accessible by the data transmission system.

17. The encoder of claim 15, wherein the received output bits are in a serial bit stream.

18. A method of providing timing information for associated data, the method comprising:

changing N bits of a Linear Feedback Shift Register (LFSR) state in response to one or more of a plurality of event intervals;

reducing N bits of LFSR state information to N of LFSR state sample information in response to the one or more event intervals_yOne bit, where N_y<N; and

LFSR state sample information and event data are provided in response to the one or more event intervals.

19. The method of claim 18, further comprising skipping at least one event interval of the plurality of event intervals, wherein the one or more event intervals comprise a first event interval and a second event interval, and the at least one event interval is between the first event interval and the second event interval.

20. The method of claim 19, wherein skipping at least one event interval comprises skipping a fixed number of event intervals.

21. The method of claim 18, wherein the one or more event intervals comprise at least two consecutive event intervals.

22. The method of claim 18, wherein providing the LFSR state sample information and event data comprises transmitting the LFSR state sample information and event data.

23. The method of claim 18, wherein providing the LFSR state sample information and event data comprises storing LFSR state sample information and data at a record.

24. The method of claim 18, further comprising providing at least m consecutive LFSR state samples, wherein m x N_y>N, and timing information is recoverable from the at least m consecutive LFSR state samples.

25. The method of claim 18, further comprising providing at least m consecutive LFSR state samples, wherein m x N_yN, and timing information is recoverable from the at least m consecutive LFSR state samples.

26. The method of claim 18, further comprising reducing the N bits of the LFSR state information to N of the LFSR state sample information in response to a sampling matrix_yA bit.

27. The method of claim 18, further comprising selecting the selected one of the plurality of cells byReducing the N bits of the LFSR state information to N of the LFSR state sample information_yBit:

masking at least some of the N bits of the LFSR state information in response to one or more bitmasks; and

combining unmasked bits of the N bits of the LFSR state information in response to each masking of the at least some of the N bits of the LFSR state information.

28. The method of claim 27, wherein combining unmasked bits of the N bits of LFSR state information comprises selecting unmasked bits of the N bits of LFSR state information in response to only one bit of LFSR state information being unmasked.

29. The method of claim 27, wherein combining unmasked bits of the N bits of LFSR state information comprises performing one or more XOR operations on the unmasked bits of the N bits of LFSR state information.

30. The method of claim 18, further comprising reducing the N bits of the LFSR state information to N of the LFSR state sample information in response to a run length code (RLE) definition_yA bit.

31. A method of providing timing information for associated data, the method comprising:

changing N of a first Linear Feedback Shift Register (LFSR) state in response to one or more of a plurality of event intervals₁N of bits and second LFSR state₂A bit;

n of LFSR state information in response to the one or more event intervals₁Bit reduction to N for LFSR state sample information_y1One bit, and N of LFSR state information₂Bit reduction to N for LFSR state sample information_y2One bit, where N_y1<N₁And N is_y2<N₂(ii) a And

providing one or more LFSR state samples of reduced LFSR state information in response to the one or more event intervals.

32. The method of claim 31, further comprising skipping at least one event interval of the plurality of event intervals, wherein the one or more event intervals comprise a first event interval and a second event interval, and the at least one event interval is between the first event interval and the second event interval.

33. The method of claim 31, wherein the one or more event intervals comprise at least two consecutive event intervals.

34. The method of claim 31, wherein providing the timing information comprises transmitting the one or more LFSR state samples and data.

35. The method of claim 31, wherein providing the timing information comprises storing the one or more LFSR state samples and data at a data log.

36. The method of claim 31, further comprising N for the LFSR state during the same event interval₁A bit and N of the LFSR state₂The bits are sampled.

37. The method of claim 31, further comprising reducing N of the LFSR state information during different ones of the plurality of event intervals_y1A bit and N of the LFSR state information_y2A bit.

38. The method of claim 31, further comprising:

providing the one or more first sample output registers with the slave N_y1One or more first output bits derived from the plurality of sample bits; and

providing the one or more second sample output registers with the slave N_y2One or more second output bits derived from the plurality of sample bits.

39. The method of claim 31, further comprising modifying the N according to a first sampling function_y1Sampling bits and modifying the N according to a second sampling function_y2A sampling bit, wherein the first sampling function is different from the second sampling function.

40. A decoder for recovering timing information for associated data, the decoder comprising:

a memory configured to store event reports associated with a plurality of event intervals, each of the event reports comprising at least data and N_yBit timing data;

a processor configured to:

in response to N of the number m_yBit timing data to recover N bit timing data, where N_yIs composed of<N; and

timing information is determined in response to the recovered N-bit timing data.

41. The decoder of claim 40, wherein the event report is an event record and the event interval is associated with an operation of an embedded system or a time period of operation of the embedded system.

42. The decoder of claim 40, wherein the event report is a message and the event interval is a data transmission interval.

43. The decoder of claim 40 wherein the processor is configured to recover the N-bit timing data and to determine the timing information in response to a priori information about a reporting system that generated the event report.

44. The decoder according to claim 43, wherein the processor is further configured to use more or less a priori information in response to a confidence that the reporting system is operating according to the a priori information.

45. The decoder according to claim 44, wherein the processor is configured to perform a confidence increasing operation selected to increase the confidence that the reporting system is operating according to the a priori information.

46. The decoder according to claim 45, wherein the confidence increasing operation comprises N other than the number m_yOne or more confidence timing data are used in addition to the bit timing data.

47. The decoder according to claim 45, wherein the confidence increasing operation comprises using a stored N_yBit timing data, and using stored N_yBit timing data replacing said number m of N_yAt least one N of bit timing data_yThe bit timing data.

48. The decoder according to claim 43, wherein the processor is configured to discard the received N in response to failing to increase the confidence that the reporting system operates according to the a priori information within a defined period_yAt least some N of the bit timing data_yThe bit timing data.

49. The decoder of claim 48, wherein the a priori information comprises one or more of redundancy, reporting intervals, past history, and combinations thereof.

50. The decoder of claim 49, wherein the past history includes previously received timing data.

51. The decoder of claim 40 wherein the processor is configured to respond to a discrete logarithm and a plurality of received N_yBit timing data to determine timing information.

52. The decoder of claim 40 wherein the processor is configured to provide a released report to a data consumer, the released report including data of the received report and the N corresponding to the received report_yTiming information of the bit timing data.

53. The decoder of claim 40, wherein the memory is configured to store one or more event log files comprising the event report.

54. The decoder of claim 40, further comprising a communication interface configured to receive a message, wherein the message comprises the event report.

55. A method of recovering timing information for associated data, the method comprising:

receiving and storing event reports, each of the event reports including data and N_yBit timing data;

in response to N of the number m_yBit timing data to recover at least one N bit timing data, where N is>N_y(ii) a And

timing information is determined in response to the recovered N-bit timing data.

56. The method of claim 55, wherein receiving and storing an event report comprises retrieving a record from an event log file, the record associated with an operation of an embedded system or a time period of operation of the embedded system.

57. The method of claim 55, wherein receiving and storing an event report comprises receiving and storing a message received via a data transmission.

58. The method of claim 55, further comprising recovering the at least one N-bit timing data and determining at least one timing information in response to a priori information about a data transmission system.

59. The method of claim 58, further comprising using more or less a priori knowledge about the data transmission system in response to a confidence that the data transmission system is operating according to the a priori information.

60. The method of claim 59, further comprising performing a confidence increase operation selected to increase the confidence associated with the data transmission.

61. The method of claim 60, further comprising using N other than said number m_yOne or more confidence timing data other than the bit timing data to perform the confidence increase operation.

62. The method of claim 61, wherein performing the confidence increase operation comprises:

at least one received N_yBit timing data and pre-calculated N_yBit timing data matching; and

selecting N from said precomputed_yBit timing data is associated with pre-computed N-bit timing data.

63. The method of claim 60, further comprising discarding the received N upon failing to increase the confidence that the data transmission system operates according to the a priori information within a defined period_yAt least some N of the bit timing data_yThe bit timing data.

64. In accordance with the method of claim 55,also included is N responsive to the discrete logarithm and the plurality of receptions_yBit timing data to determine timing information.

65. The method of claim 55, further comprising providing a released message to a data consumer, the released message comprising a data payload of the received message and the N corresponding to the received message_yTiming information of the bit timing data.

66. A method for associating monitoring data about a monitored system with system data from the monitored system, the method comprising:

receiving system data messages, each system data message comprising system data and first timing data;

receiving monitoring data messages, wherein each monitoring data message comprises monitoring data and second timing data;

recovering the first timing information in response to the first timing data received in one or more of the received system data messages;

recovering second timing information in response to second timing data received in one or more of the received monitor data messages; and

associating at least one system data with at least one monitoring data in response to the first timing information and the second timing information.

Technical Field

Embodiments of the present disclosure relate generally to timestamps for data transmission, and more particularly, to compact timestamps generated from linear feedback shift registers.

Background

Accurate time stamping of transmitted data (e.g., from a source microcontroller or microprocessor to a target host) is a common task during data recording from a source to a host. In a periodically sampled data system, such as a motor drive or battery charger, the system typically executes code in control cycles at a fixed rate and transmits samples of the data (e.g., voltage, current, status flags, etc.) used in a given control cycle, along with some correlation of the control cycle (also referred to as a "tick count") in which the data occurs.

Some data systems use the state of a Linear Feedback Shift Register (LFSR) to encode and recover a count that can be used to determine timing data. For example, FIG. 1 shows a 12-bit LFSR 100 in a Galois configuration, consisting of a series of shift register cells, each storing one bit. In each LFSR update cycle, each cell receives its input from the content of the previous cell, here shifted from right to left. When the system is clocked, the contents of all cells are shifted to the left. Bit not in non-tapped cellVariably shifted one position to the left. The bits in the cells that are taps are XOR' ed with the bits in the last (i.e., the cell that holds the most significant bit) cell 102 and the result is stored in the next location. The new bit in last cell 102 is the next input bit for the XOR operation. The choice of whether to perform the XOR is determined by LFSR taps 104, 106 and 108, which correspond to non-zero terms in the characteristic polynomial of the LFSR. For example, FIG. 1 shows a polynomial x having a characteristic¹²+x⁶+x⁴A 12-bit LFSR 100 of + x +1, which has the binary representation "1000001010011".

LFSR 100 is characterized by a primitive polynomial having a period of 2¹²Maximum length LFSR of 1 — 4095, covering all values except the all-zero pattern. If the LFSR 100 is implemented on a sampled data system where the initial LFSR state under token technology 0 is "000000000001" and the LFSR state is sent to the host under any subsequent token, the host may recover the token count using a discrete logarithm calculation based on the LFSR state. The larger the LFSR size, the longer the period. The LFSR 100 may be more compactly represented as LFSR 110, with the XOR gates not shown before the taps. Notably, the LFSR 100 and the LFSR 110 are different representations of the same LFSR.

In the case where the data system transmits a single bit (e.g., the input bit in the last cell 102) at each tick count, if consecutive samples of d single bits are received without missing samples, the N-bit LFSR state may be reconstructed after receiving N consecutive output bits.

The inventors of the present disclosure should now appreciate that in resource-limited systems, there is a tradeoff between communication speed and the time that a processor can spend for activities other than preparing and transmitting data, such as transmitting a token count or timestamp. Furthermore, for smaller data packets (e.g., about 100 bytes or less), the payload has limited space, so if more bytes are used to time stamp, fewer bytes can be used for actual data, thereby affecting the communication bandwidth of the data transmission system. Thus, for some systems, the size of the LFSR state, which additionally has sufficient periodicity, makes it unsuitable for timestamping.

Drawings

While the present disclosure concludes with claims particularly pointing out and distinctly claiming one or more embodiments, various features, objects and advantages of the embodiments of the disclosure may be readily ascertained by one of ordinary skill in the art from the following detailed description taken in conjunction with the accompanying drawings:

fig. 1 shows a linear feedback shift register in an encoding arrangement according to the beginning of the art.

Fig. 2A illustrates a functional block diagram of a timestamp recovery system that can be used with a data transmission system according to one or more embodiments of the present disclosure.

Fig. 2B illustrates a functional block diagram of an LFSR encoder in accordance with one or more embodiments of the present disclosure.

Fig. 2C illustrates a sampling function implemented as a selection and XOR gate in accordance with one or more embodiments of the present disclosure.

Fig. 3A shows a simplified block diagram of a software LFSR decoder according to one or more embodiments of the present disclosure.

Fig. 3B illustrates a simplified block diagram of a software LFSR decoder and state recovery logic according to one or more embodiments of the present disclosure.

Fig. 3C, 3D, and 3E illustrate simplified state transition diagrams of state recovery logic according to one or more embodiments of the present disclosure.

Fig. 3F, 3G, 3H, and 3I illustrate simplified state transition diagrams of state recovery logic according to one or more embodiments of the present disclosure.

Fig. 3J, 3K, and 3L illustrate simplified state transition diagrams of state recovery logic according to one or more embodiments of the present disclosure.

Fig. 4A and 4B illustrate tables of exemplary operations to restore a logical state machine in accordance with one or more embodiments of the present disclosure.

Fig. 5 illustrates a functional block diagram of an LFSR encoder with a sampling function configured for bit selection in accordance with one or more embodiments of the present disclosure.

Fig. 6A illustrates a functional block diagram of a multi LFSR state encoder according to one or more embodiments of the present disclosure.

Fig. 6B illustrates a functional block diagram of a dual LFSR state encoder according to one or more embodiments of the present disclosure.

Fig. 6C illustrates a flow diagram of a decoding process for timestamps generated by a dual LFSR encoder in accordance with one or more embodiments of the present disclosure.

Fig. 7 illustrates a functional block diagram of a data system in accordance with one or more embodiments of the present disclosure.

Fig. 8 illustrates a functional block diagram of a data system in accordance with one or more embodiments of the present disclosure.

Detailed Description

In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific examples in which embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosure. However, other embodiments may be utilized, and structural, material, and process changes may be made without departing from the scope of the present disclosure.

The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations which are employed to describe the embodiments of the present disclosure. The drawings presented herein are not necessarily drawn to scale. For the convenience of the reader, like structures or components in the various drawings may retain the same or similar numbering; however, similarity in numbering does not imply that the structures or components must be identical in size, composition, configuration, or any other property.

It will be readily understood that the components of the embodiments, as generally described herein, and illustrated in the figures, could be arranged and designed in a wide variety of different configurations. Thus, the following description of various embodiments is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments. While various aspects of the embodiments may be presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The following description may include examples to assist those of ordinary skill in the art in practicing the disclosed embodiments of the present invention. The use of the terms "exemplary," "by way of example," and "e.g.," mean that the associated description is illustrative, and although the scope of the disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the embodiments or the scope of the disclosure to the specified components, steps, features, functions, or the like.

Moreover, the particular embodiments shown and described are merely examples and should not be taken as the only way to implement the present disclosure unless otherwise indicated herein. Elements, circuits, and functions may be shown in block diagram form in order not to obscure the present disclosure in unnecessary detail. Rather, the particular embodiments shown and described are merely exemplary and should not be taken as the only way to implement the present disclosure unless otherwise indicated herein. Additionally, block definitions and logical partitioning between individual blocks are examples of particular embodiments. It will be apparent to those of ordinary skill in the art that the present disclosure may be practiced with many other partitioning solutions. In most cases, details concerning timing considerations and the like have been omitted where such details are not necessary to obtain a complete understanding of the present disclosure and are within the abilities of persons of ordinary skill in the relevant art.

Those of ordinary skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the specification may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some of the figures may show signals as a single signal for clarity of presentation and description. It will be understood by those of ordinary skill in the art that the signals may represent a signal bus, where the bus may have a variety of bit widths, and the present disclosure may be implemented on any number of data signals, including a single data signal.

The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a special purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor, which may also be referred to herein as a host processor or simply a host, may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a special-purpose computer when it is configured to execute computing instructions (e.g., software code) related to embodiments of the present disclosure.