阅读说明：本技术 一种逆阻型门极换流晶闸管及其制造方法 (Reverse-resistance type gate pole commutation thyristor and manufacturing method thereof ) 是由 陈勇民 戴小平 陈芳林 蒋谊 唐龙谷 徐焕新 于 2019-04-23 设计创作，主要内容包括：本发明公开了一种逆阻型门极换流晶闸管及其制造方法。晶闸管的层状结构竖直方向自下而上依次包括：P<Sup>+</Sup>阳极发射区、P阳极区、N<Sup>-</Sup>基区、P基区、P<Sup>+</Sup>基区、半埋于所述P<Sup>+</Sup>基区顶部的多个N+发射区；其中,在从正上方俯视晶闸管的方向上,多个N<Sup>+</Sup>发射区在以晶闸管的芯片中心为圆心的多个同心圆内沿圆弧均匀排布；P<Sup>+</Sup>阳极发射区包括P<Sub>1</Sub><Sup>+</Sup>阳极发射区和水平方向环绕P<Sub>1</Sub><Sup>+</Sup>阳极发射区的P<Sub>2</Sub><Sup>+</Sup>阳极发射区,所述P<Sub>2</Sub><Sup>+</Sup>阳极发射区位于所述P<Sup>+</Sup>阳极发射区的在远离门极引出端位置的N<Sup>+</Sup>发射区下方的区域以及所述P<Sup>+</Sup>阳极发射区的在所述晶闸管边缘终端位置的区域。(The invention discloses a reverse-resistance type gate commutated thyristor and a manufacturing method thereof. The vertical direction of the lamellar structure of thyristor includes from bottom to top in proper order: p + Anode emitter region, P anode region, N ‑ Base region, P + Base region semi-buried in the P + A plurality of N + emitter regions at the top of the base region; wherein, in the direction of overlooking the thyristor from the right top, a plurality of N + The emitting regions are uniformly distributed along arcs in a plurality of concentric circles taking the center of a chip of the thyristor as the center of a circle; p + The anode emission region comprises P 1 + The anode emission region surrounds P in the horizontal direction 1 + P of anode emission region 2 + Anode emitter region, andp is 2 + An anode emission region is positioned in the P + N of anode emitter region at position far away from gate lead-out end + Area under the emission area and the P + A region of the anode emitter region at the thyristor edge termination location.)

1. The utility model provides a contrary formula of hindering gate pole change of current thyristor which characterized in that, the vertical direction of the lamellar structure of thyristor includes from bottom to top in proper order: p⁺Anode emitter region, P anode region, N^-Base region, P⁺Base region and plurality of N⁺An emission region;

wherein the plurality of N is in a direction looking down the thyristor from directly above⁺The emitting regions are uniformly distributed in circles along the circumferences with different diameters and taking the center of a chip of the thyristor as the center of a circle; the P is⁺The anode emission region comprises P₁ ⁺An anode emission region horizontally surrounding the P₁ ⁺P of anode emission region₂ ⁺An anode emission region; wherein, the P₂ ⁺An anode emission region is positioned in the P⁺N of anode emission region far from gate leading-out position⁺The area corresponding to the lower part of the emitting area and the P⁺A region of the anode emitter region at the thyristor edge termination location.

2. The reverse-resistance type gate commutated thyristor according to claim 1,

the P is₂ ⁺The doping concentration of the anode emission region is lower than that of the P₁ ⁺Doping concentration of the anode emitter region.

3. The reverse-resistance gate-commutated thyristor according to claim 1 or 2, further comprising:

a gate electrode located at said P⁺The base region top is not covered by the N⁺On the part covered by the emitting area; wherein the gate leading-out terminal is positioned at the center of the thyristor chip and at the edge of the thyristorA middle position between the terminal positions, or a position adjacent to the edge terminal of the thyristor;

a cathode located at the N⁺The top of the emitting region;

an anode located at the P⁺And the bottom of the anode emission region.

4. The reverse-resistance type gate commutated thyristor according to claim 3,

when the gate leading-out terminal is positioned at the middle position between the chip center position of the thyristor and the edge terminal position of the thyristor, the P is₂ ⁺An anode emission region is positioned in the P⁺1-3 circles of N of anode emission region farthest from chip center position of thyristor⁺Area under the emission area and the P⁺A region of the anode emitter region at the thyristor edge termination location.

5. The reverse-resistance type gate commutated thyristor according to claim 3,

when the gate terminal is adjacent to the edge terminal of the thyristor, P is₂ ⁺An anode emission region is positioned in the P⁺The anode emission region is 1 to 3 circles N nearest to the center of the thyristor chip⁺Area under the emission area and the P⁺A region of the anode emitter region at the thyristor edge termination location.

6. A manufacturing method of a reverse-resistance type gate commutated thyristor is characterized by comprising the following steps:

providing N^-A type single crystal silicon substrate;

to the N^-Carrying out P-type impurity pre-deposition on the upper surface and the lower surface of the type monocrystalline silicon substrate, and carrying out high-temperature diffusion on impurities to form a P base region and a P anode region;

injecting P-type doping impurities into the upper surface of the P base region and the preset injection window of the P anode region respectively, and performing high-temperature diffusion on the injected doping impuritiesForm P⁺Base region and P₁ ⁺An anode emission region;

at the P⁺Forming a plurality of N on the top of the base region⁺An emission region; wherein the plurality of N is in a direction looking down the thyristor from directly above⁺The emitting regions are uniformly distributed in circles along the circumferences with different diameters and taking the center of a chip of the thyristor as the center of a circle;

for the P₁ ⁺Implanting again P-type dopant impurity into a designated region around the anode emitter region, and performing high-temperature diffusion on the implanted dopant impurity to form P₂ ⁺An anode emission region; wherein, the P₂ ⁺An anode emission region is positioned in the P⁺N of anode emission region far from gate leading-out position⁺The area corresponding to the lower part of the emitting area and the P⁺A region of the anode emitter region at the thyristor edge termination location.

7. The manufacturing method according to claim 6, further comprising the steps of:

for the plurality of N⁺Emission area and the N⁺The middle part of the emitting area is subjected to surface passivation isolation;

depositing a metal electrode layer on the surface of the passivation isolation, and carrying out etching and annealing treatment to form a metal electrode layer positioned on the P⁺The base region top is not covered by the N⁺A gate electrode on the part covered by the emitter region, located at said N⁺A cathode on top of the emitter region; the P is₁ ⁺An anode emission region and said P₂ ⁺Depositing a metal electrode layer on the lower surface of the anode emission region, and annealing to form the P₁ ⁺Anode emission region and P₂ ⁺And an anode at the bottom of the anode emission region.

8. The method according to claim 6 or 7, wherein the N is subjected to a closed tube aluminum expanding process in a low vacuum furnace tube saturated aluminum source atmosphere^-Aluminum diffusion is carried out on the upper surface and the lower surface of the type monocrystalline silicon substrate to form the P anodeRegion and P⁺And a base region.

9. The manufacturing method according to claim 6 or 7, wherein the N is formed by⁺An emission area:

at the P⁺Carrying out high-temperature oxidation promotion on N-type impurities on the upper surface of the base region, wherein P is⁺N is formed on the upper surface of the base region⁺An impurity diffusion layer and an oxide layer;

photoetching the oxide layer to form N which is uniformly arranged in a radial concentric manner⁺A pattern of emission areas;

to the N⁺Selectively grooving the emitting region pattern to form N which is uniformly arranged concentrically and radially⁺An emission area.

10. The method of manufacturing of claim 9, wherein the selective trenching is performed using a chemical wet etch or a dry etch process.

Technical Field

The invention relates to the technical field of power semiconductor devices, in particular to a reverse-resistance type gate commutated thyristor and a manufacturing method thereof.

Background

A Gate Commutated Thyristor (GCT) is a semiconductor device with ultra-high power capacity in the field of power electronics. The main structure of the conventional reverse-resistance GCT chip in the longitudinal direction comprises four PNPN layers (as shown in FIG. 1), which are subdivided into a P + transparent emitting anode and an N + transparent emitting anode according to the doping degree^-Base region, P⁺Short base region and N⁺The emitter region (also known as cathode sliver). The device has 3 PN junctions, and J is arranged along the direction from the anode to the cathode₁Junction (reverse blocking main junction), J₂Junction (positive blocking main junction) and J₃Junction (gate cathode junction). For GCT tube cores with different diameters, the cathode comb strips are generally divided into 2-16 circles, and are radially arranged in a wafer in a sector arc or circumference uniform arrangement mode. According to the magnitude of the GCT turn-off current, the GCT gate leading-out part is arranged at the center of the wafer, namely called a central gate, or is arranged at the middle or the periphery of the wafer, namely called a middle ring gate or an edge ring gate.

For large diameter reverse-blocking IGCTs, such as 6 inch IGCTs, the safe operating area does not scale as its area increases. For the standard IGCT structure, according to the experimental results reported by the published literature, the current turn-off capability of the device is only increased by 4 times when the effective area of the device is increased by 10 times, and the maximum conversion power density is obviously reduced. Because the large-diameter reverse-resistance IGCT generally adopts the middle annular gate pole, and the gate pole impedances close to and far from the contact area of the gate pole are slightly different, small time difference exists among IGCT thyristor units during turn-off, so that the current crowding phenomenon occurs in the contact area far from the gate pole. When the device is recovered in the reverse direction, the same phenomenon can be generated at the position near the terminal, and the expansion of the safe working area of the device is further limited.

For the conventional reverse-resistance GCT, the following two common failure phenomena are mainly existed:

1) during the forward turn-off of the GCT, excess carriers (holes) generated by dynamic avalanche accumulate under the GCT cathode comb strip, and when the accumulation is enough, the junction of J3 can be driven to be turned on, thereby causing the turn-off failure of the device. In the turn-off process of the large-size GCT chip, because the gate resistance of the region far away from the GCT gate contact is large, the turn-off is finished later, and the current aggregation phenomenon is easy to occur. On the other hand, N^-The carriers generated by base dynamic avalanche act as base current for the pnp transistor contained in the device, which is equivalent to a forward feedback current gain mechanism for an avalanche transistor, thus further accelerating current collection in this region, and therefore the following may occur: when the current under one or more cathode bars is high enough, the thyristor can be triggered to start to turn back on, resulting in a failure to turn off. Therefore, an important feature of the GCT chip under this mechanism is that the failure sites are often distributed far away from the gate lead-out region.

2) GCT is in the process of reverse blocking recovery turn-off, and a large amount of storage is injected into N in the on state^-Base carrier, electron passing through N⁺The region flows to the cathode, and the holes flow to the anode, so that a high electric field exists at the terminal of the chip mesa in the reverse recovery stage, and a large number of carriers stored at the terminal are not easy to be extracted to the anode, which also easily causes the avalanche failure of the device.

Currently, in the prior art, the following technique is generally adopted to improve the turn-off capability of the GCT and avoid the turn-off failure.

1) Non-uniform irradiation technique

The local region of the GCT far away from the gate pole is irradiated with higher dose, so that the service life of local carriers is reduced, the current density distribution of the region in an on-state is reduced, and the range of an IGCT safe working area is enlarged. The transverse carrier injection efficiency of the GCT chip is adjusted through non-uniform irradiation, and the phenomenon of chip avalanche breakdown caused by current crowding in a region far away from a gate contact area is avoided in the turn-off process. Although this technique improves the turn-off capability of the device, excessive irradiation increases the blocking leakage current of the device.

2) Lateral variable doping technique

In a thyristor with laterally variable doped termination structure, the higher concentration P⁺The high-low junction formed by the doped layer on the low-concentration P-type doped layer is a non-parallel plane junction, and the junction surface of the doped layer is bent to avoid the higher-concentration P⁺The type impurity enters the junction terminal region, and has the functions of reducing the chip voltage drop by thinning the long base region and improving the blocking voltage of the thyristor. Although the technology can improve reverse blocking and reverse recovery capability of the reverse blocking type GCT, the design requirement for improving turn-off capability of the large-size GCT cannot be met.

3) Lateral emissivity control

The anode of the junction area of the IGBT terminal is weakly doped, the current gain of the local area of the IGBT terminal is controlled by reducing the emission efficiency of the anode, the static blocking performance of the device is improved, and the safe working area of the device is further improved. At present, the technology is similar to the lateral variation doping technology, but the application of the technology to IGCT has no related technical literature reports.

Another existing technology for controlling the injection efficiency of a terminal is to introduce an oxide layer between an n-type buffer layer and a p-type collector region of a terminal of a device for isolation to inhibit the current concentration effect at the terminal in the turn-off process, so as to improve the turn-off characteristic and reliability of the device.

However, none of the above methods can simultaneously maintain the technical advantages of low on-state voltage drop and low trigger current of the GCT and improve the turn-off current capability and reverse recovery-di/dt capability of the reverse resistance type GCT.

Disclosure of Invention

To go upThe present invention provides a reverse-resistance gate commutated thyristor, wherein the vertical direction of the layered structure of the thyristor sequentially comprises, from bottom to top: the vertical direction of the laminated structure of the thyristor sequentially comprises from bottom to top: p⁺Anode emitter region, P anode region, N^-Base region, P⁺Base region and plurality of N⁺An emission region;

wherein the plurality of N is in a direction looking down the thyristor from directly above⁺The emitting regions are uniformly distributed in circles along the circumferences with different diameters and taking the center of a chip of the thyristor as the center of a circle; the P is⁺The anode emission region comprises P₁ ⁺An anode emission region horizontally surrounding the P₁ ⁺P2 of anode emission region⁺An anode emission region; wherein, the P₂ ⁺An anode emission region is positioned in the P⁺N of anode emission region far from gate leading-out position⁺The area corresponding to the lower part of the emitting area and the P⁺A region of the anode emitter region at the thyristor edge termination location.

According to an embodiment of the present invention, the above P₂ ⁺The doping concentration of the anode emission region is lower than P₁ ⁺Doping concentration of the anode emitter region.

According to an embodiment of the present invention, the thyristor further includes:

a gate electrode located at said P⁺The base region top is not covered by the N⁺On the part covered by the emitting area; the gate leading-out end is positioned in the middle position between the chip center position of the thyristor and the edge terminal position of the thyristor or the position adjacent to the edge terminal of the thyristor;

a cathode located at the N⁺The top of the emitting region;

an anode located at the P⁺And the bottom of the anode emission region.

According to an embodiment of the present invention, the P is located at an intermediate position between a chip center position of the thyristor and an edge terminal position of the thyristor₂ ⁺Anode emitter regionIn the P⁺1-3 circles of N of anode emission region farthest from chip center position of thyristor⁺Area under the emission area and the P⁺A region of the anode emitter region at the thyristor edge termination location.

According to another embodiment of the present invention, the P is when the gate terminal is located adjacent to the edge terminal of the thyristor₂ ⁺An anode emission region is positioned in the P⁺The anode emission region is 1-3 circles N nearest to the chip center position of the thyristor⁺Area under the emission area and the P⁺A region of the anode emitter region at the thyristor edge termination location.

The invention also provides a manufacturing method of the reverse-resistance type gate commutated thyristor, which is characterized by comprising the following steps:

providing N^-A type single crystal silicon substrate;

to the N^-Carrying out P-type impurity pre-deposition on the upper surface and the lower surface of the type monocrystalline silicon substrate, and carrying out high-temperature diffusion on impurities to form a P base region and a P anode region;

injecting P-type doping impurities into the upper surface of the P base region and the preset injection window of the P anode region respectively, and performing high-temperature diffusion on the injected doping impurities to form P⁺Base region and P₁ ⁺An anode emission region;

at the P⁺Forming a plurality of N on the top of the base region⁺An emission region; wherein the plurality of N is in a direction looking down the thyristor from directly above⁺The emitting regions are uniformly distributed in circles along the circumferences with different diameters and taking the center of a chip of the thyristor as the center of a circle;

for the P₁ ⁺Implanting again P-type dopant impurity into a designated region around the anode emitter region, and performing high-temperature diffusion on the implanted dopant impurity to form P₂ ⁺An anode emission region; wherein, the P₂ ⁺An anode emission region is positioned in the P⁺N of anode emission region far from gate leading-out position⁺The area corresponding to the lower part of the emitting area and the P⁺A region of the anode emitter region at the thyristor edge termination location.

According to an embodiment of the present invention, the above manufacturing method further includes the steps of:

for the plurality of N⁺Emission area and the N⁺The middle part of the emitting area is subjected to surface passivation isolation;

depositing a metal electrode layer on the surface of the passivation isolation, and carrying out etching and annealing treatment to form a metal electrode layer positioned on the P⁺The base region top is not covered by the N⁺A gate electrode on the part covered by the emitter region, located at said N⁺A cathode on top of the emitter region; the P is₁ ⁺An anode emission region and said P₂ ⁺Depositing a metal electrode layer on the lower surface of the anode emission region, and annealing to form the P₁ ⁺Anode emission region and P₂ ⁺And an anode at the bottom of the anode emission region.

According to the embodiment of the invention, the closed tube aluminum expanding process carried out in the saturated aluminum source atmosphere of the low vacuum furnace tube is preferably adopted to carry out the aluminum expanding process on the N^-Aluminum diffusion is carried out on the upper surface and the lower surface of the type monocrystalline silicon substrate to form the P anode region and the P⁺And a base region.

According to an embodiment of the present invention, the N is preferably formed by the following steps⁺An emission area:

at the P⁺Carrying out high-temperature oxidation promotion on N-type impurities on the upper surface of the base region, wherein P is⁺N is formed on the upper surface of the base region⁺An impurity diffusion layer and an oxide layer;

photoetching the oxide layer to form N which is uniformly arranged in a radial concentric manner⁺A pattern of emission areas;

to the N⁺Selectively grooving the emitting region pattern to form N which is uniformly arranged concentrically and radially⁺An emission area.

According to an embodiment of the present invention, selective trenching is preferably performed using a chemical wet etch or a dry etch process.

According to an embodiment of the present invention, the predetermined implantation window is preferably formed using silicon dioxide or photoresist.

One or more embodiments of the present invention may have the following advantages over the prior art:

the invention is characterized in that a low-emission anode structure (P) is introduced at the terminal of a GCT table top₁ ⁺Anode emission region and P₂ ⁺Anode emission region), the negative pole comb strip current density far away from the gate can be adjusted, and the failure of turn-off caused by breakdown due to carrier aggregation is avoided. The novel large-size GCT chip structure provided by the invention can keep the technical advantages of low-pass voltage drop and low trigger current of GCT, and can improve the turn-off current capability and reverse recovery-di/dt capability of reverse-resistance GCT.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:

FIG. 1 is a schematic diagram of a longitudinal structure of a conventional reverse-blocking GCT chip;

FIG. 2 shows N of reverse-blocking GCT according to a first embodiment of the present invention⁺An emission region, a middle gate pole leading-out position and a chip edge terminal top view;

FIG. 3 is a cross-sectional view of the longitudinal structure of the reverse resistance GCT chip shown in FIG. 2;

FIG. 4 is a schematic diagram illustrating the design parameters of the longitudinal structure of the reverse-blocking GCT chip according to the embodiment of the present invention;

FIG. 5 shows N of reverse-blocking GCT according to the second embodiment of the present invention⁺An emission region, an edge gate pole leading-out position and a chip edge terminal top view;

FIG. 6 is a cross-sectional view of the longitudinal structure of the reverse resistance GCT chip shown in FIG. 5;

fig. 7 is a schematic diagram of a manufacturing process of a reverse resistance type GCT chip according to a third embodiment of the present invention.

1, P + anode emitter region; a 2, N-substrate; 3, a P base region; 4, P + short base region; 5, N + cathode region; 6, an anode; 7, a gate electrode; 8, a cathode; 9, a gate electrode; 10, J1 node; 11, J2 node; 12, J3 junction (gated cathode junction).

Detailed Description

The following detailed description of the embodiments of the present invention will be provided with reference to the drawings and examples, so that how to apply the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.