阅读说明：本技术 驱动装置、供电系统以及测试驱动装置的方法 (Drive device, power supply system and method for testing drive device ) 是由 归山隼一 于 2020-04-21 设计创作，主要内容包括：本申请涉及驱动装置、供电系统以及测试驱动装置的方法。驱动装置包括：用于检测被施加到功率晶体管的应力的状态的传感器；用于输出阈值电压的阈值电压设置电路；用于通过将检测到的传感器的电压与阈值电压进行比较来确定应力的状态是否异常的异常监视电路；以及用于在由异常监视电路确定应力的状态异常时将功率晶体管固定为导通或截止的控制电路。当操作模式为测试模式时,控制电路通过切换由阈值电压设置电路设置的阈值电压的电平来测试异常监视电路是否确定应力的状态为异常,以便在正常操作的异常监视电路中确定被施加到功率晶体管的应力的状态为异常。(The application relates to a drive device, a power supply system and a method for testing a drive device. The drive device includes: a sensor for detecting a state of stress applied to the power transistor; a threshold voltage setting circuit for outputting a threshold voltage; an abnormality monitoring circuit for determining whether the state of stress is abnormal by comparing the detected voltage of the sensor with a threshold voltage; and a control circuit for fixing the power transistor to be turned on or off when the state of stress determined by the abnormality monitoring circuit is abnormal. When the operation mode is the test mode, the control circuit tests whether the abnormality monitoring circuit determines the state of stress as abnormal by switching the level of the threshold voltage set by the threshold voltage setting circuit, so as to determine the state of stress applied to the power transistor as abnormal in the abnormality monitoring circuit in normal operation.)

1. A drive device, comprising:

a sensor configured to detect and output a state of stress applied to the power transistor as a detection voltage;

a threshold voltage setting circuit configured to output a threshold voltage;

an abnormality monitoring circuit configured to determine whether the state of the stress applied to the power transistor is abnormal by comparing the detection voltage with the threshold voltage; and

a control circuit configured to fix the power transistor to be turned on or off according to a type of the stress when the abnormality monitoring circuit determines that the state of the stress is abnormal,

wherein, when the operation mode is a test mode, the control circuit is further configured to test whether the abnormality monitoring circuit determines the state of the stress as abnormal by switching the level of the threshold voltage set by the threshold voltage setting circuit, so as to determine the state of the stress applied to the power transistor as abnormal in the abnormality monitoring circuit in normal operation.

2. The drive device as set forth in claim 1,

wherein the stress is a voltage applied to the power transistor,

wherein the abnormality monitoring circuit is configured to determine whether a voltage applied to the power transistor is in an overvoltage state by comparing the detection voltage output from the sensor according to the voltage applied to the power transistor with the threshold voltage, and

wherein the control circuit is configured to forcibly turn on the power transistor when it is determined by the abnormality monitoring circuit that the voltage applied to the power transistor is in an overvoltage state.

3. The drive device as set forth in claim 2,

wherein the sensor comprises a first resistive element and a second resistive element arranged in series between a first terminal and a second terminal of the power transistor, and

wherein the sensor outputs a voltage at a node between the first resistive element and the second resistive element as the detection voltage.

4. The drive device as set forth in claim 1,

wherein the stress is a current flowing through the power transistor,

wherein the abnormality monitoring circuit is configured to determine whether or not the current flowing through the power transistor is in an overcurrent state by comparing the detection voltage output from the sensor according to the current flowing through the power transistor with the threshold voltage, and

wherein the control circuit is configured to forcibly turn off the power transistor when the abnormality monitoring circuit determines that the current flowing through the power transistor is in an overcurrent state.

5. The drive device as set forth in claim 4,

wherein the power transistor is an Insulated Gate Bipolar Transistor (IGBT) or a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and

wherein the sensor is configured to output, as the detection voltage, a collector voltage or a drain voltage of the power transistor indicating a voltage value corresponding to a collector current or a drain current of the power transistor.

6. The drive device as set forth in claim 4,

wherein the power transistor is a multi-emitter type Insulated Gate Bipolar Transistor (IGBT) or a multi-source type Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and

wherein the sensor has a resistor for converting a current output from a current sensing emitter or a current sensing source of the power transistor into the detection voltage.

7. The drive device as set forth in claim 1,

wherein the stress is a temperature of the power transistor, and

wherein the abnormality monitoring circuit is configured to forcibly turn off the power transistor when the abnormality monitoring circuit determines that the temperature of the power transistor is overheated by comparing the detection voltage output from the sensor according to the temperature of the power transistor with the threshold voltage.

8. The drive device as set forth in claim 7,

wherein the sensor comprises:

a constant current source, and

a diode through which a constant current output from the constant current source flows,

wherein the sensor outputs a forward voltage of the diode as the detection voltage, the forward voltage of the diode varying according to a temperature of the power transistor.

9. The drive device according to claim 1, further comprising: a gate voltage monitoring circuit configured to monitor a gate voltage of the power transistor.

10. The driving apparatus according to claim 9, wherein the gate voltage monitoring circuit is configured to directly monitor the gate voltage of the power transistor.

11. The drive device as set forth in claim 9,

wherein the control circuit is configured to fix the gate voltage of the power transistor to a predetermined voltage according to the type of stress when the abnormality monitoring circuit determines that the state of the stress is abnormal, and

wherein the control circuit is configured to test whether the gate voltage monitoring circuit determines that the gate voltage is fixed to the predetermined voltage when the operation mode is a test mode.

12. The driving apparatus according to claim 9, wherein the gate voltage monitoring circuit includes a comparator configured to compare a gate voltage of the power transistor with a reference voltage.

13. The drive device according to claim 9, further comprising:

an active mirror clamp circuit configured to clamp the gate voltage of the power transistor to a ground level in response to the gate voltage decreasing below a boundary value of on/off switching of the power transistor;

wherein the active mirror clamp circuit comprises:

a switching element provided between a gate of the power transistor and a ground voltage terminal;

a comparator configured to compare the gate voltage with a reference voltage lower than the boundary value; and

a switching circuit configured to control the switching element to be turned on when it is determined by the comparator that the gate voltage is less than the reference voltage,

wherein the comparator provided in the active mirror clamp circuit is also used as the gate voltage monitoring circuit.

14. The drive device as set forth in claim 9,

wherein the active mirror clamp circuit is configured to keep the switching element on when the switching element is controlled on until the power transistor is activated by the control circuit to be controlled from off to on.

15. The drive device as set forth in claim 13,

wherein the comparator outputs a comparison result indicating noise generation in the gate of the power transistor when the gate voltage of the power transistor is equal to or higher than the reference voltage even if the power transistor is controlled to be off by the control circuit.

16. The drive device as set forth in claim 15,

wherein the control circuit is configured to be able to switch the level of the reference voltage.

17. The drive device as set forth in claim 16,

wherein the control circuit is configured to adjust the reference voltage to a maximum value allowed as an increase of the gate voltage caused by the noise when an operation mode is a test mode, and then adjust an on-off switching speed of the power transistor within a range in which the gate voltage indicates less than the maximum value of the reference voltage.

18. A power supply system comprising:

a drive device, comprising:

a sensor configured to detect and output a state of stress applied to the power transistor as a detection voltage;

a threshold voltage setting circuit configured to output a threshold voltage;

an abnormality monitoring circuit configured to determine whether the state of the stress applied to the power transistor is abnormal by comparing the detection voltage with the threshold voltage; and

a control circuit configured to fix the power transistor to be turned on or off according to a type of the stress when the abnormality monitoring circuit determines that the state of the stress is abnormal,

wherein when the operation mode is a test mode, the control circuit is further configured to test whether the abnormality monitoring circuit determines the state of the stress as abnormal by switching the level of the threshold voltage set by the threshold voltage setting circuit, so that the abnormality monitoring circuit operating normally determines the state of the stress as abnormal, and

a power transistor.

19. A method of testing a drive device, comprising:

switching a level of the threshold voltage set by the threshold voltage setting circuit so as to determine a state of stress applied to the power transistor as abnormal in the abnormality monitoring circuit which operates normally; and

testing whether the abnormality monitoring circuit determines that a state of stress applied to the power transistor is abnormal by comparing a detection voltage of a sensor for detecting the state of stress applied to the power transistor with the threshold voltage.

Technical Field

The invention relates to a driving device, a power supply system and a testing method of the driving device. For example, the present invention is suitable for a drive device, a power supply system, and a test method for a drive device that improve safety.

Background

Since high voltage and large current are used in controlling an inverter mounted on an electric vehicle and in controlling a large-sized motor, high safety is required for on/off control of power transistors such as an IGBT (insulated gate bipolar transistor) and a MOSFET (metal oxide semiconductor field effect transistor).

For example, if a power transistor is inadvertently turned on when it is to be turned off, an overcurrent may flow through the power transistor. In addition, when a surge or a counter electromotive force occurs, an overvoltage may be applied to the power transistor. Furthermore, in the case of high loads, the power transistor overheats to exceed the rated temperature. Such overcurrent, overvoltage or overheating conditions can lead to breakdown or unintentional degradation of the power transistor.

Accordingly, a gate driver for driving a power transistor is generally provided with a circuit for detecting overvoltage, overcurrent, and overheat conditions of the power transistor and protecting the power transistor from the overvoltage, overcurrent, and overheat conditions.

The disclosed techniques are listed below.

[ patent document 1] Japanese unexamined patent application publication No. 2017-

[ patent document 2] U.S. Pat. No. 5,534,814

For example, patent document 1 discloses a configuration of a gate driver having a function of protecting a power transistor.

Non-patent document 1 l.dulau et al, "a new gate driver integrated circuit for IGBT devices with advanced protection", IEEE electric and electronics bulletin, volume 21, phase 1, pages 38-44,2006. (L.Dulau, et al, "A new gate driver integrated circuit for IGBT devices with advanced technologies", IEEE Transactions on Power Electronics, Vol.21, Issue 1, p.38-44,2006.)

Patent document 2 and non-patent document 1 disclose configurations of an active mirror clamp circuit for preventing noise generated in the IGBT gate voltage.

Disclosure of Invention

However, in the configuration of the related art, there is no function of testing whether or not a protection circuit such as an overvoltage protection circuit operates normally. Therefore, there are the following problems: when the protection circuit does not normally operate due to, for example, an open failure caused by cracking of solder of the terminal, adhesion of dust, or a short circuit caused by a component failure, the power transistor cannot be protected from excessive stress such as overvoltage. That is, in the configuration of the related art, there is a problem that the security cannot be improved. Thus, in prior art configurations, the power transistor may be damaged or inadvertently degraded. Other objects and novel features will become apparent from the description and drawings of the specification.

According to one embodiment, a driving apparatus includes: a sensor configured to detect and output a state of stress applied to the power transistor as a detection voltage; a threshold voltage setting circuit configured to output a threshold voltage; an abnormality monitoring circuit configured to determine whether a state of stress applied to the power transistor is abnormal by comparing the detection voltage and the threshold voltage; and a control circuit configured to fix the power transistor to be turned on or off according to a type of the stress when the abnormality monitoring circuit determines that the state of the stress is abnormal. When the operation mode is the test mode, the control circuit is further configured to test whether the abnormality monitoring circuit determines the state of stress as abnormal by switching the level of the threshold voltage set by the threshold voltage setting circuit, so as to determine the state of stress applied to the power transistor as abnormal in the abnormality monitoring circuit that operates normally.

According to another embodiment, a method of testing a driving apparatus includes: the level of the threshold voltage set by the threshold voltage setting circuit is switched so as to determine the state of stress applied to the power transistor as abnormal in the abnormality monitoring circuit which operates normally, and whether the abnormality monitoring circuit determines the state of stress applied to the power transistor as abnormal is tested by comparing the detection voltage of the sensor for detecting the state of stress applied to the power transistor with the threshold voltage.

According to the above-described embodiments, it is possible to provide a driving apparatus, a power supply system, and a method of testing a driving apparatus, which can improve safety.

Drawings

Fig. 1 is a diagram showing a configuration example of a power supply system according to a first embodiment.

Fig. 2 is a flowchart showing a test operation of the gate driving circuit provided in the power supply system shown in fig. 1.

Fig. 3 is a diagram illustrating a modified example of the power transmission system shown in fig. 1.

Fig. 4 is a diagram showing a configuration example of a power supply system according to the second embodiment.

Fig. 5 is a diagram for explaining a test operation of the provided gate driving circuit corresponding to the lower arm of the inverter circuit.

Fig. 6 is a diagram for explaining a test operation of the provided gate driving circuit corresponding to the upper arm of the inverter circuit.

Fig. 7 is a diagram showing a configuration example of a power supply system according to the third embodiment.

Fig. 8 is a diagram showing a configuration example of a power supply system according to the fourth embodiment.

Fig. 9 is a diagram showing a configuration example of the active mirror clamp circuit.

Fig. 10 is a diagram showing a configuration example of a power supply system according to the fifth embodiment.

Fig. 11 is a truth table of input and output signals of a gate driving circuit provided in the power supply system shown in fig. 10.

Fig. 12 is a timing chart showing an operation of the gate driving circuit provided in the power supply system shown in fig. 10.

Detailed Description

The following description and drawings are omitted or simplified as appropriate for clarity of explanation. Additionally, elements described as functional blocks for performing various processes in the drawings may be configured as a CPU (central processing unit), a memory, and other circuits in terms of hardware, and may be implemented by a program loaded into the memory in terms of software. Accordingly, those skilled in the art will appreciate that these functional blocks may be implemented in various forms by hardware alone, by software alone, or by a combination thereof, and the present invention is not limited to any one of them. In the drawings, the same elements are denoted by the same reference numerals, and repeated description thereof is omitted as necessary.

In addition, various types of non-transitory computer-readable media may be used to store and provide the above-described program to the computer. Non-transitory computer readable media include various types of tangible storage media. Examples of the non-transitory computer readable medium include magnetic recording media (e.g., floppy disks, magnetic tapes, hard disk drives), magneto-optical recording media (e.g., magneto-optical disks), CD-ROMs (read only memories), CD-R, CD-R/ws, solid-state memories (e.g., mask ROMs, PROMs (programmable ROMs), EPROMs (erasable PROMs, flash ROMs, RAMs (random access memories)). the program may also be provided to the computer by various types of transitory computer readable media.

First embodiment

Fig. 1 is a diagram showing a configuration example of a power supply system SYS1 according to the first embodiment. The power supply system SYS1 of the present embodiment is used in, for example, an inverter for driving a motor.

The power supply system SYS1 according to the present embodiment includes an abnormality monitoring circuit for monitoring the state of stress applied to the power transistor TR1, and has a function of testing whether the abnormality monitoring circuit operates normally. Therefore, the power supply system SYS1 according to the present embodiment can monitor the state of stress applied to the power transistor TR1 by using a highly reliable abnormality monitoring circuit, so that the safety of the power supply system SYS1 can be improved. A detailed description will be given hereinafter.

As shown in fig. 1, the power supply system SYS1 includes a power transistor TR1 and a driving device 1 for driving the power transistor TR 1.

The power transistor TR1 is an IGBT, a MOSFET, or the like, and switches whether or not to supply power to a load such as a motor. In the present embodiment, the power transistor TR1 is an IGBT.

The driving device 1 includes at least a gate driving circuit 10, a sensor 16, a control circuit 17, and a resistor Rg.

The sensor 16 detects the state of stress applied to the power transistor TR1, and outputs a detected voltage Vs. The stress applied to the power transistor TR1 includes, for example, a voltage applied to the power transistor TR1, a current flowing through the power transistor TR1, and a temperature of the power transistor TR 1.

The gate drive circuit 10 controls the gate voltage Vg of the power transistor TR1 based on an instruction from the control circuit 17. Specifically, the gate drive circuit 10 includes an abnormality monitoring circuit 11, a threshold voltage setting circuit 12, a buffer 14, a gate voltage monitoring circuit 15, and a logic circuit 13. These components provided in the gate driver circuit 10 are formed on the same chip, for example.

The logic circuit 13 generates a control signal OUT based on a control signal IN from the control circuit 17. The buffer 14 drives and outputs the control signal OUT. The control signal OUT output from the buffer 14 is applied to the gate of the power transistor TR1 through the resistor Rg. Thus, the power transistor TR1 is turned on and off.

The abnormality monitoring circuit 11 monitors whether the state of stress applied to the power transistor TR1 is abnormal based on the result detected by the sensor 16. Specifically, the abnormality monitoring circuit 11 compares the detection voltage Vs output from the sensor 16 with the threshold voltage Vt set in the threshold voltage setting circuit 12, and outputs the comparison result as the monitoring result.

For example, when the detected voltage Vs is within the allowable voltage defined by the threshold voltage Vt, the abnormality monitoring circuit 11 outputs a monitoring result indicating that the stress applied to the power transistor TR1 is normal. On the other hand, when the detected voltage Vs is outside the allowable voltage defined by the threshold voltage Vt, the abnormality detection circuit 11 outputs a monitoring result indicating that the stress applied to the power transistor TR1 is abnormal.

The logic circuit 13 activates the error signal ERR1 (e.g., H level) upon receiving a monitoring result indicating that the state of stress applied to the power transistor TR1 is abnormal from the abnormality monitoring circuit 11. When the control circuit 17 receives the error signal ERR1 in the activated state, the control circuit 17 instructs the gate drive circuit 10 to fix the power transistor TR1 to be turned on or off depending on the type of stress (voltage, current, or heat). The gate drive circuit 10 fixes the power transistor TR1 to be turned on or off based on an instruction from the control circuit 17. Therefore, excessive stress applied to the power transistor TR1 is eliminated, so that breakdown and unintentional degradation of the power transistor TR1 are suppressed.

The gate voltage monitor 15 monitors the gate voltage Vg of the power transistor TR 1. Specifically, the gate voltage monitoring circuit 15 compares the gate voltage Vg with the reference voltage Vr to monitor whether the gate voltage Vg indicates a desired voltage level.

The logic circuit 13 compares the monitoring result by the gate voltage monitoring circuit 15 with the control signal IN output from the control circuit 17. When the monitoring result of the gate voltage monitoring circuit 15 is different from the control signal IN output from the control circuit 17, the logic circuit 13 activates the error signal ERR2, for example, sets the error signal to the H level. The control circuit 17, upon receiving the error signal ERR2 in the activated state, for example, stops operating the gate drive circuit 10 or notifies the user that the power transistor TR1 is not operating correctly.

Here, the gate voltage monitoring circuit 15 directly monitors the gate voltage Vg of the power transistor TR 1. Therefore, unlike the case where the gate voltage Vg is indirectly monitored from the internal signal of the gate drive circuit 10, the gate voltage monitoring circuit 15 can detect that the gate voltage Vg does not exhibit a desired voltage level due to, for example, an open-circuit fault or a short-circuit fault occurring in the terminals of the chip or components other than the chip.

Further, the control circuit 17 has a function of testing whether each of the abnormality monitoring circuit 11 and the gate voltage monitoring circuit 15 normally operates, for example, at the time of system startup before the system enters normal operation, during idling, or at the time of shutdown after the system completes normal operation.

(test operation of the gate driver circuit 10)

Subsequently, a test operation of the gate driver circuit 10 provided in the power supply system SYS1 will be described with reference to fig. 2. Fig. 2 is a flowchart showing an operation of testing the gate driver circuit 10 provided in the power supply system SYS 1. Hereinafter, an operation mode in which a normal operation is performed is referred to as a normal operation mode, and an operation mode in which a test of whether the abnormality monitoring circuit 11 and the gate voltage monitoring circuit 15 normally operate is performed is referred to as a test mode.

First, in the test mode, a stress of a normal level in the normal operation mode is applied to the power transistor TR1 (step S101).

Thereafter, the control circuit 17 switches the level of the threshold voltage Vt set by the threshold voltage setting circuit 12 so that the detection voltage Vs is outside the range of the allowable voltage defined by the threshold voltage Vt. In other words, the control circuit 17 switches the level of the threshold voltage Vt set by the threshold voltage setting circuit 12 so as to determine that the state of stress applied to the power transistor TR1 is abnormal in the case where the abnormality monitoring circuit 11 operates normally. (step S102).

Thereafter, the control circuit 17 checks the monitoring results of the abnormality monitoring circuit 11 and the gate voltage monitoring circuit 15, respectively (step S103).

At this time, if the state is normal, the abnormality monitoring circuit 11 outputs a monitoring result indicating that the state of stress applied to the power transistor TR1 is abnormal, and if the state is not normal, outputs a monitoring result opposite to the state of stress applied to the power transistor TR 1. The logic circuit 13 activates the error signal ERR1 (e.g., H level) upon receiving a monitoring result indicating that the state of stress applied to the power transistor TR1 is abnormal from the abnormality monitoring circuit 11. The control circuit 17 receives the error signal ERR1 in the active state to determine that the abnormality monitoring circuit 11 is operating normally.

At this time, the gate voltage monitoring circuit 15 outputs a monitoring result indicating that the gate voltage Vg of the power transistor TR1 is forcibly fixed to a predetermined voltage if normal, and outputs a monitoring result opposite thereto if not normal. When the result of monitoring by the gate voltage monitoring circuit 15 has the same value as the control signal IN output from the control circuit 17, the logic circuit 13 sets the error signal ERR2 to be deactivated (for example, L level). The control circuit 17 determines that the gate voltage monitoring circuit 15 is operating normally by receiving the deactivated error signal ERR 2.

When the control circuit 17 determines that both the abnormality monitoring circuit 11 and the gate voltage monitoring circuit 15 operate normally (yes in step S104), the threshold voltage Vt is returned to the level used in the normal operation, and then the normal operation is started (step S105 → S106).

In contrast, when it is determined that the abnormality monitoring circuit 11 or the gate voltage monitoring circuit 15 does not operate normally (no in step S104), the control circuit 17 stops operating the gate drive circuit 10, for example, or notifies the user that the power transistor TR1 does not operate normally (step S107).

As described above, when the operation mode is the test mode, the device 1 and the power supply system SYS1 including the device 1 are configured to test the abnormality monitoring circuit 11 and the gate voltage monitoring circuit 15 after adjusting the threshold voltage Vt so as to determine that the state of stress applied to the power transistor TR1 is abnormal in the case where the abnormality monitoring circuit 11 normally operates. Therefore, the drive device 1 and the power supply system SYS1 can monitor the state of stress applied to the power transistor TR1 by using the highly reliable abnormality monitoring circuit 11 and the gate voltage monitoring circuit 15, so that the safety of the power supply system can be improved.

Although the reference voltage Vr supplied to the gate voltage monitoring circuit 15 is fixed in the present embodiment, the reference voltage Vr may not be fixed. The reference voltage Vr may be adjustable by the threshold voltage setting circuit 12 or the like. Therefore, the gate voltage monitoring circuit 15 can be tested in more detail.

Second embodiment

Fig. 4 is a diagram illustrating a configuration example of the power supply system SYS1a according to the second embodiment. In the power supply system SYS1a, the abnormality monitoring circuit 11 is configured to monitor a voltage applied to the power transistor TR 1. A detailed description will be given hereinafter. As shown in fig. 4, the power supply system SYS1a includes a power transistor TR1 and a driving device 1a for driving the power transistor TR 1. The driving device 1a includes at least a gate driving circuit 10a, a sensor 16a, a control circuit 17, and a resistor Rg.

The sensor 16a corresponds to the sensor 16, and includes resistors R1 and R2. The resistive elements R1 and R2 are provided in series between the collector (first terminal) and the emitter (second terminal) of the power transistor TR 1. The sensor 16a outputs the voltage of the node N11 between the resistor R1 and the resistor R2 as the detection voltage Vs. The detection voltage Vs increases with an increase in the voltage applied to the power transistor TR1, and decreases with a decrease in the voltage applied to the power transistor TR 1.

The gate driving circuit 10a corresponds to the gate driving circuit 10, and includes a comparator CMP1a, a comparator CMP2, a logic circuit 13, a buffer 14, a register 121, and a digital-to-analog converter (DAC) 122. The comparator CMP1a functions as the abnormality monitoring circuit 11. The comparator CMP2 serves as the gate voltage monitoring circuit 15. The register 121 and the DA converter 122 function as the threshold voltage setting circuit 12.

The register 121 stores information (digital value) DT of the threshold voltage Vt specified by the control circuit 17. The DA converter 122 converts the digital value DT stored in the register 121 into a threshold voltage Vt and outputs the threshold voltage Vt.

The comparator CMP1a compares the threshold voltage Vt with the detection threshold voltage Vs, and outputs the comparison result as the monitoring result by the abnormality monitoring circuit 11. For example, when the detection voltage Vs is less than the threshold voltage Vt, the comparator CMP1a outputs an L level monitoring result indicating that the voltage applied to the power transistor TR1 is within a normal range. When the detection voltage Vs is equal to or higher than the threshold voltage Vt, the comparator CMP1a outputs an H level monitoring result indicating that the voltage applied to the power transistor TR1 is in an overvoltage state.

Upon receiving the H level monitor result from the comparator CMP1a, the logic circuit 13 activates the error signal ERR 1. When receiving the error signal ERR1 in the activated state, the control circuit 17 instructs the gate drive circuit 10a to forcibly turn on the power transistor TR 1. The gate driver 10a forcibly turns on the power transistor TR1 by fixing the gate voltage Vg of the power transistor TR1 to the H level. This eliminates the overvoltage state of the power transistor TR1, thereby suppressing breakdown and unintentional degradation of the power transistor TR 1.

The comparator CMP2 compares the gate voltage Vg with the reference voltage Vr, and outputs the comparison result as a monitoring result by the gate voltage monitoring circuit 15. The specific operation of the comparator CMP2 and the operation of the logic circuit 13 and the control circuit based on the monitoring result of the comparator CMP2 are the same as those of the gate voltage monitoring circuit 15, the logic circuit 13, and the control circuit 17 according to the first embodiment, and thus the description thereof is omitted.

(test operation of the gate drive circuit 10 a)

Subsequently, a test operation of the gate driver circuit 10a provided in the power supply system SYS1a will be described.

First, in the test mode, the normal level voltage in the normal operation mode is applied to the power transistor TR 1. Specifically, for example, a voltage of 400V is applied to the collector of the power transistor TR 1. At this time, the detection voltage Vs indicates, for example, 4V which is one hundredth of the collector voltage.

Thereafter, the control circuit 17 switches the level of the threshold voltage Vt so that the detection voltage Vs becomes equal to or higher than the threshold voltage Vt. In other words, the control circuit 17 lowers the level of the threshold voltage Vt (for example, from normal 6V to 3V) to output the monitoring result of the H level indicating that the power transistor TR1 is in an overvoltage state if the comparator CMP1a operates normally.

Thereafter, the controller 17 confirms the monitoring results of the comparators CMP1a and CMP 2.

At this time, since the detection voltage Vs (═ 4V) becomes higher than the threshold voltage Vt (═ 3V), the comparator CMP1a outputs the monitoring result of the H level when the threshold voltage Vt is normal, and outputs the monitoring result of the L level when the threshold voltage Vt is abnormal. The logic circuit 13 receives the monitoring result of the H level from the comparator CMP1a to activate the error signal ERR1 (e.g., H level). The control circuit 17 receives the error signal ERR1 in the active state to determine that the comparator CMP1a is operating normally.

At this time, if the gate voltage Vg is normal, the comparator CMP2 outputs a monitoring result of an H level indicating that the gate voltage Vg of the power transistor TR1 is forcibly fixed to an H level, and outputs a monitoring result of an L level if the gate voltage Vg is abnormal. When the monitoring result by the comparator CMP2 indicates the same value (H level) as the control signal IN output from the control circuit 17, the logic circuit 13 sets the error signal ERR2 to be deactivated (e.g., L level). The control circuit 17 receives the deactivated error signal ERR2 and the control circuit 17 determines that the comparator CMP2 is operating normally.

When it is determined that both the comparators CMP1a and CMP2 are operating normally, the control circuit 17 starts the normal operation after returning the threshold voltage Vt to the level (e.g., 6V) used in the normal operation. In contrast, if it is determined that one of the comparators CMP1a or CMP2 is not normally operated, the control circuit 17 stops the operation of the gate drive circuit 10a, for example, or notifies the user that the power transistor TR1 is not normally operated. The remaining configuration and operation of the drive device 1a are the same as those of the drive device 1, and thus the description thereof is omitted.

As described above, when the operation mode is the test mode, the device 1a and the power supply system SYS1a including the device 1a are configured to test the comparators CMP1a and CMP2 after lowering the threshold voltage Vt, so that if the comparator CMP1a normally operates, it is determined that the applied voltage of the power transistor TR1 is in an overvoltage state. Therefore, the drive device 1a and the power supply system SYS1a having the device 1a can monitor the applied voltage of the power transistor TR1 using the reliable comparators CMP1a and CMP2, so that safety can be improved. It should be noted that the drive device 1a and the power supply system SYS1a provided with the drive device can be easily tested without generating a high voltage.

(application example of Power supply System SYS1a and test operation thereof)

Next, an application example of the power supply system SYS1a and a test operation thereof will be described. In the present embodiment, the power supply system SYS1a is applied to the inverter circuit.

Fig. 5 is a diagram for explaining a test operation of the provided gate driving circuit corresponding to the lower arm of the inverter circuit. Fig. 6 is a diagram for explaining a test operation of the provided gate driving circuit corresponding to the upper arm of the inverter circuit.

As shown in fig. 5 and 6, the inverter circuit includes a power transistor TR1_1, a power transistor TR1_2, gate driving circuits 10_1 and 10_2, and sensors 16_1 and 16_ 2. The power transistors TR1_1 and TR1_2 are provided in series between a power supply voltage terminal (hereinafter referred to as a power supply voltage terminal Vbus) to which the power supply voltage Vbus is supplied and a ground voltage terminal GND. Each of the power transistors TR1_1 and TR1_2 corresponds to the power transistor TR1, and constitutes an upper arm and a lower arm of the inverter circuit, respectively.

Each of the sensors 16_1 and 16_2 corresponds to the sensor 16a, and detects the applied voltage of the power transistors TR1_1 and TR1_2, respectively. Each of the gate driving circuits 10_1 and 10_2 corresponds to the gate driving circuit 10a, and drives the gates of the power transistors TR1_1 and TR1_2, respectively.

First, a test operation of the provided gate driving circuit 10_2 corresponding to the lower arm TR1_2 will be described with reference to fig. 5.

In the initial state, in a state where both the power transistors TR1_1 and TR1_2 are turned off, the power supply voltage Vbus of, for example, 400V is applied to the power supply voltage terminal. The threshold voltage Vt of each of the gate driving circuits 10_1 and 10_2 is set to, for example, 600V.

Thereafter, the power transistor TR1_1 is switched from off to on with the power transistor TR1_2 kept off. Accordingly, the output terminal between the power transistors TR1_1 and TR1_2 is precharged to the power supply voltage Vbus level of 400V. After the precharge is completed, the power transistor TR1_1 is switched from on to off again. At this time, the voltage of the power supply voltage Vbus is applied between the collector and the emitter of the power transistor TR1_ 2.

Thereafter, the threshold voltage Vt of the gate driving circuit 10_2 is switched to a voltage level lower than the power supply voltage Vbus, for example, 300V. Therefore, tests of the abnormality monitoring circuit 11 and the gate voltage monitoring circuit 15 provided in the gate drive circuit 10_2 are performed. When the abnormality monitoring circuit 11 provided in the gate drive circuit 10_2 operates normally, the power transistor TR1_2 is forcibly controlled to be on.

Next, a test operation of the provided gate drive circuit 10_1 corresponding to the upper arm TR1_1 will be described with reference to fig. 6.

In the initial state, the power supply voltage Vbus of, for example, 400V is applied to the power supply voltage terminal in a state where both the power transistors TR1_1 and TR1_2 are turned off. The threshold voltage Vt of each of the gate driving circuits 10_1 and 10_2 is set to, for example, 600V.

Thereafter, with the power transistor TR1_1 kept off, the power transistor TR1_2 is switched from off to on. Therefore, the output terminal between the power transistors TR1_1 and TR1_2 is precharged to the ground voltage GND level (0V). After the precharge is completed, the power transistor TR1_2 is switched from on to off again. At this time, the voltage of the power supply voltage Vbus is applied between the collector and the emitter of the power supply transistor TR1_ 1.

Thereafter, the threshold voltage Vt of the gate driving circuit 10_1 is switched to a voltage level lower than the power supply voltage Vbus, for example, 300V. Therefore, tests of the abnormality monitoring circuit 11 and the gate voltage monitoring circuit 15 provided in the gate drive circuit 10_1 are performed. When the abnormality monitoring circuit 11 provided in the gate drive circuit 10_1 operates normally, the power transistor TR1_1 is forcibly controlled to be on.

As described above, the power supply system SYS1a applied to the inverter circuit tests the gate drive circuits 10_1 and 10_2 without short-circuiting the power supply voltage terminal Vbus and the ground voltage terminal GND. This suppresses damage and unintentional deterioration of the power transistors TR1_1 and TR1_2 and the load of the motor due to the short-circuit current.

Third embodiment

Fig. 7 is a diagram illustrating a configuration example of a power supply system SYS1b according to the third embodiment. In the power supply system SYS1b, the abnormality monitoring circuit 11 is configured to monitor a current flowing through the power transistor TR 1. A detailed description will be given hereinafter.

As shown in fig. 7, the power supply system SYS1b includes a power transistor TR1 and a driving device 1b for driving the power transistor TR 1. The driving device 1b includes at least a gate driving circuit 10b, a sensor 16b, a control circuit 17, and a resistor Rg. In the present embodiment, the power transistor TR1 is a multiple emitter type IGBT. For example, 1/10000 current of the emitter flows through the current sensing emitter of the multiple emitter IGBT.

The sensor 16b corresponds to the sensor 16, and includes a resistor Rs. The sensor 16b converts the current flowing through the current sensing emitter of the power transistor TR1 into a detection voltage Vs using a resistor Rs, and outputs the detection voltage Vs. As the current flowing through the power transistor TR1 increases, the detection voltage Vs increases, and as the current flowing through the power transistor TR1 decreases, the detection voltage Vs decreases.

The gate driving circuit 10b corresponds to the gate driving circuit 10, and includes a comparator CMP1b, a comparator CMP2, a logic circuit 13, a buffer 14, a register 121, and a digital-to-analog converter 122. The comparator CMP1b functions as the abnormality monitoring circuit 11. The comparator CMP2 serves as the gate voltage monitoring circuit 15. The register 121 and the DA converter 122 function as the threshold voltage setting circuit 12.

The comparator CMP1b compares the threshold voltage Vt with the detection threshold voltage Vs, and outputs the comparison result as the monitoring result by the abnormality monitoring circuit 11.

For example, when the detection voltage Vs is less than the threshold voltage Vt, the comparator CMP1b outputs a monitoring result of an L level indicating that the current flowing through the power transistor TR1 is within a normal range. When the detection voltage Vs is equal to or higher than the threshold voltage Vt, the comparator CMP1b outputs an H-level monitoring result indicating that the current flowing through the power transistor TR1 is in an overcurrent state.

Upon receiving the H level monitor result from the comparator CMP1b, the logic circuit 13 activates the error signal ERR 1. When receiving the error signal ERR1 in the activated state, the control circuit 17 instructs the gate drive circuit 10b to forcibly turn off the power transistor TR 1. The gate driver 10b forcibly turns off the power transistor TR1 by fixing the gate voltage Vg of the power transistor TR1 to the L level. This eliminates the overcurrent state of the power transistor TR1, thereby suppressing breakdown and unintentional degradation of the power transistor TR 1.

The comparator CMP2 compares the gate voltage Vg with the reference voltage Vr, and outputs the comparison result as a monitoring result by the gate voltage monitoring circuit 15. The specific operation of the comparator CMP2 and the operation of the logic circuit 13 and the control circuit based on the monitoring result of the comparator CMP2 are the same as those of the gate voltage monitoring circuit 15, the logic circuit 13, and the control circuit 17 according to the first embodiment, and thus the description thereof is omitted.

(test operation of the gate drive circuit 10 b)

Subsequently, a test operation of the gate driver circuit 10b provided in the power supply system SYS1b will be described.

First, in the test mode, a normal-level current in the normal operation mode is supplied to the power transistor TR 1.

Thereafter, the control circuit 17 switches the level of the threshold voltage Vt so that the detection voltage Vs becomes equal to or higher than the threshold voltage Vt. In other words, the control circuit 17 lowers the level of the threshold voltage Vt so as to output the monitoring result of the H level indicating that the current flowing through the power transistor TR1 is in the overcurrent state if the comparator CMP1b normally operates.

Although the present embodiment illustrates the case where the current flows through the power transistor TR1 and the level of the threshold voltage Vt is lowered in the test mode, the present invention is not limited to this case. For example, the threshold voltage Vt may be reduced to a negative threshold voltage without having to pass current through the power transistor TR 1. Alternatively, a DC offset may be added between the two inputs of the comparator CMP1b without having to flow current through the power transistor TR 1.

Thereafter, the controller 17 confirms the monitoring results of the comparators CMP1b and CMP 2.

At this time, if the comparator CMP1b is normal, the comparator CMP1b outputs the monitoring result of the H level, and if the comparator CMP1b is abnormal, the monitoring result of the L level is output. The logic circuit 13 receives the monitoring result of the H level from the comparator CMP1b to activate the error signal ERR1 (e.g., H level). The control circuit 17 receives the error signal ERR1 in the active state to determine that the comparator CMP1b is operating normally.

At this time, if the comparator CMP2 is normal, the comparator outputs a monitoring result of L level indicating that the gate voltage Vg of the power transistor TR1 is forcibly fixed to L level for a predetermined period of time, for example, for 1 μ s, and outputs a monitoring result of H level if the gate voltage Vg is not normal. When the monitoring result by the comparator CMP2 indicates the same value (L level) as the control signal IN output from the comparator 17, the logic circuit 13 deactivates the error signal ERR2 (e.g., L level). The control circuit 17 receives the deactivated error signal ERR2 and the control circuit 17 determines that the comparator CMP2 is operating normally.

When the control circuit 17 determines that all the comparators CMP1b and CMP2 are operating normally, the control circuit 17 returns the threshold voltage Vt to the level used in the normal operation, and then starts the normal operation. In contrast, if it is determined that one of the comparators CMP1b or CMP2 does not normally operate, the control circuit 17 stops the operation of the gate drive circuit 10b, for example, or notifies the user that the power transistor TR1 does not operate properly.

The remaining configuration and operation of the driving device 1b are the same as those of the driving device 1, and thus the description thereof is omitted.

In this way, when the operation mode is the test mode, the device 1b and the power supply system SYS1b including the device 1bs are configured to test the comparators CMP1b and CMP2 after lowering the threshold voltage Vt so as to determine that the current flowing through the power transistor TR1 is in the overcurrent state if the comparator CMP1b normally operates. Therefore, since the state of the current flowing through the power transistor TR1 can be monitored using the reliable comparators CMP1b and CMP2, the driving device 1b and the power supply system SYS1b having the driving device 1b can improve safety. Incidentally, the driving device 1b and the power supply system SYS1b having the driving device 1b can be easily tested without generating an overcurrent.

In the present embodiment, the power transistor TR1 is a multi-emitter IGBT, and the current flowing through the current sense emitter of the power transistor TR1 is converted into the detection voltage Vs and used, but the present invention is not limited thereto. The power transistor TR1 may be a multi-source MOSFET, and may convert and use the current flowing in the current sensing source of the power transistor TR1 into the detection voltage Vs. Additionally, for example, by utilizing a phenomenon that the collector-emitter voltage of the IGBT increases as the collector current of the IGBT increases, a voltage proportional to the collector-emitter voltage of the power transistor TR1 may be used as the detection voltage Vs (hereinafter, this current detection system is referred to as the DESAT method).

When the DESAT system is employed, in the test mode, the power transistor TR1 is turned off to raise the collector voltage, whereby it is possible to make the comparator CMP1c test whether an overcurrent state of the power transistor TR1 is detected. However, in the normal operation mode, when the power transistor TR1 is turned off, even if the collector voltage rises, the comparator CMP1b needs to consider that the power transistor TR1 is not abnormal.

Fourth embodiment

Fig. 8 is a diagram illustrating a configuration example of a power supply system SYS1c according to the fourth embodiment. In the power supply system SYS1c, the abnormality monitoring circuit 11 is configured to monitor the temperature of the power transistor TR 1. Hereinafter, a detailed description will be given.

As shown in fig. 8, the power supply system SYS1c includes a power transistor TR1 and a driving device 1c for driving the power transistor TR 1. The driving device 1c includes at least a gate driving circuit 10c, a sensor 16c, a control circuit 17, and a resistor Rg. The sensor 16c corresponds to the sensor 16, and includes a constant current source I1 and a diode D1. The diode D1 is provided near the power transistor TR1, for example on a chip on which the power transistor TR1 is formed. Therefore, the temperature of the diode D1 is equal to the temperature of the power transistor TR 1. On the other hand, the constant current source I1 is provided, for example, on a chip on which the gate driver circuit 10c is mounted.

A constant current output from the constant current source I1 flows through the diode D1. The sensor 16c outputs the forward voltage of the diode D1 as the detection voltage Vs. Even at normal temperature, the detection voltage Vs is higher than the 0V voltage. Specifically, even at room temperature, the detection voltage Vs indicates a value about an intermediate value between 0V and the logic power supply voltage or the analog power supply voltage. Further, the forward voltage of the diode D1 becomes smaller as the temperature of the power transistor TR1 increases, and becomes larger as the temperature of the power transistor TR1 decreases. The sensor 16c is not limited to the above configuration, and may be configured by a thermistor or a thermocouple.

The gate driving circuit 10c corresponds to the gate driving circuit 10, and includes a comparator CMP1c, a comparator CMP2, a logic circuit 13, a buffer 14, a register 121, and a digital-to-analog converter 122. The comparator CMP1c functions as the abnormality monitoring circuit 11. The comparator CMP2 serves as the gate voltage monitoring circuit 15. The register 121 and the DA converter 122 function as the threshold voltage setting circuit 12.

The comparator CMP1c compares the threshold voltage Vt with the detection threshold voltage Vs, and outputs the comparison result as the monitoring result by the abnormality monitoring circuit 11. For example, when the detection voltage Vs is equal to or higher than the threshold voltage Vt, the comparator CMP1c outputs an L level monitoring result indicating that the temperature of the power transistor TR1 is within a normal range. When the detection voltage Vs is less than the threshold voltage Vt, the comparator CMP1c outputs an H-level monitoring result indicating that the temperature of the power transistor TR1 is overheated.

Upon receiving the H level monitor result from the comparator CMP1c, the logic circuit 13 activates the error signal ERR 1. When receiving the error signal ERR1 in the activated state, the control circuit 17 instructs the gate drive circuit 10c to forcibly turn off the power transistor TR 1. The gate driver 10c forcibly turns off the power transistor TR1 by fixing the gate voltage Vg of the power transistor TR1 to the L level. This eliminates overheating of the power transistor TR1, thereby suppressing breakdown and unintentional degradation of the power transistor TR 1.

The comparator CMP2 compares the gate voltage Vg with the reference voltage Vr, and outputs the comparison result as a monitoring result by the gate voltage monitoring circuit 15. The specific operation of the comparator CMP2 and the operation of the logic circuit 13 and the control circuit based on the monitoring result of the comparator CMP2 are the same as those of the gate voltage monitoring circuit 15, the logic circuit 13, and the control circuit 17 according to the first embodiment, and thus the description thereof is omitted.

(test operation of the gate drive circuit 10 c)

Subsequently, a test operation of the gate driver circuit 10c provided in the power supply system SYS1c will be described. First, in the test mode, the power transistor TR1 is set to a normal temperature. Thereafter, the control circuit 17 switches the level of the threshold voltage Vt so that the detection voltage Vs becomes equal to or higher than the threshold voltage Vt. In other words, the control circuit 17 lowers the level of the threshold voltage Vt so as to output the monitoring result of the H level indicating the temperature overheating of the power transistor TR1 if the comparator CMP1c normally operates.

Thereafter, the controller 17 confirms each monitoring result of the comparators CMP1c and CMP 2.

At this time, if the comparator CMP1c is normal, the comparator CMP1c outputs the monitoring result of the H level, and if the comparator CMP1c is abnormal, the monitoring result of the L level is output. The logic circuit 13 receives the monitoring result of the H level from the comparator CMP1c to activate the error signal ERR1 (e.g., H level). The control circuit 17 receives the error signal ERR1 in the active state to determine that the comparator CMP1c is operating normally.

At this time, if the comparator CMP2 is normal, the comparator outputs a monitoring result of L level indicating that the gate voltage Vg of the power transistor TR1 is forcibly fixed to L level for a predetermined period of time, for example, 1 μ s, and outputs a monitoring result of H level if the gate voltage Vg is not normal. When the monitoring result by the comparator CMP2 indicates the same value (L level) as the control signal IN output from the comparator 17, the logic circuit 13 deactivates the error signal ERR2 (e.g., L level). The control circuit 17 receives the deactivated error signal ERR2 and the control circuit 17 determines that the comparator CMP2 is operating normally.

When the control circuit 17 determines that both the comparators CMP1c, CMP2 are operating normally, the control circuit 17 returns the threshold voltage Vt to the level used in the normal operation, and then starts the normal operation. Incidentally, if it is determined that one of the comparators CMP1c and CMP2 does not operate normally, the control circuit 17 stops the operation of the gate drive circuit 10c, for example, or notifies the user that the power transistor TR1 does not operate properly. The remaining configuration and operation of the driving device 1c are the same as those of the driving device 1, and thus the description thereof is omitted.

As described above, when the operation mode is the test mode, the driving device 1c of the present embodiment and the power supply system SYS1c including the driving device 1c are configured to test the comparators CMP1c and CMP2 after lowering the threshold voltage Vt so as to determine that the power transistor TR1 is overheated if the comparator CMP1c normally operates. Therefore, the state of the current flowing through the power transistor TR1 can be monitored using the reliable comparators CMP1c and CMP2, so that the safety of the drive device 1c and the power supply system SYS1c having the drive device can be improved. It should be noted that the drive device 1c and the power supply system SYS1c provided with the drive device can be easily tested without overheating.

Fifth embodiment

The gate voltage monitoring circuit 15 according to the first to fourth embodiments may use a comparator provided in an active mirror clamp circuit which will be described later. This suppresses an increase in the circuit scale of the gate driver circuit 10. Additionally, the active mirror clamp circuit may have a function of detecting whether noise is generated in the gate of the power transistor TR1, which is liable to cause erroneous ignition. Hereinafter, a detailed description will be given.

First, a general active mirror clamp circuit will be described. In general, when the collector voltage of the off-state power transistor TR1 rises sharply, the rise in the collector voltage propagates to the gate through a feedback capacitor formed between the gate and the collector, and the gate voltage Vg rises unintentionally. Here, if the gate voltage Vg rises above the threshold voltage of the power transistor TR1, the power transistor TR1 is unintentionally turned on, and thus the power transistor TR1 may be unintentionally damaged or deteriorated. To solve such a problem, the gate drive circuit 10 is generally provided with an active mirror clamp circuit for clamping the gate of the power transistor TR 1.

Fig. 9 is a diagram showing a configuration example of the active mirror clamp circuit 20. As shown in fig. 9, the active mirror clamp circuit 20 includes a comparator 21, a switch circuit 22, a buffer 23, and an N-channel MOS transistor MN1 (switching element; hereinafter simply referred to as transistor).

The comparator 21 compares the gate voltage Vg of the power transistor TR1 with the reference voltage Vr, and outputs the comparison result. Specifically, the comparator 21 outputs the comparison result of the L level when the gate voltage Vg is equal to or higher than the reference voltage Vr, and the comparator 21 outputs the comparison result of the H level when the gate voltage Vg is smaller than the reference voltage Vr. Note that the reference voltage Vr indicates a value lower than a boundary value (threshold) at which the power transistor TR1 is turned on and off.

The switch circuit 22 switches the power transistor TR1 from on to off in response to a control signal in (out) output from the control circuit 17 switching from H level to L level. Then, the gate voltage Vg is further decreased to be less than the reference voltage Vr, and the switching circuit 22 switches the control signal AMC from the L level to the H level.

The control signal AMC is applied to the gate of the transistor MN1 via the buffer 23. The transistor MN1 is provided between the gate of the power transistor TR1 and the ground voltage terminal, and is turned on and off based on the control signal AMC. For example, when the control signal AMC is switched from the L level to the H level, the transistor TR1 is switched from the off state to the on state in response to the control signal AMC. Therefore, the gate voltage Vg of the power transistor TR1 rapidly drops to the ground level. Note that even during a period IN which the control signal IN indicates the L level, when the gate voltage Vg temporarily rises above the reference voltage Vr, the switch circuit 22 continues to output the control signal AMC at the H level. Therefore, the gate voltage Vg of the power transistor TR1 is maintained at the ground level.

At this time, the gate voltage Vg of the power transistor TR1 is directly fixed to the ground level without passing through the resistor Rg. Therefore, even when collector voltage Vc of power transistor TR1 in the off state sharply rises, the rise of gate voltage Vg is suppressed. Therefore, the power transistor TR1 does not turn on unintentionally, thereby suppressing breakdown and unintentional degradation of the power transistor TR 1.

During the turn-off of the power transistor TR1, the gate voltage Vg is controlled by the control signal OUT supplied from the control circuit 17 via the resistor Rg until the gate voltage Vg falls below a boundary value (threshold) at which the power transistor TR1 turns on and off. Further, during the on process of the power transistor TR1, the gate voltage Vg is controlled by the control signal OUT supplied from the control circuit 17 via the resistor Rg. Therefore, the on/off switching speed of the power transistor TR1 can be controlled to a desired speed by the control circuit 17 without being affected by the clamping of the active mirror clamp circuit 20.

Next, an active mirror clamp circuit according to the present embodiment having a function of detecting occurrence of noise in the gate of the power transistor TR1 will be described. In the following explanation, the comparator provided in the active mirror clamp circuit according to the present embodiment is also used as the gate voltage monitoring circuit 15.

Fig. 10 is a diagram showing a configuration example of a power supply system SYS1d according to the fifth embodiment. As shown in fig. 10, the power supply system SYS1d includes a power transistor TR1 and a driving device 1d for driving the power transistor TR 1. The driving device 1d includes at least a gate driving circuit 10d, a control circuit 17, and a resistor Rg. In the example shown in fig. 10, components corresponding to the abnormality monitoring circuit 11 among the components of the gate drive circuit 10d are omitted. Thus, the sensor 16 is also omitted.

The gate drive circuit 10d includes a comparator 21, a switch circuit 22d, a buffer 23, and a transistor MN1, which are constituent elements of the active mirror clamp circuit 20. Specifically, the gate drive circuit 10D includes the comparator 21, the switch circuit 22D, the buffer 14, the buffer 23, the transistor MN1, the register 123, and the D/a converter 124. The comparator 21 also functions as the gate voltage monitoring circuit 15. The switch circuit 22d also functions as the logic circuit 13. The register 123 and the DA converter 124 function as a setting circuit for setting the level of the reference voltage Vr. The level of the reference voltage Vr is adjustable.

The switch circuit 22d is a modified example of the switch circuit 22, and has, for example, an SR latch circuit 221 and a logical product circuit 222. IN the SR latch circuit 221, the control signal IN from the control circuit 17 is input to the reset terminal R, the comparison result Vcmp of the comparator 21 is input to the set terminal S, and the control signal AMC is output from the output terminal Q. In this example, reset is prioritized when set and reset of the SR latch circuit 221 are simultaneously input. The logical product circuit 222 outputs a logical product of the control signal AMC and the inverted signal of the comparison result of the comparator 21 as an error signal ERR 2.

Fig. 11 is a truth table of input signals and output signals of the gate driving circuit 10 d. Fig. 12 is a timing chart showing the operation of the gate drive circuit 10 d. As shown IN fig. 11 and 12, when the control signal IN output from the control circuit 17 is at the H level, the control signal AMC indicates the L level regardless of the comparison result Vcmp, and the error signal ERR2 indicates the L level. Thereafter, when the control signal IN is switched from the H level to the L level, the voltage of the control signal OUT, i.e., the gate voltage Vg, decreases according to the change. However, during a period in which the voltage Vg of the control signal OUT is equal to or higher than the reference voltage Vr (e.g., 3V), the comparison result Vcmp indicates the L level. At this time, the control signal AMC indicates an L level, and the error signal ERR2 indicates an L level indicating that an error has not occurred.

Since the control signal AMC indicates the L level, the transistor MN1 is turned off. Thereafter, when the voltage Vg of the control signal OUT becomes smaller than the reference voltage Vr, the comparison result Vcmp is switched from the L level to the H level. Therefore, the control signal AMC switches from the L level to the H level. The error signal ERR2 maintains the L level.

Since the control signal AMC indicates the H level, the transistor MN1 is turned on. After that, when the voltage Vg of the control signal OUT temporarily becomes equal to or higher than the reference voltage Vr due to noise or the like, the comparison result Vcmp temporarily switches to the L level even if the control signal IN indicates the L level. At this time, the error signal ERR2 switches from the L level to the H level, indicating that the gate voltage Vg rises unintentionally. At this time, the control signal AMC maintains the H level. Therefore, the transistor MN1 remains in the on state.

Upon receiving the H-level error signal ERR2, the control circuit 17 stops the operation of the gate drive circuit 10d, or notifies the user that the power transistor TR1 is not operating correctly, for example.

At this time, the control circuit 17 can suppress the degree of increase in noise generated in the gate voltage Vg by, for example, reducing the switching speed of the power transistor TR1 or adjusting various other parameters.

Before the normal operation, for example, by performing the switching control of the power transistor TR1 while adjusting the reference voltage Vr, it can be observed that the value of the gate voltage Vg including the noise component has a degree of margin until the gate voltage Vg reaches the threshold for switching the power transistor TR1 from off to on. The control circuit 17 can effectively adjust the switching speed by using the observation result.

For example, the threshold of the gate voltage Vg at which the power transistor TR1 switches from the off state to the on state is set to 5.0V. Additionally, it is assumed that the gate voltage Vg is allowed to rise up to 2.0V due to the switching operation. In this example, in the case where the reference voltage Vr is set to 2.0V, by increasing the gate drive current as much as possible and increasing the switching speed in a range where an error is not detected, it is possible to automatically search for a parameter setting value capable of suppressing a switching loss and preventing a false ignition due to a switching operation. When the search and adjustment of the parameter setting value are completed, the value of the register 123 is rewritten by the control circuit 17, and the reference voltage Vr returns to the level (e.g., 3V) used in the normal operation.

Therefore, the driving device 1c and the power supply system SYS1d having the driving device 1c according to the present embodiment realize the gate voltage monitoring circuit 15 with the comparator provided in the active mirror clamp circuit. Therefore, the drive device 1c and the power supply system SYS1d having the drive device 1c can suppress an increase in circuit size.

In the drive device 1 according to the present embodiment and the power supply system SYS1d including the drive device 1, the active mirror clamp circuit has a function of detecting whether or not noise is generated at the gate of the power transistor TR1, which may cause erroneous ignition. Therefore, the drive device 1 and the power supply system SYS1d having the drive device can adjust the switching speed to reduce noise when noise that may cause erroneous ignition is detected at the gate of the power transistor TR1, for example. Thereby improving safety.

As described above, the driving device, the power supply system, and the test method of the driving device according to the first to fifth embodiments are configured to test the abnormality monitoring circuit 11 and the gate voltage monitoring circuit 15 after adjusting the threshold voltage Vt, so that when the operation mode is the test mode, if the abnormality monitoring circuit 11 operates normally, it is determined that the state of stress applied to the power transistor TR1 is abnormal. Therefore, the driving apparatus and the power supply system according to the above-described first to fifth embodiments can monitor the state of stress applied to the power transistor TR1 by using the highly reliable abnormality monitoring circuit 11 and the gate voltage monitoring circuit 15. The safety of the drive device and the power supply system can be improved.

Although the invention made by the inventors has been specifically described based on the embodiments, the invention is not limited to the embodiments that have been described, and needless to say, various modifications can be made without departing from the gist thereof.

In the first to fifth embodiments described above, the power transistor TR1 is an IGBT, but is not limited to an IGBT. The power transistor TR1 may be, for example, a transistor such as a MOSFET other than an IGBT.

Further, in the above-described first to fifth embodiments, the example when the gate voltage monitoring circuit 15 (or a circuit equivalent thereto) is provided has been described, but is not limited thereto. In the abnormality monitoring circuit 11 (or a circuit corresponding thereto) and the gate voltage monitoring circuit 15 (or a circuit corresponding thereto), at least only the abnormality monitoring circuit 11 is required.

For example, in the above-described embodiments according to the semiconductor device, the conductivity type (p-type or n-type) of the semiconductor substrate, the semiconductor layer, the diffusion layer (diffusion region), or the like may be inverted. Accordingly, in the case where one of the n-type and p-type conductivity types is the first conductivity type and the other conductivity type is the second conductivity type, the first conductivity type may be the p-type and the second conductivity type may be the n-type, or conversely, the first conductivity type may be the n-type and the second conductivity type may be the p-type.