High-low frequency gain-adjustable analog equalizer
阅读说明：本技术 一种高低频增益可调的模拟均衡器 (High-low frequency gain-adjustable analog equalizer ) 是由 段吉海 朱岛 韦保林 徐卫林 韦雪明 岳宏卫 于 2020-07-29 设计创作，主要内容包括：本发明公开一种高低频增益可调的模拟均衡器,由2个有源负载网络、3个均衡电路和1个有源反馈电路组成；2个有源负载网络包括第一有源负载网络和第二有源负载网络；3个均衡电路包括第一低频细调均衡电路、第二低频细调均衡电路和低频粗调均衡电路。第一低频细调均衡电路和第二低频细调均衡电路的输入端形成本模拟均衡器的输入端。第一有源负载网络、第一低频细调均衡电路、第二低频细调均衡电路和有源反馈电路的输出端与低频粗调均衡电路的输入端连接；第二有源负载网络的输出端、低频粗调均衡电路的输出端和有源反馈电路的输入端形成本模拟均衡器的输出端。本发明能够提升整体均衡能力,增加了低频细调的可调范围,降低版图面积。(The invention discloses a high-low frequency gain-adjustable analog equalizer, which consists of 2 active load networks, 3 equalizing circuits and 1 active feedback circuit; the 2 active load networks comprise a first active load network and a second active load network; the 3 equalizing circuits comprise a first low-frequency fine-tuning equalizing circuit, a second low-frequency fine-tuning equalizing circuit and a low-frequency coarse-tuning equalizing circuit. The input terminals of the first low-frequency fine tuning equalizing circuit and the second low-frequency fine tuning equalizing circuit form the input terminals of the analog equalizer. The output ends of the first active load network, the first low-frequency fine tuning and balancing circuit, the second low-frequency fine tuning and balancing circuit and the active feedback circuit are connected with the input end of the low-frequency coarse tuning and balancing circuit; the output end of the second active load network, the output end of the low-frequency coarse tuning balancing circuit and the input end of the active feedback circuit form the output end of the analog equalizer. The invention can improve the integral balance capability, increase the adjustable range of low-frequency fine adjustment and reduce the layout area.)
1. A high-low frequency gain adjustable analog equalizer is characterized by comprising 2 active load networks, 3 equalizing circuits and 1 active feedback circuit; the 2 active load networks comprise a first active load network and a second active load network; the 3 equalizing circuits comprise a first low-frequency fine-tuning equalizing circuit, a second low-frequency fine-tuning equalizing circuit and a low-frequency coarse-tuning equalizing circuit;
after the input end VIN of the first low-frequency fine tuning equalizing circuit is connected with the input end VIN of the second low-frequency fine tuning equalizing circuit, the input end VIN of the analog equalizer is formed;
after the input end VIP of the first low-frequency fine tuning equalizing circuit is connected with the input end VIP of the second low-frequency fine tuning equalizing circuit, the input end VIP of the analog equalizer is formed;
the output end von of the first active load network is connected with the output end von of the first low-frequency fine tuning balancing circuit, the output end von of the second low-frequency fine tuning balancing circuit, the output end von fb of the active feedback circuit and the input end vin of the low-frequency coarse tuning balancing circuit;
the output end vopr of the first active load network is connected with the output end vop of the first low-frequency fine tuning and balancing circuit, the output end vop of the second low-frequency fine tuning and balancing circuit, the output end vopfb of the active feedback circuit and the input end vip of the low-frequency coarse tuning and balancing circuit;
after the output end VON of the second active load network, the output end VON of the low-frequency coarse tuning equalization circuit and the input end vipfb of the active feedback circuit are connected, the output end VON of the analog equalizer is formed;
and after the output end vopr of the second active load network, the output end VOP of the low-frequency coarse tuning balancing circuit and the input end vinfb of the active feedback circuit are connected, the output end VOP of the analog equalizer is formed.
2. The analog equalizer with adjustable gain according to claim 1, wherein the first low frequency fine tuning equalization circuit, the second low frequency fine tuning equalization circuit and the low frequency coarse tuning equalization circuit have the same structure.
3. The analog equalizer with adjustable high and low frequency gains as claimed in claim 1 or 2, wherein each equalizing circuit comprises a MOS transistor NM1-5, a feedback resistor R1 and a feedback capacitor C1; the MOS transistor NM1-5 is an NMOS transistor;
the drain electrode of the MOS tube NM1 forms the output end von of the equalization circuit; the gate of the MOS transistor NM1 forms the input vin of the equalization circuit; the source electrode of the MOS transistor NM1, one end of the feedback resistor R1, one end of the feedback capacitor C1, the drain electrode of the MOS transistor NM3 and the drain electrode of the MOS transistor NM4 are connected; the drain electrode of the MOS tube NM2 forms the output end vop of the equalizing circuit; the gate of the MOS transistor NM2 forms the input end vip of the equalization circuit; the source electrode of the MOS transistor NM2, the other end of the feedback resistor R1, the other end of the feedback capacitor C1, the source electrode of the MOS transistor NM3 and the drain electrode of the MOS transistor NM5 are connected; the grid electrode of the MOS tube NM3 is connected with a control voltage VCL; the source electrode of the MOS transistor NM4 and the source electrode of the MOS transistor NM5 are grounded; the gate of the MOS transistor NM4 and the gate of the MOS transistor NM5 are connected to the control voltage vb.
4. The analog equalizer of claim 1, wherein the first active load network and the second active load network are identical in structure.
5. The analog equalizer with adjustable high and low frequency gains as claimed in claim 1 or 4, wherein each active load network comprises a MOS transistor PM1-4, a MOS transistor NM20-23 and a load resistor R4-5; wherein the MOS transistor PM1-4 is a PMOS transistor, and the MOS transistor NM20-23 is an NMOS transistor;
the source electrode of the MOS pipe PM1 is connected with a power supply VDD; the grid electrode of the MOS transistor PM1 is connected with the drain electrode of the MOS transistor PM3 and the drain electrode of the MOS transistor NM21, and the drain electrode of the MOS transistor PM1 is connected with the source electrode of the MOS transistor PM3 and one end of the resistor R4; the other end of the resistor R4 forms an output end von of the active load network; the grid electrode of the MOS tube PM3 is connected with a high-frequency control voltage VC; the grid electrode of the MOS transistor NM21, the grid electrode of the MOS transistor NM20 and the drain electrode of the MOS transistor NM20 are connected with a control current IC; the sources of the MOS transistor NM20 and the MOS transistor NM21 are grounded;
the source electrode of the MOS pipe PM2 is connected with a power supply VDD; the grid electrode of the MOS transistor PM2 is connected with the drain electrode of the MOS transistor PM4 and the drain electrode of the MOS transistor NM23, and the drain electrode of the MOS transistor PM2 is connected with the source electrode of the MOS transistor PM4 and one end of the resistor R5; the other end of the resistor R5 forms an output end vopr of the active load network; the grid electrode of the MOS tube PM4 is connected with a high-frequency control voltage VC; the grid electrode of the MOS transistor NM23, the grid electrode of the MOS transistor NM22 and the drain electrode of the MOS transistor NM22 are connected with a control current IC; the sources of the MOS transistor NM22 and the MOS transistor NM23 are grounded.
6. The analog equalizer with adjustable gain according to claim 1, wherein the active feedback circuit comprises MOS transistors NM 11-14; the MOS transistor NM11-14 is an NMOS transistor;
the gate of the MOS transistor NM11 forms the input end vinfb of the active feedback circuit; the drain electrode of the MOS tube NM11 forms the output end von fb of the active feedback circuit; the source electrode of the MOS tube NM11 is connected with the drain electrode of the MOS tube NM 13; the grid electrode of the MOS tube NM13 is connected with the control voltage vb, and the source electrode of the MOS tube NM13 is grounded;
the gate of the MOS transistor NM12 forms the input end vipfb of the active feedback circuit; the drain electrode of the MOS tube NM12 forms the output end vopfb of the active feedback circuit; the source electrode of the MOS tube NM12 is connected with the drain electrode of the MOS tube NM 14; the gate of the MOS transistor NM14 is connected to the control voltage vb, and the source of the MOS transistor NM14 is grounded.
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an analog equalizer with adjustable high and low frequency gains.
Background
Due to the large amount of data generated, the demand for transmission data rate is also increasing. However, in a serial communication system, there are non-ideal factors such as dielectric loss and skin effect in a wired channel such as a transmission line and a coaxial cable, and these non-ideal factors attenuate a signal, and the attenuation amplitude increases as the data rate increases. The more serious the attenuation is, the more the integrity of the signal is affected, the more the normal judgment of a receiving end circuit is affected, and the bit error rate of the system is increased.
In order to reduce the error rate in a high-speed serial communication system, an equalizer having a compensation effect on high-frequency signals is usually added at a receiving end, so as to achieve the effect of weakening the attenuation of limited channels to the signals and obtain a relatively flat overall frequency response. Different wire channels, whose attenuation is different, are transmitted in a serial communication system; the same wired channel, but different channel lengths, with different attenuations; the same wired channel, the same channel length, but different data rates, will also have different attenuations. Since the attenuation of the channel is unpredictable and time-varying, it is desirable that the gain of the equalizer be adjustable to account for different channel attenuations. However, when the existing equalizer faces strong attenuation channel equalization, the problems of low-frequency adjustable range and irreconcilable layout area of high-frequency peak gain exist.
Disclosure of Invention
The invention aims to solve the problems that the low-frequency adjustable range is low and the high-frequency peak gain is not adjustable and the layout area is too large when the existing equalizer equalizes a strong attenuation channel, and provides an analog equalizer with adjustable high-frequency and low-frequency gains.
In order to solve the problems, the invention is realized by the following technical scheme:
an analog equalizer with adjustable high and low frequency gains is composed of 2 active load networks, 3 equalizing circuits and 1 active feedback circuit. The 2 active load networks include a first active load network and a second active load network. The 3 equalizing circuits comprise a first low-frequency fine-tuning equalizing circuit, a second low-frequency fine-tuning equalizing circuit and a low-frequency coarse-tuning equalizing circuit. The input end VIN of the first low-frequency fine tuning equalization circuit is connected with the input end VIN of the second low-frequency fine tuning equalization circuit to form the input end VIN of the analog equalizer. And after the input end VIP of the first low-frequency fine tuning equalizing circuit is connected with the input end VIP of the second low-frequency fine tuning equalizing circuit, the input end VIP of the analog equalizer is formed. The output end von of the first active load network is connected with the output end von of the first low-frequency fine tuning and balancing circuit, the output end von of the second low-frequency fine tuning and balancing circuit, the output end von fb of the active feedback circuit and the input end vin of the low-frequency coarse tuning and balancing circuit. The output end vopr of the first active load network is connected with the output end vop of the first low-frequency fine tuning and balancing circuit, the output end vop of the second low-frequency fine tuning and balancing circuit, the output end vopfb of the active feedback circuit and the input end vip of the low-frequency coarse tuning and balancing circuit. And after the output end VON of the second active load network, the output end VON of the low-frequency coarse tuning and balancing circuit and the input end vipfb of the active feedback circuit are connected, the output end VON of the analog equalizer is formed. And after the output end vopr of the second active load network, the output end VOP of the low-frequency coarse tuning balancing circuit and the input end vinfb of the active feedback circuit are connected, the output end VOP of the analog equalizer is formed.
In the above scheme, the first low-frequency fine tuning and equalizing circuit, the second low-frequency fine tuning and equalizing circuit and the low-frequency coarse tuning and equalizing circuit have the same structure.
In the scheme, each equalization circuit comprises a MOS transistor NM1-5, a feedback resistor R1 and a feedback capacitor C1. The MOS transistor NM1-5 is an NMOS transistor. The drain of the MOS transistor NM1 forms the output von of the equalization circuit. The gate of the MOS transistor NM1 forms the input vin of the equalization circuit. The source electrode of the MOS transistor NM1, one end of the feedback resistor R1, one end of the feedback capacitor C1, the drain electrode of the MOS transistor NM3 and the drain electrode of the MOS transistor NM4 are connected. The drain of the MOS transistor NM2 forms the output vop of the equalization circuit. The gate of the MOS transistor NM2 forms the input vip of the equalization circuit. The source of the MOS transistor NM2, the other end of the feedback resistor R1, the other end of the feedback capacitor C1, the source of the MOS transistor NM3 and the drain of the MOS transistor NM5 are connected. The gate of the MOS transistor NM3 is connected to the control voltage VCL. The source of the MOS transistor NM4 and the source of the MOS transistor NM5 are grounded. The gate of the MOS transistor NM4 and the gate of the MOS transistor NM5 are connected to the control voltage vb.
In the above scheme, the first active load network and the second active load network have the same structure.
In the scheme, each active load network comprises an MOS transistor PM1-4, an MOS transistor NM20-23 and a load resistor R4-5. Wherein, the MOS transistor PM1-4 is a PMOS transistor, and the MOS transistor NM20-23 is an NMOS transistor. The source of the MOS transistor PM1 is connected to the power supply VDD. The gate of MOS transistor PM1 is connected to the drain of MOS transistor PM3 and the drain of MOS transistor NM21, and the drain of MOS transistor PM1 is connected to the source of MOS transistor PM3 and one end of resistor R4. The other end of the resistor R4 forms the output von of the active load network. The gate of the MOS transistor PM3 is connected to the high-frequency control voltage VC. The grid of the MOS transistor NM21, the grid of the MOS transistor NM20 and the drain of the MOS transistor NM20 are connected with the control current IC. The sources of the MOS transistor NM20 and the MOS transistor NM21 are grounded. The source of the MOS transistor PM2 is connected to the power supply VDD. The gate of MOS transistor PM2 is connected to the drain of MOS transistor PM4 and the drain of MOS transistor NM23, and the drain of MOS transistor PM2 is connected to the source of MOS transistor PM4 and one end of resistor R5. The other end of resistor R5 forms the output vopr of the active load network. The gate of the MOS transistor PM4 is connected to the high-frequency control voltage VC. The grid of the MOS transistor NM23, the grid of the MOS transistor NM22 and the drain of the MOS transistor NM22 are connected with the control current IC. The sources of the MOS transistor NM22 and the MOS transistor NM23 are grounded.
In the scheme, the active feedback circuit comprises a MOS transistor NM 11-14. The MOS transistor NM11-14 is an NMOS transistor. The gate of the MOS transistor NM11 forms the input vinfb of the active feedback circuit. The drain of the MOS transistor NM11 forms the output terminal von fb of the active feedback circuit. The source of the MOS transistor NM11 is connected with the drain of the MOS transistor NM 13. The gate of the MOS transistor NM13 is connected to the control voltage vb, and the source of the MOS transistor NM13 is grounded. The gate of the MOS transistor NM12 forms the input terminal vipfb of the active feedback circuit. The drain of the MOS transistor NM12 forms the output terminal vopfb of the active feedback circuit. The source of the MOS transistor NM12 is connected with the drain of the MOS transistor NM 14. The gate of the MOS transistor NM14 is connected to the control voltage vb, and the source of the MOS transistor NM14 is grounded.
Compared with the prior art, the invention has the following characteristics:
1. the input of the equalizing circuit adopts a parallel structure, so that the adjustable range of low-frequency fine adjustment is increased while the integral equalizing capacity is improved.
2. The low-frequency coarse adjustment and equalization circuit and the low-frequency fine adjustment and equalization circuit are connected in series, and the capacity of equalizing a high-attenuation channel is improved.
3. The data with high transmission rate can be balanced, and the gain with the peak value of 16dB can be provided for the data with the transmission rate of 15 Gbps.
4. The active inductor is adopted to provide the capacity of induction peaking for the equalizer, the layout area is reduced while the equalizing capacity is improved, and the high-frequency peak value gain of the equalizer is adjustable because the inductance value of the active inductor is adjustable.
Drawings
Fig. 1 is a schematic circuit diagram of a high and low frequency gain-adjustable analog equalizer.
Fig. 2 is a simulation result of the amplitude-frequency characteristic curve of the present invention.
Fig. 3 shows simulation results of amplitude-frequency characteristic curves of different VCLs.
Fig. 4 shows simulation results of different amplitude-frequency characteristic curves of VCH control voltage.
Fig. 5 shows simulation results of amplitude-frequency characteristic curves of different VCH and VCL control voltages.
Fig. 6 shows the change of the inductance of the active inductor in the first active load network under different VC control voltages.
Fig. 7 shows the change of the inductance of the active inductor in the second active load network for different VC control voltages.
Fig. 8 shows simulation results of amplitude-frequency characteristic curves of different VC, VCH and VCL control voltages.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings in conjunction with specific examples.
An analog equalizer with adjustable high and low frequency gains is shown in fig. 1 and comprises 2 active load networks, 3 equalizing circuits and 1 active feedback circuit. The 2 active load networks include a first active load network and a second active load network. The 3 equalizing circuits comprise a first low-frequency fine-tuning equalizing circuit, a second low-frequency fine-tuning equalizing circuit and a low-frequency coarse-tuning equalizing circuit. The input end VIN of the first low-frequency fine tuning equalization circuit is connected with the input end VIN of the second low-frequency fine tuning equalization circuit to form the input end VIN of the analog equalizer. And after the input end VIP of the first low-frequency fine tuning equalizing circuit is connected with the input end VIP of the second low-frequency fine tuning equalizing circuit, the input end VIP of the analog equalizer is formed. The output end von of the first active load network is connected with the output end von of the first low-frequency fine tuning and balancing circuit, the output end von of the second low-frequency fine tuning and balancing circuit, the output end von fb of the active feedback circuit and the input end vin of the low-frequency coarse tuning and balancing circuit. The output end vopr of the first active load network is connected with the output end vop of the first low-frequency fine tuning and balancing circuit, the output end vop of the second low-frequency fine tuning and balancing circuit, the output end vopfb of the active feedback circuit and the input end vip of the low-frequency coarse tuning and balancing circuit. And after the output end VON of the second active load network, the output end VON of the low-frequency coarse tuning and balancing circuit and the input end vipfb of the active feedback circuit are connected, the output end VON of the analog equalizer is formed. And after the output end vopr of the second active load network, the output end VOP of the low-frequency coarse tuning balancing circuit and the input end vinfb of the active feedback circuit are connected, the output end VOP of the analog equalizer is formed.
The first low-frequency fine tuning equalization circuit comprises an NMOS tube NM1-5, a feedback resistor R1 and a feedback capacitor C1. The MOS transistor NM1 and the MOS transistor NM2 are differential pair amplifying transistors, and a parallel network formed by the feedback resistor R1, the feedback capacitor C1 and the MOS transistor NM3 is a source negative feedback network of a differential pair. The MOS transistor NM4 and the MOS transistor NM5 are tail current transistors of a differential pair. The drain of the MOS transistor NM1 forms the output terminal von1 of the first low-frequency fine tuning equalization circuit, the gate of the MOS transistor NM1 forms the input terminal vin1 of the first low-frequency fine tuning equalization circuit, and the source of the MOS transistor NM1, one end of the feedback resistor R1, one end of the feedback capacitor C1, the drain of the MOS transistor NM3 and the drain of the MOS transistor NM4 are connected. The drain of the MOS transistor NM2 forms the output end vop1 of the first low-frequency fine tuning equalization circuit, the gate of the MOS transistor NM2 forms the input end vip1 of the first low-frequency fine tuning equalization circuit, and the source of the MOS transistor NM2, the other end of the feedback resistor R1, the other end of the feedback capacitor C1, the source of the MOS transistor NM3 and the drain of the MOS transistor NM5 are connected. The gate of the MOS transistor NM3 is connected to the control voltage VCL. The source of the MOS transistor NM4 and the source of the MOS transistor NM5 are grounded, and the gate of the MOS transistor NM4 and the gate of the MOS transistor NM5 are connected to the control voltage vb.
The second low-frequency fine tuning equalization circuit comprises an NMOS tube NM6-10, a feedback resistor R2 and a
The low-frequency coarse tuning and equalizing circuit comprises NMOS tubes NM15-19, a feedback capacitor C3 and a feedback resistor R3. The MOS transistor NM15 and the MOS transistor NM16 are differential pair amplifying transistors, and a parallel network formed by the feedback resistor R3, the feedback capacitor C3 and the MOS transistor NM17 is a source negative feedback network of a differential pair. The MOS transistor NM18 and the MOS transistor NM19 are tail current transistors of a differential pair. The gate of the MOS transistor NM15 forms an input terminal vin3 of the low-frequency coarse tuning and equalizing circuit, the drain of the MOS transistor NM15 forms an output terminal von3 of the low-frequency coarse tuning and equalizing circuit, and the source of the MOS transistor NM15, one end of the feedback capacitor C3, one end of the feedback resistor R3, and the drains of the MOS transistor NM17 and the MOS transistor NM18 are connected. The gate of the MOS transistor NM18 is connected to the control voltage vb, and the source of the MOS transistor NM18 is grounded. The gate of the MOS transistor NM16 forms an input end vip3 of the low-frequency coarse tuning and equalizing circuit, the drain of the MOS transistor NM16 forms an output end vop3 of the low-frequency coarse tuning and equalizing circuit, and the source of the MOS transistor NM16, the other end of the feedback capacitor C3, the other end of the feedback resistor R3, the source of the MOS transistor NM17, and the drain of the MOS transistor NM19 are connected. The gate of the MOS transistor NM19 is connected to the control voltage vb, the source of the MOS transistor NM19 is grounded, and the gate of the MOS transistor NM17 is connected to the external control voltage VCH.
The first active load network comprises a PMOS pipe PM1-4, an NMOS pipe NM20-23 and a load resistor R4-5. The source of MOS pipe PM1 is connected with power VDD, the gate of MOS pipe PM1 is connected with the drain of MOS pipe PM3 and the drain of MOS pipe NM21, and the drain of MOS pipe PM1 is connected with the source of MOS pipe PM3 and one end of resistor R4. The other end of the resistor R4 forms the output von1 of the first active load network and connects the output von1 of the first low frequency fine tuning equalization circuit and the output von2 of the second low frequency fine tuning equalization circuit. The gate of the MOS transistor PM3 is connected to the high-frequency control voltage VC. The source electrode of the MOS transistor NM21 is grounded, the grid electrode of the MOS transistor NM21, the grid electrode of the MOS transistor NM20 and the drain electrode of the MOS transistor NM20 are connected with the control current IC, and the source electrode of the MOS transistor NM20 is grounded. The source of MOS pipe PM2 is connected with power VDD, the gate of MOS pipe PM2 is connected with the drain of MOS pipe PM4 and the drain of MOS pipe NM23, and the drain of MOS pipe PM2 is connected with the source of MOS pipe PM4 and one end of resistor R5. The other end of the resistor R5 forms the output vop1 of the first active load network and connects the output vopr1 of the first low frequency fine tuning equalization circuit and the output vop2 of the second low frequency fine tuning equalization circuit. The gate of the MOS transistor PM4 is connected to the high-frequency control voltage VC. The source electrode of the MOS transistor NM23 is grounded, the grid electrode of the MOS transistor NM23, the grid electrode of the MOS transistor NM22 and the drain electrode of the MOS transistor NM22 are connected with the control current IC, and the source electrode of the MOS transistor NM22 is grounded.
The second active load network comprises a PMOS tube PM5-8, an NMOS tube NM24-27 and a load resistor R6-7. The source of MOS pipe PM5 is connected with power VDD, the gate of MOS pipe PM5 is connected with the drain of MOS pipe PM7 and the drain of MOS pipe NM25, and the drain of MOS pipe PM5 is connected with the source of MOS pipe PM7 and one end of resistor R6. The other end of the resistor R6 forms an output terminal von2 of the second active load network and is connected with an output terminal von3 of the low-frequency coarse tuning and balancing circuit. The gate of the MOS transistor PM7 is connected to the high-frequency control voltage VC. The source electrode of the MOS transistor NM25 is grounded, the grid electrode of the MOS transistor NM25, the grid electrode of the MOS transistor NM24 and the drain electrode of the MOS transistor NM24 are connected with the control current IC, and the source electrode of the MOS transistor NM24 is grounded. The source of MOS pipe PM6 is connected with power VDD, the gate of MOS pipe PM6 is connected with the drain of MOS pipe PM8 and the drain of MOS pipe NM27, and the drain of MOS pipe PM6 is connected with the source of MOS pipe PM8 and one end of resistor R7. The other end of the resistor R7 forms an output terminal vopr2 of the second active load network and is connected with an output vop3 of the low-frequency coarse tuning and balancing circuit. The gate of the MOS transistor PM8 is connected to the high-frequency control voltage VC. The source electrode of the MOS transistor NM27 is grounded, the grid electrode of the MOS transistor NM27, the grid electrode of the MOS transistor NM26 and the drain electrode of the MOS transistor NM26 are connected with the control current IC, and the source electrode of the MOS transistor NM26 is grounded.
The active feedback circuit comprises an NMOS transistor NM 11-14. The MOS transistor NM11 and the MOS transistor NM12 are differential pair amplifying transistors. The MOS transistor NM13 and the MOS transistor NM14 are tail current transistors of a differential pair. The gate of the MOS transistor NM11 forms the input terminal vinfb of the active feedback circuit, the drain of the MOS transistor NM11 forms the output terminal von fb of the active feedback circuit, and the source of the MOS transistor NM11 is connected to the drain of the MOS transistor NM 13. The gate of the MOS transistor NM13 is connected to the control voltage vb, and the source of the MOS transistor NM13 is grounded. The gate of the MOS transistor NM12 forms the input end vipfb of the active feedback circuit, the drain of the MOS transistor NM12 forms the output end vopfb of the active feedback circuit, and the source of the MOS transistor NM12 is connected to the drain of the MOS transistor NM 14. The gate of the MOS transistor NM14 is connected to the control voltage vb, and the source of the MOS transistor NM14 is grounded.
The MOS transistor NM1-27 is an NMOS transistor with the standard voltage of 1.8V, and the MOS transistor PM1-8 is a PMOS transistor with the standard voltage of 1.8V.
The first low-frequency fine tuning equalizing circuit, the second low-frequency fine tuning equalizing circuit and the low-frequency coarse tuning equalizing circuit have the same structure, namely, the first low-frequency fine tuning equalizing circuit, the second low-frequency fine tuning equalizing circuit and the low-frequency coarse tuning equalizing circuit are all composed of a differential pair with capacitance resistance source negative feedback, and due to the source negative feedback effect of the capacitance resistance, the differential pair generates a zero point on the left side of a complex frequency domain and a pole. The position of the zero point is related to the size of the feedback resistor and the feedback capacitor, and when the gain curve passes through the zero point, the gain rises, so that the compensation effect on the channel attenuation after the zero point can be realized. In addition, the structure that the first low-frequency fine tuning equalizing circuit and the second low-frequency fine tuning equalizing circuit are connected in parallel and the low-frequency coarse tuning equalizing circuit is connected in series is adopted, so that the whole equalizing circuit can generate three zeros and five poles, when a gain curve passes through each zero, the slope of the gain curve rises at 20dB/dec, the values of the feedback resistor and the feedback capacitor are reasonably adjusted, the position relation of the zero and the poles is changed, the gain difference value between high frequency and low frequency can be improved, and the equalizing capacity of a high-loss channel is improved.
The first active load network and the second active load network have the same structure, and the balancing circuit and the corresponding loads are connected in series, namely the low-frequency fine adjustment balancing circuit is connected in series with the first active load network, and the low-frequency coarse adjustment balancing circuit is connected in series with the second active load network. The active load network can be equivalent to an active inductor which is connected with a load resistor in series, the active inductor can provide a zero point and a pole for the equalizer, the existence of the active inductor can be reduced, the load capacitance of the equalizing circuit can be reduced, the frequency point where the pole is located is further increased, the bandwidth of the equalizer is increased, and therefore signals with higher transmission rate can be equalized. The feedback circuit takes the output of the low-frequency coarse adjustment and equalization circuit as input, and the output compensates the output of the low-frequency fine adjustment and equalization circuit, so that zero point jitter of the differential signal is reduced.
For the high-low frequency adjustable analog equalizer shown in fig. 1, a 0.18 μm process design is adopted, and simulation results of fig. 2-8 are obtained through simulation.
In fig. 2, when the fixed control voltage VC is 0. 0V, VCH V and VCL is 0.9V, the amplitude-frequency response of the circuit is shown as 16dB peak, and the frequency corresponding to the peak is 7.7 GHz.
Fig. 3 shows the adjustable range of the amplitude-frequency response when the fixed control voltage VC is 0V, VCH V and 0.9V, and the adjustable range of the low frequency fine tuning equalizer circuit when the control voltage VCL is changed from 0V to 1.8V, and it can be seen that the low frequency gain is 2dB when VCL is 0V and 4dB when VCL is 1.8V.
Fig. 4 shows the adjustable range of the amplitude-frequency response when the fixed control voltage VC is 0V, VCL V to 0.9V, and the adjustable range of the low-frequency coarse tuning equalizer circuit when the control voltage VCH is changed from 0V to 1.8V, and it can be seen that the low-frequency gain is-1.6 dB when VCH is 0V, and the low-frequency gain is 4.9dB when VCH is 1.8V.
Fig. 5 shows the adjustable range of the amplitude-frequency response when the fixed control voltage VC is 0V and the control voltages VCH and VCL are changed from 0V to 1.8V, and the adjustable range of the low-frequency coarse equalizer and the low-frequency fine equalizer is also the whole adjustable range, and it can be seen that the low-frequency gain is-2.7 dB when VCH is 0V, VCL V and the low-frequency gain is 5.8dB when VCH is 1.8V, VCL V.
Fig. 6-7 show the variation of the inductance of the active inductor in the active load when the control voltage VC is changed from 0V to 0.6V, and the reason why the high frequency of the equalizer is adjustable is that the inductance of the active inductor is adjustable.
Fig. 8 shows the adjustable range of the amplitude-frequency response when the control voltage VC is changed from 0V to 0.6V and the control voltages VCH and VCL are changed from 0V to 1.8V, and the adjustable range of the whole equalizer circuit, it can be seen that the adjustable range of the low frequency is from-6 dB to 6.5dB, and the adjustable range of the high frequency peak is from 11.1dB to 16.1 dB.
It should be noted that, although the above-mentioned embodiments of the present invention are illustrative, the present invention is not limited thereto, and thus the present invention is not limited to the above-mentioned embodiments. Other embodiments, which can be made by those skilled in the art in light of the teachings of the present invention, are considered to be within the scope of the present invention without departing from its principles.
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