阅读说明：本技术 通过一对双绞线或两对双绞线来传输的以太网通信系统 (Ethernet communication system transmitting by one twisted pair or two twisted pairs ) 是由 陈少涵 庄栋明 于 2019-03-28 设计创作，主要内容包括：本发明公开了一种以太网通信系统,只通过两对双绞线来传输,该以太网通信系统包括一个第一收发机及恰好两对双绞线。该第一收发机包括一个第一物理编码子层(physical coding sublayer,PCS)、连接至该第一物理编码子层的两个第一物理媒体衔接(physical medium attachment,PMA)、及分别连接至该两个第一物理媒体衔接的两个第一混合电路。该恰好两对双绞线是分别连接至该第一收发机的这两个第一混合电路。(The invention discloses an Ethernet communication system which only transmits through two pairs of twisted-pair wires. The first transceiver includes a first Physical Coding Sublayer (PCS), two first Physical Media Attachments (PMA) connected to the first physical coding sublayer, and two first hybrid circuits respectively connected to the two first physical media attachments. The exactly two twisted pairs are the two first hybrids connected to the first transceiver, respectively.)

1. An ethernet communication system for transmitting over only two pairs of twisted pair lines, comprising:

a first transceiver, comprising:

a first Physical Coding Sublayer (PCS) which is encoded using a low density parity check code (LDPC);

two first Physical Media Attachment (PMA) connected to the first physical coding sublayer; and

two first hybrid circuits respectively connected to two first physical media links; and

exactly two twisted pairs, each connected to two of the first hybrids of the first transceiver.

2. The ethernet communication system according to claim 1, wherein a data transmission rate of a media independent interface of the ethernet communication system is set to 1.25Gbps for the 2.5G BASE-T standard, 2.5Gbps for the 5G BASE-T standard, and 5.0Gbps for the 10G BASE-T standard.

3. An ethernet communication system according to claim 1, wherein a low density parity check code encoder of the ethernet communication system encodes data bits intended for transmission into 2048 or 1024 encoded bits per 640nsec or per 1280 nsec.

4. An ethernet communication system according to claim 1, wherein a bit mapper of the ethernet communication system maps 2048 coded bits to 512 discrete sixteen-level pulse amplitude modulation symbols or maps 1024 coded bits to 256 discrete sixteen-level pulse amplitude modulation symbols.

5. The Ethernet communication system of claim 1, wherein a Media Independent Interface (MII) data transmission rate of the Ethernet communication system is set to 1.0Gbps for the 2.5G BASE-T standard.

6. The Ethernet communication system of claim 1 wherein a low density parity check code encoder of the Ethernet communication system aggregates 1 auxiliary bit, 10 data blocks of 65 bits each, and an additional 1072 zeros and encodes the 1723 bits into 2048 encoded bits.

7. The Ethernet communication system of claim 1, wherein a low density parity check code encoder of the Ethernet communication system aggregates 1 auxiliary bit, 20 data blocks of 65 bits each, and an additional 422 zeros and encodes the 1723 bits into 2048 encoded bits.

8. An ethernet communication system for transmitting over only one twisted pair, comprising:

a first transceiver, comprising:

a first physical coding sublayer;

a first physical media connection coupled to the first physical coding sublayer; and

a first hybrid circuit coupled to the first physical medium; and

exactly one twisted pair of wires connected to the first hybrid of the first transceiver.

9. The ethernet communication system according to claim 1, wherein a data transmission rate of a media independent interface of the ethernet communication system is set to 0.625Gbps for the 2.5G BASE-T standard, to 1.25Gbps for the 5G BASE-T standard, and to 2.5Gbps for the 10G BASE-T standard.

10. The Ethernet communication system of claim 1, wherein a low density parity check code encoder of the Ethernet communication system encodes 1723 data bits per 1280nsec or per 2560nsec into 2048 encoded bits.

Technical Field

The present invention relates to communication systems, and more particularly to the use of Ethernet (Ethernet).

Background

Ethernet transceiver (transceiver) systems, suitable for example for: the IEEE 2.5G BASE-T, 5G BASE-T, or 10G BASE-T standards all require four twisted pairs for data transmission.

As shown in fig. 1, the ethernet transceiver system 9 includes a first transceiver 10 and a second transceiver 20. The first transceiver 10 comprises four sets of transceiver units, each set comprising a first transmitter 101, a first receiver 102, and a first hybrid circuit 13. The second transceiver 20 also comprises four sets of transceiver units, each set comprising a second transmitter 201, a second receiver 202, and a second hybrid 23. There are four twisted pairs 30 between the first transceiver 10 and the second transceiver 20, respectively connecting the four first hybrids 13 of the first transceiver 10 and the four second hybrids 23 of the second transceiver 20.

In addition, in the 1000BASE-T standard, the transceiver systems are interconnected using separate four to five twisted pair (CAT-5) connections for a single link. In practice, this communication involves the simultaneous parallel transmission of four data signals on four twisted pairs, each at a bit rate of 250 Mbps. The 1000BASE-T standard further requires that the digital data for transmission be represented in discrete five-level pulse amplitude modulation (PAM-5) symbols and encoded in eight state trellis coding. The two-bit PAM-5 symbol actually uses a cable bandwidth of about 80MHz to limit CAT-5 data transmission to 125 MBaud.

Currently, there is a real need for Ethernet communication systems that provide for transmission over non-four twisted pair lines for standards such as 2.5G BASE-T, 5G BASE-T, and 10G BASE-T.

Disclosure of Invention

The present invention is directed to a communication system for transmission over a twisted pair or two twisted pairs, which is applicable to a variety of ethernet networks, such as: 2.5G BASE-T, 5G BASE-T, and 10G BASE-T.

The present invention, when designing such an ethernet communication system for transmission over one twisted pair or two twisted pairs, takes into account at least the following three conditions:

first, the parity-check matrix (parity-check matrix) of the original IEEE 802.3bz and IEEE 802.3an LDPC encoder/decoder is unchanged to avoid adding additional hardware complexity.

Second, the native Baud rate (Baud rate) of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), for example: 200MBaud, 400MBaud, or 800MBaud to avoid enlarging a frequency bandwidth (frequency bandwidth) of a Transmit (TX) signal/Receive (RX) signal and to reduce a connectable transmission distance (loop-reach).

Third, a transmission/reception symbol rate (symbol rate) of pulse amplitude modulation with16 discrete levels (PAM-16) or double square quadrature amplitude modulation (DSQ-128) without changing discrete sixteen levels, for example: 200MHz, 400MHz, or 800 MHz.

Furthermore, compared to ethernet transceivers of IEEE 802.3bz and IEEE 802.3an, the present invention provides a reduced transmission throughput (throughput) without additional Digital Signal Processing (DSP) when using two pairs (two pairs) or one pair (one pair) of twisted pairs, such as: 2.5Gbps, 1.25Gbps, 1.0Gbps, or 0.625 Gbps.

Thus, according to one aspect of the present invention, there is provided an ethernet communication system for transmission over only two pairs of twisted pairs, the ethernet communication system comprising a first transceiver and exactly two pairs of twisted pairs. The first transceiver includes a first physical coding sublayer encoded using a low density parity check code, two first physical medium engagements coupled to the first physical coding sublayer, and two first hybrids coupled to the two first physical medium engagements, respectively. The exactly two twisted pairs are respectively connected to the two first hybrids of the first transceiver.

Alternatively or preferably, the data transmission rate of a media independent interface of the Ethernet communication system is set to 1.25Gbps for the 2.5G BASE-T standard, 2.5Gbps for the 5G BASE-T standard, and 5.0Gbps for the 10G BASE-T standard.

Alternatively or preferably, a low density parity check code encoder of the ethernet communication system encodes data bits intended for transmission into 2048 or 1024 encoded bits per 640nsec or 1280 nsec.

Alternatively or preferably, a bit mapper of the ethernet communication system maps 2048 coded bits to 512 discrete sixteen levels of pulse amplitude modulation symbols or maps 1024 coded bits to 256 discrete sixteen levels of pulse amplitude modulation symbols.

Alternatively or preferably, the data transmission rate of a media independent interface of the Ethernet communication system should be set to 1.0Gbps for the 2.5G BASE-T standard.

Alternatively or preferably, a low density parity check code encoder of the ethernet communication system aggregates 1 auxiliary bit, 10 data blocks of 65 bits each, and an additional 1072 zeros and encodes the 1723 bits into 2048 encoded bits.

Alternatively or preferably, a low density parity check code encoder of the ethernet communication system aggregates 1 auxiliary bit, 20 data blocks of 65 bits each, and an additional 422 zeros and encodes the 1723 bits into 2048 encoded bits.

In addition, according to another aspect of the present invention, an ethernet communication system for transmission over only one twisted pair is provided, the ethernet communication system comprising a first transceiver and exactly one twisted pair. The first transceiver includes a first physical coding sublayer, a first physical media connection coupled to the first physical coding sublayer, and a first hybrid coupled to the first physical media connection. The exactly one twisted pair is connected to the first hybrid of the first transceiver.

Alternatively or preferably, the data transfer rate of a media independent interface of the Ethernet communication system is set to 0.625Gbps for the 2.5G BASE-T standard, 1.25Gbps for the 5G BASE-T standard, and 2.5Gbps for the 10G BASE-T standard.

Alternatively or preferably, a low density parity check code encoder of the ethernet communication system encodes 1723 data bits per 1280nsec or per 2560nsec into 2048 encoded bits.

Drawings

FIG. 1 shows an example of a 2.5G/5G/10G BASE-T Ethernet transceiver system of the prior art.

Fig. 2 shows an ethernet communication system transmitting over two pairs of twisted pairs according to embodiment 4 of the present invention.

Fig. 3A shows an ethernet communication system for transmission over four twisted pairs of comparative example 1.

Fig. 3B shows an ethernet communication system transmitting over two pairs of twisted pairs according to embodiment 1 of the present invention.

Fig. 4A shows an ethernet communication system transmitting over two pairs of twisted pairs according to embodiment 2 of the present invention.

FIG. 4B shows the relationship of the data, LDPC input buffer, and bit mapper of FIG. 4A.

Fig. 5A shows an ethernet communication system transmitting over two pairs of twisted pairs according to embodiment 3 of the present invention.

FIG. 5B shows the relationship of the data, LDPC input buffer, and bit mapper of FIG. 5A.

Fig. 6A shows an ethernet communication system transmitting over a pair of twisted pair lines according to embodiment 5(a) of the present invention.

Fig. 6B shows an ethernet communication system transmitting over a pair of twisted pair lines according to embodiment 5(B) of the present invention.

Reference numerals

1 (transmitted over four twisted pair lines) Ethernet communication system

2 (transmitted over two twisted pair lines) Ethernet communication system

3 (transmitted over a twisted pair) Ethernet communication system

10 first transceiver

101 first transmitter

102 first receiver

11 first Physical Coding Sublayer (PCS)

12 first physical media join (PMA)

13 first hybrid circuit

14 first PMA with PCS

20 second transceiver

201 second transmitter

202 second receiver

21 second PCS

22 second PMA

23 second hybrid circuit

24 second PMA PCS

30 twisted pair

51 LDPC input buffer (LDPC encoder)

52 bit mapper

Detailed Description

In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.

Various embodiments of the invention are provided below. These examples are intended to illustrate the technical contents of the present invention, and are not intended to limit the scope of the claims of the present invention. Features of the invention may be modified, replaced, combined, separated, or designed to be applied to other embodiments.

It is to be noted that, in the present invention, ordinal numbers such as "first" or "second" are used only for distinguishing a plurality of elements (elements) having the same name, and do not indicate the order, execution, arrangement, or process sequence of the elements.

Unless otherwise indicated, each element may be implemented in a suitable manner, either as a separate circuit or integrated as an integrated circuit, and may include one or more active elements, such as transistors or logic gates, or one or more passive elements, such as resistors, capacitors, or inductors, but is not limited thereto. The various elements may be connected to each other in any suitable manner, for example using one or more lines to form a series or parallel connection in conjunction with their respective input and output signals. In addition, each element may allow input and output signals to be input and output sequentially or in parallel. The above design is determined according to the actual application.

In the present invention, terms such as "system", "device", "apparatus", "module", or "unit" refer to an electronic component, a digital circuit composed of a plurality of electronic components, an analog circuit, or other circuits in a broader sense, and they are not necessarily in a hierarchical or subordinate relationship unless otherwise specified.

Furthermore, in the present invention, terms such as "only" (alone), "only" (merly), "just" (just), or "just" (exact) may be used to define a number, an amount, a number, or a value of an element or a parameter for a specific purpose or a specific effect. A number, amount, number, or value above or below the limits may not achieve the particular purpose or effect desired.