阅读说明：本技术 存储器的光刻曝光方法 (Photoetching exposure method of memory ) 是由 王雷 于 2021-06-09 设计创作，主要内容包括：本发明公开了一种存储器的光刻曝光方法,在存储器制作的光刻工艺中,采用掩膜版曝光时,将存储器上的具有不同曝光尺寸要求的区域进行分拆,划分为不同的曝光分组,具有相同曝光解析力要求的区域划为一组,在曝光时对不同分组进行不同模式的能够相应满足该组解析力要求的曝光模式的曝光,在曝光时,采用不同的照明方式进行曝光：首先采用第一种曝光方式对存储阵列单元曝光分组进行曝光,然后保持晶圆在承台上不动,再采用第二种曝光方式对其他结构曝光分组进行曝光；全部曝光完成后,进行一次显影完成图形转移。本发明有针对性地为每组选择更佳的曝光方式,改善了图形转移的质量,并且可以在光刻能力有限的情况下。(The invention discloses a photoetching exposure method of a memory, in the photoetching process for manufacturing the memory, when a mask plate is used for exposure, areas with different exposure size requirements on the memory are divided into different exposure groups, the areas with the same exposure resolving power requirement are divided into one group, different groups are exposed in different modes in the exposure process, the exposure modes which can correspondingly meet the resolving power requirement of the group are carried out, and in the exposure process, different illumination modes are used for exposure: firstly, exposing the storage array unit exposure groups by adopting a first exposure mode, then keeping the wafer on a bearing platform still, and exposing other structure exposure groups by adopting a second exposure mode; after all the exposures are completed, one-time development is performed to complete the pattern transfer. The invention selects a better exposure mode for each group in a targeted manner, improves the quality of pattern transfer and can be used under the condition of limited photoetching capacity.)

1. A photoetching exposure method of a memory is characterized in that: in the photoetching process for manufacturing the memory, when a mask is used for exposure, regions with different exposure size requirements on the memory are divided into different exposure groups;

dividing exposure groups into areas with the same exposure analysis force requirement into the same group according to different exposure analysis force requirements, and dividing the patterns on the mask into a plurality of exposure groups according to different exposure illumination requirements;

and during exposure, respectively carrying out different exposure modes on the exposure groups with different exposure analysis force requirements, wherein the exposure modes can correspondingly meet the exposure group analysis force requirements and have the minimum influence on other exposure groups.

2. A lithographic exposure method for a memory as claimed in claim 1, characterized in that: the memory comprises a memory array unit area and other structure areas, wherein the memory array unit area and other structure parts are divided into different exposure areas so as to be divided into different exposure groups on a mask plate: the exposure grouping of the memory array units comprising the memory and the exposure grouping of other structures formed by the patterns of the structures on the memory except the memory array units; the patterns of the exposure groups of the memory array units have the highest pattern density, and the exposure groups of other structures have lower pattern densities than the exposure groups of the memory array units.

3. A lithographic exposure method for a memory as claimed in claim 2, characterized in that: the other structures of the memory are exposed in groups, including logic device regions and IO regions.

4. A lithographic exposure method for a memory as claimed in claim 2, characterized in that: during exposure, different illumination modes are adopted for exposure: firstly, exposing the storage array unit exposure groups with intensive graphs by adopting a first exposure mode, keeping the position of a wafer on a bearing platform still, and exposing other structure exposure groups with slightly low intensive graphs by adopting a second exposure mode; and after the different sequence exposures respectively carried out on the different exposure groups are completely finished, carrying out one-time development to finish all the pattern transfer.

5. A lithographic exposure method for a memory as claimed in claim 4, characterized in that: the first exposure mode is an exposure mode with higher resolving power for a dense pattern, and the second exposure mode has better resolving power for a relatively sparse pattern area.

6. A lithographic exposure method for a memory as claimed in claim 5, characterized in that: the first exposure mode comprises polarized illumination and off-axis illumination.

7. A lithographic exposure method for a memory as claimed in claim 1, characterized in that: the different groups are exposed in different exposure modes, no overlapping area exists between the exposure patterns, the different exposures are independent and do not influence each other, and extra correction is not needed.

8. A lithographic exposure method for a memory as claimed in claim 4, characterized in that: the illumination modes of two or more exposures are different, and the requirement conflict of patterns among different exposure areas on the photoetching process does not need to be considered.

9. A lithographic exposure method for a memory as claimed in claim 4, characterized in that: during exposure, the sequence of different exposure modes carried out on different exposure groups can be randomly adjusted, and the second exposure mode can be adjusted to be before the first exposure mode; the grouping can be divided into more exposure groups according to the span of the size range of the devices on the chip or different gradients of density degrees, and more exposure modes are correspondingly selected.

10. A lithographic exposure method for a memory as claimed in claim 1, characterized in that: the exposure method is suitable for all chips with different density areas and different exposure resolving power requirements.

Technical Field

The invention relates to the field of semiconductor device manufacturing process, in particular to a photoetching exposure method of a memory.

Background

In the Memory (Memory) manufacturing Process, the Memory cell size reduction is mainly limited by the limit Resolution of the photolithography Process, and in order to realize the limit Resolution, it is usually necessary to use a Resolution Enhancement Technology (RET), which is to determine the optimal illumination condition by simulation calculation according to the existing mask design pattern to realize the maximum Common Process Window (Common Process Window), and this part of the work is generally performed in the early stage of the development of the new photolithography Process. Common resolution enhancement techniques include mainly off-axis illumination (OAI), Optical Proximity Correction (OPC), Phase Shift Mask (PSM), sub-resolution assist maps (SRAF), and the like. Most RET modifies the shape and phase of the mask to some extent to achieve the goal of improving the quality of the pattern transfer.

RET techniques such as polarized illumination, off-axis illumination, etc., are optimized for dense patterns with better resolution, but are worse for patterns of other sizes. The curves shown in fig. 1 reflect the DOF relationship between conventional illumination, polarized illumination, off-axis illumination, and device size. DOF is the depth of focus, or depth of field, which refers to the range of a focal plane that can be imaged clearly after being focused by the lithography machine. Since there are not only Memory cells in a Memory chip, but also many other types of devices such as digital logic control, IO, decoding circuits, etc., as shown in fig. 2, the CD (feature size or critical dimension) requirements and patterns of different functional units, devices are completely different. The Memory array in the Memory belongs to a graph dense area, and the logic area and the IO area belong to a relative graph sparse area. The two partial regions have different requirements on the exposure resolution capability in the photolithography process.

At present, the existing lithography process can not simultaneously realize the device requirements of different functional units (or areas with different pattern densities), and needs to sacrifice part of each unit in order to realize balance, so that the reduction of the memory array unit is greatly influenced by peripheral circuits.

Disclosure of Invention

The invention aims to provide a photoetching exposure method of a memory, which can reduce the size of the memory under the condition of limited photoetching capacity.

In order to solve the above problems, the lithography exposure method of the memory according to the present invention comprises:

in the photoetching process for manufacturing the memory, when a mask is used for exposure, regions with different exposure size requirements on the memory are divided into different exposure groups;

dividing exposure groups into areas with the same exposure analysis force requirement into the same group according to different exposure analysis force requirements, and dividing the patterns on the mask into a plurality of exposure groups according to different exposure illumination requirements;

and during exposure, respectively carrying out different exposure modes on the exposure groups with different exposure analysis force requirements, wherein the exposure modes can correspondingly meet the exposure group analysis force requirements and have the minimum influence on other exposure groups.

In a further improvement, the memory comprises a memory array unit area and other structure areas, and the memory array unit area and other structure parts are divided into different exposure areas so as to be divided into different exposure groups on a mask plate: the exposure grouping of the memory array units comprising the memory and the exposure grouping of other structures formed by the patterns of the structures on the memory except the memory array units; the patterns of the exposure groups of the memory array units have the highest pattern density, and the exposure groups of other structures have lower pattern densities than the exposure groups of the memory array units.

In a further refinement, the other structures of the memory are exposed in groups, including logic device regions and IO regions.

The further improvement is that during exposure, different illumination modes are adopted for exposure: firstly, exposing the storage array unit exposure groups with intensive graphs by adopting a first exposure mode, keeping the position of a wafer on a bearing platform still, and exposing other structure exposure groups with slightly low intensive graphs by adopting a second exposure mode; and after the different sequence exposures respectively carried out on the different exposure groups are completely finished, carrying out one-time development to finish all the pattern transfer.

In a further improvement, the first exposure mode has a higher resolution for dense patterns, and the second exposure mode has a better resolution for relatively sparse pattern regions.

In a further improvement, the first exposure mode comprises polarized illumination and off-axis illumination.

The further improvement is that the different groups are exposed in different exposure modes, no overlapping area exists between the exposure patterns, the different exposures are independent and do not influence each other, and no additional correction is needed.

The further improvement is that the illumination modes of two or more exposures are different, and the requirement conflict of patterns among different exposure areas on the photoetching process is not considered.

The further improvement is that during exposure, the sequence of different exposure modes carried out on different exposure groups can be randomly adjusted, and the second exposure mode can be adjusted to be before the first exposure mode; the grouping can be divided into more exposure groups according to the span of the size range of the devices on the chip or different gradients of density degrees, and more exposure modes are correspondingly selected.

The further improvement is that the exposure method is suitable for all chips which have areas with different density degrees and can form different exposure resolving power requirements. The photoetching exposure method of the memory, disclosed by the invention, respectively exposes the sparse region and the dense region by adopting different exposure modes (illumination modes) according to different exposure requirements of the dense region and the relatively sparse region of the graph, and specifically selects a better exposure mode for each group, thereby improving the quality of graph transfer and realizing the manufacture of a smaller-size memory under the condition of limited photoetching capacity.

Drawings

Fig. 1 is a plot of DOF relationships between conventional illumination, polarized illumination, off-axis illumination, and device dimensions.

FIG. 2 is a schematic diagram of the different regions of the memory.

FIG. 3 is a schematic diagram of a corresponding grouping of relatively sparse regions of a pattern on a photolithographic reticle for exposure.

FIG. 4 is a schematic illustration of a corresponding exposure of a relatively dense region of a pattern, i.e., a memory array region, on a photolithographic reticle in individual groupings.

FIG. 5 is a schematic illustration of a relatively sparse area on a wafer after exposure to light on a memory device.

FIG. 6 is a schematic diagram of a relatively dense area on a wafer for a memory.

Detailed Description

The following detailed description of the present invention is provided with reference to the accompanying drawings, and the technical solutions in the present invention will be clearly and completely described, but the present invention is not limited to the following embodiments. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is noted that the drawings are in greatly simplified form and that non-precision ratios are used for convenience and clarity only to aid in the description of the embodiments of the invention. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and the same reference numerals denote the same elements throughout. It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

The photoetching exposure method of the memory is mainly used for solving the problem that the requirements of pattern exposure resolution power are inconsistent in the manufacturing process of the memory, a pattern dense area needs high resolution power, but an exposure mode with high resolution power is not suitable for the exposure requirement of a pattern sparse area, and for the pattern sparse area, the exposure mode with high resolution power can reduce the effect of pattern exposure on the contrary, namely, the exposure mode with high resolution power is only suitable for the pattern dense area and is not suitable for the pattern sparse area. In order to achieve a balance point, in the conventional exposure process, a compromise exposure mode is selected in the manufacturing process for the memory, and as a result, both of them do not achieve an optimal effect, which has a great limitation. Therefore, the invention provides a solution, in the photolithography process for manufacturing the memory, when the mask is used for exposure, the areas with different exposure size requirements on the memory are split and divided into different exposure groups, the areas with the same exposure resolution requirement are divided into one group, different groups are exposed in different exposure modes correspondingly meeting the group resolution requirement during exposure, and finally, the development is carried out for one time. The different exposure resolution requirements are divided according to the density of the patterns in different areas on the chip, the areas with close density have the same exposure resolution requirements, and the division of the exposure grouping is performed according to the same.

Taking a memory as an example, for the memory, the memory comprises a memory array unit area and other structure areas, and the memory array unit area and other structure areas are divided into different exposure areas to form different exposure groups. For a memory, generally, a memory cell array on the memory belongs to a pattern-dense area, and other structural parts of the memory, including a logic device area, an IO area and the like, generally belong to a sparse area with a slightly lower relative pattern density, so that exposure groups are divided into two groups, and for other types of chips, the exposure groups can be divided into more exposure groups. In fact, for the sparse area with a slightly lower density in the present embodiment, it is also possible to subdivide the sparse area into more exposure groups, which is, of course, related to the range of exposure capabilities of different exposure modes, and it is not necessary to divide the sparse area into two exposure groups directly by the memory cell array area and other areas. As shown in fig. 3 and 4, fig. 3 groups the logic device region and the IO region of the memory, and fig. 4 groups the memory array unit (the diagrams are schematic diagrams for explaining the method of the present invention only, and the layout of the actual chip is greatly different from the diagram shown in the present invention). Thus, different exposure groupings can be produced on the reticle: the memory array unit exposure group comprising the memory, and other structure exposure groups formed by the patterns of the structures on the memory except the memory array unit. The two exposure groups correspond to different exposure resolution requirements respectively, and need to be treated differently in the following exposure.

During exposure, different illumination modes are adopted for exposure: the method comprises the steps of firstly, exposing a storage array unit in groups by adopting a first exposure mode, namely, exposing a pattern dense area by adopting an exposure mode with higher pattern resolution, such as a polarized illumination mode, an off-axis illumination mode and other RET modes, keeping a wafer on a bearing platform to be still after the first exposure is finished, and then, exposing other structures in groups by adopting a second exposure mode. The second exposure mode has better resolution for relatively sparse pattern areas. Of course, there is no hard requirement for the sequence of different exposure modes, and the exposure of the sparse pattern region may be performed first, and then the exposure of the dense pattern region may be performed, as shown in fig. 5 and 6. The precedence order of the exposure groupings has a five effect on the exposure effect. After all the exposures are finished, the pattern transfer can be finished by carrying out one-time development.

The method also has the advantages that the method is different from the traditional exposure method in that different groups are exposed in different exposure modes, different exposure groups or different exposure modes are adopted, and each exposure pattern has no overlapping area, so that different exposures are not influenced mutually, and additional correction is not needed. In addition, the illumination modes of the two exposures are different, and the requirement conflict of patterns among different exposure areas on the photoetching process does not need to be considered. It should be noted that this is completely different from the two exposures in the prior art, in which the locally dense pattern is formed by splitting the pattern into two, the mutual influence needs to be considered between the two exposures, and the exposed pattern needs to be corrected.

The photoetching exposure method of the memory, disclosed by the invention, respectively exposes the sparse region and the dense region by adopting different exposure modes (illumination modes) according to different exposure requirements of the dense region and the relatively sparse region of the graph, and specifically selects a better exposure mode for each group, thereby improving the quality of graph transfer and realizing the manufacture of a smaller-size memory under the condition of limited photoetching capacity.

It should be noted that the exposure method of the present invention is not only suitable for memory chips, but also can be used for dividing the areas or structures with close exposure requirements into the same exposure group for different exposure modes, so as to improve the pertinence and optimize the exposure effect.

The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.