阅读说明：本技术 双向数据链路 (Bidirectional data link ) 是由 A·马尼安 A·莱恩 于 2019-03-11 设计创作，主要内容包括：双向数据链路包括前向信道发射器电路(102)和前向信道接收机电路(104)。前向信道发射器电路(102)包括前向信道驱动器电路(106)和反向信道接收机电路(108)。反向信道接收机电路(108)耦合到前向信道驱动器电路(106)。反向信道接收机电路(108)包括求和电路和有源滤波器电路。求和电路耦合到前向信道驱动器电路(106)。有源滤波器电路耦合到求和电路。前向信道接收机电路(104)包括前向信道接收机(110)和反向信道驱动器电路(112)。反向信道驱器电路(112)耦合到前向信道接收机(110)。(The bidirectional data link includes forward channel transmitter circuitry (102) and forward channel receiver circuitry (104). The forward channel transmitter circuit (102) includes a forward channel driver circuit (106) and a reverse channel receiver circuit (108). A backchannel receiver circuit (108) is coupled to the forward channel driver circuit (106). The back channel receiver circuit (108) includes a summing circuit and an active filter circuit. The summing circuit is coupled to a forward channel driver circuit (106). An active filter circuit is coupled to the summing circuit. The forward channel receiver circuit (104) includes a forward channel receiver (110) and a reverse channel driver circuit (112). A reverse channel driver circuit (112) is coupled to the forward channel receiver (110).)

1. A bidirectional data link, comprising:

forward channel transmitter circuitry, comprising:

a forward channel driver circuit; and

a backchannel receiver circuit coupled to the forward channel driver circuit, the backchannel receiver circuit comprising:

a summing circuit coupled to the forward channel driver circuit; and

an active filter circuit coupled to the summing circuit; and

a forward channel receiver circuit, comprising: a forward channel receiver; and a reverse channel driver circuit coupled to the forward channel receiver.

2. The bidirectional data link of claim 1 wherein the active filter circuit comprises:

a first transistor coupled to the summing circuit;

a second transistor coupled to the first transistor to form a differential amplifier; and

a first capacitor coupled to an output of the differential amplifier.

3. The bidirectional data link of claim 2 wherein the active filter circuit comprises:

a third transistor;

a fourth transistor connected to the third transistor to form a cross-coupled pair; and

a second capacitor coupled to an output of the cross-coupled pair.

4. The bi-directional data link of claim 1 wherein said reverse channel receiver circuitry comprises:

a reference voltage circuit coupled to the active filter circuit;

a driver replica circuit comprising a scaling portion of the forward channel driver circuit coupled to the active filter circuit; and

a capacitor coupling the driver replica circuit to the active filter circuit.

5. The bidirectional data link of claim 1 wherein the back channel driver circuit comprises:

a plurality of driving transistors; and

a plurality of degeneration resistors, each of the degeneration resistors grounding one of the drive transistors.

6. The bidirectional data link of claim 5, wherein the plurality of drive transistors comprises:

a plurality of active-side transistors;

a plurality of dummy side transistors; and

a termination circuit coupled to the virtual side transistor, the termination circuit comprising: a capacitor configured to communicate backchannel data; and a resistor that grounds the capacitor.

7. The bidirectional data link of claim 1 wherein the backchannel driver circuit comprises a differential current mode drive circuit comprising:

a plurality of driving transistors;

a plurality of pull-up resistors, each of the pull-up resistors coupled to one of the drive transistors; and

a voltage regulator circuit coupled to the pull-up resistor.

8. The bidirectional data link of claim 1, wherein:

the summing circuit includes: a first resistor coupled to the first output of the forward channel driver circuit, the forward channel driver circuit coupled to a conductor; and a second resistor coupled to the second output of the forward channel driver circuit; and

the backchannel receiver circuit includes a capacitor coupling the first resistor and the second resistor to the active filter circuit.

9. A transceiver circuit, comprising:

a forward channel driver circuit comprising a differential output; and

a backchannel receiver circuit coupled to the differential output, the backchannel receiver circuit comprising: a summing circuit; and an active filter circuit coupled to the summing circuit.

10. The transceiver circuit of claim 9, wherein the summing circuit comprises:

a first resistor comprising a first terminal coupled to a positive terminal of the differential output; and

a second resistor, comprising: a first terminal coupled to a negative terminal of the differential output; and a second terminal coupled to a second terminal of the first resistor.

11. The transceiver circuit of claim 9, wherein the active filter circuit comprises:

a first transistor coupled to the summing circuit, wherein the first transistor is controlled by an output signal generated by the summing circuit;

a second transistor coupled to a reference voltage source and to the first transistor to form a differential amplifier; and

a first capacitor, comprising: a first terminal coupled to a first output of the differential amplifier; and a second terminal coupled to a second output of the differential amplifier.

12. The transceiver circuit of claim 11, wherein the active filter circuit comprises:

a cross-coupled pair coupled to the differential amplifier, the cross-coupled pair comprising: a first transistor; and a second transistor cross-coupled with the first transistor; and

a second capacitor, comprising: a first terminal coupled to a first output of the cross-coupled pair; and a second terminal coupled to a second output of the cross-coupled pair.

13. The transceiver circuit of claim 11, wherein the reference voltage source is coupled to a terminal of the first transistor.

14. The transceiver circuit of claim 11, further comprising:

a driver replica circuit comprising a scaling portion of the forward channel driver circuit; and

a capacitor coupling the driver replica circuit to the second transistor.

15. A transceiver circuit, comprising:

a forward channel receiver circuit comprising an input terminal; and

a reverse channel driver circuit coupled to the forward channel receiver circuit and comprising:

an output terminal coupled to the input terminal of the forward channel receiver circuit; and

a differential current mode drive circuit coupled to the output terminals and comprising:

a plurality of drive transistors, each of the drive transistors including a first terminal; and

a plurality of degeneration resistors, each of the degeneration resistors comprising:

a first terminal coupled to the first terminal of one of the drive transistors; and

a second terminal connected to ground.

16. The transceiver circuit of claim 15, wherein the plurality of drive transistors comprises:

a plurality of active-side transistors; wherein at least one of the active side transistors is coupled to the output terminal of the back channel driver circuit;

a plurality of dummy side transistors; and

a termination circuit coupled to the virtual side transistor, the termination circuit comprising:

a capacitor comprising a first terminal coupled to a first terminal of each of the dummy side transistors, wherein the capacitor is configured to communicate the backchannel data; and

a resistor, comprising:

a first terminal coupled to a second terminal of the capacitor; and

a second terminal connected to ground.

17. The transceiver circuit of claim 15, wherein the back channel driver circuit comprises:

a plurality of pull-up resistors, each of the pull-up resistors coupled to one of the drive transistors; and

a voltage regulator circuit coupled to the pull-up resistor.

18. A reverse channel communication system, comprising:

a back channel driver circuit, comprising:

a plurality of drive transistors, each of the drive transistors including a first terminal; and

a plurality of degeneration resistors, each of the degeneration resistors comprising:

a first terminal coupled to the first terminal of one of the drive transistors; and

a second terminal connected to ground; and

a reverse channel receiver, comprising:

a summing circuit; and

an active filter circuit coupled to the summing circuit.

19. The reverse channel communication system of claim 18, wherein:

the plurality of driving transistors includes: a plurality of active-side transistors; wherein at least one of the active side transistors is configured to drive the backchannel data onto the conductor; and a plurality of dummy side transistors; and

the back channel driver circuit further comprises:

a termination circuit coupled to the virtual side transistor, the termination circuit comprising:

a capacitor comprising a first terminal coupled to a first terminal of each of the dummy side transistors, wherein the capacitor is configured to communicate the backchannel data; and

a resistor, comprising:

a first terminal coupled to a second terminal of the capacitor; and

a second terminal connected to ground; and

a plurality of pull-up resistors, each of the pull-up resistors coupled to one of the drive transistors; and

a voltage regulator circuit coupled to the pull-up resistor.

20. The reverse channel communication system of claim 18, wherein:

the summing circuit includes:

a first resistor comprising a first terminal coupled to a first input terminal of the backchannel receiver circuit; and

a second resistor, comprising:

a first terminal coupled to a second input terminal of the reverse channel receiver circuit; and

a second terminal coupled to a second terminal of the first resistor;

the active filter circuit includes:

a first transistor coupled to the summing circuit, wherein the first transistor is controlled by an output signal generated by the summing circuit;

a second transistor coupled to a reference voltage source and to the first transistor to form a differential amplifier;

a first capacitor, comprising:

a first terminal coupled to a first output of the differential amplifier; and

a second terminal coupled to a second output of the differential amplifier;

a cross-coupled pair coupled to the differential amplifier, the cross-coupled pair comprising:

a third transistor; and

a fourth transistor cross-coupled with the third transistor; and

a second capacitor, comprising:

a first terminal coupled to a first output of the cross-coupled pair; and

a second terminal coupled to a second output of the cross-coupled pair.

Background

Communication links are common in modern electronic systems. Some communication links are unidirectional (i.e., data flows in only one direction), while others are bidirectional (i.e., data flows in both directions). A bi-directional communication link sharing a communication medium must distinguish data traveling in one direction from data traveling in the opposite direction.

Disclosure of Invention

A data link for simultaneous bidirectional communication via single-ended coaxial cable is disclosed. In one example, a bidirectional data link includes forward channel transmitter circuitry and forward channel receiver circuitry. The forward channel transmitter circuitry includes forward channel driver circuitry and reverse channel receiver circuitry. The backchannel receiver circuitry is coupled to the forward channel driver circuitry. The backchannel receiver circuitry includes a summing circuit and an active filter circuit. The summing circuit is coupled to the forward channel driver circuit. An active filter circuit is coupled to the summing circuit. The forward channel receiver circuitry includes a forward channel receiver and a reverse channel driver circuit. The back channel driver circuit is coupled to the forward channel receiver.

In another example, a transceiver circuit includes a forward channel driver circuit and a reverse channel receiver circuit. The forward channel driver circuit includes a differential output. A back channel receiver circuit is coupled to the differential output. The backchannel receiver circuitry includes a summing circuit and an active filter circuit. An active filter circuit is coupled to the summing circuit.

As yet another example, a transceiver circuit includes a forward channel receiver circuit and a reverse channel driver circuit. The forward channel receiver circuit includes an input terminal. The back channel driver circuit is coupled to the forward channel receiver circuit. The back channel driver circuit includes an output terminal and a differential current mode drive circuit. The output terminal is coupled to an input terminal of the forward channel receiver circuit. A differential current mode drive circuit is coupled to the output terminals. The differential current mode drive circuit includes a plurality of drive transistors and a plurality of degeneration resistors. Each drive transistor includes a first terminal. Each degeneration resistor includes a first terminal coupled to the first terminal of one of the drive transistors, and a second terminal connected to ground.

In yet another example, a reverse channel communication system includes a reverse channel driver circuit and a reverse channel receiver circuit. The back channel driver circuit includes a plurality of driving transistors and a plurality of degeneration resistors. Each drive transistor includes a first terminal. Each degeneration resistor includes a first terminal coupled to the first terminal of one of the drive transistors, and a second terminal connected to ground. The backchannel receiver includes a summing circuit and an active filter circuit. An active filter circuit is coupled to the summing circuit.

Drawings

Fig. 1 shows a block diagram of a bidirectional data link according to the present description.

Fig. 2 shows an example of signals that illustrate the operation of a bi-directional data link in accordance with the present description.

Fig. 3 shows a schematic diagram of a back channel driver suitable for use in a bi-directional data link in accordance with the present description.

Fig. 4 shows a schematic diagram of a reverse channel receiver suitable for use in a bi-directional data link in accordance with the present description.

Fig. 5 shows a schematic diagram of a backchannel receiver suitable for use in a bi-directional data link including a driver replica circuit in accordance with the present description.

Fig. 6 illustrates an example of a voltage-mode driver circuit suitable for use in a forward channel transmitter in accordance with the present description.

Detailed Description

In this specification, the term "coupled" means either an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. Also, in this specification, the recitation "based on" means "based at least in part on". Thus, if X is based on Y, then X may be a function of Y and any of several other factors.

The system employs a variety of methods for bi-directional signaling. Time division multiplexing preserves the communication medium for transmission in only one direction at any given time. For example, 95% of the time may reserve the communication medium for use by the forward channel and 5% of the time may reserve the communication medium for use by the reverse channel. Time division multiplexing may need to be alternated to coordinate switching between the forward and reverse channels without losing data. Frequency division multiplexing simultaneously transmits forward channel data and reverse channel data using different carrier frequencies. However, high bandwidth may be difficult to achieve using frequency division multiplexing. The replica transmitters at each end of the link are actively removed from use to subtract the transmitted data from the received data. While active cancellation allows for simultaneous bi-directional communication with the forward and reverse channels, the replica and cancellation circuitry requires additional power and circuit area and may be difficult to implement in single-ended systems or at high data rates (e.g., >10 gb/s).

The bidirectional link circuit disclosed herein provides simultaneous bidirectional signaling over a single-ended medium (e.g., coaxial cable) without the use of replica circuits. The bidirectional link circuit includes a forward channel transmitter and a forward channel receiver. The forward channel transmitter includes a driver and a backchannel receiver that transmit forward channel data at a relatively high rate (e.g., >3 gigabits/second (Gb/s)). The backchannel data rate may be substantially lower than the forward channel data rate (e.g., approximately 300 megabits/second (Mb/s)). The backchannel receiver extracts backchannel data from the single-ended medium by adding the signal transmitted on the forward channel to the inverse of the signal on the single-ended medium and low-pass filters the sum of the signals to remove the high-frequency noise generated by the forward channel. The forward channel receiver includes a receiver circuit that receives forward channel data and a current mode backchannel driver for transmitting backchannel data. The backchannel driver includes degeneration to reduce noise induced in the forward channel.

Fig. 1 shows a block diagram of a bi-directional data link 100 according to the present description. The bi-directional data link 100 includes forward channel transmitter circuitry 102 and forward channel receiver circuitry 104. Communication between forward channel transmitter circuitry 102 and forward channel transmitter circuitry 102 is single-ended by coaxial cable 114 or other suitable conductor. The forward channel transmitter circuitry 102 includes forward channel driver circuitry 106 and reverse channel receiver circuitry 108. Forward channel driver circuit 106 is a voltage mode driver or current mode driver that receives data to be transmitted and drives the data onto coaxial cable 114. The forward channel driver circuit 106 is a differential driver. The non-inverting output 120 of the forward channel driver circuit 106 is coupled to the coaxial cable 114 and drives the coaxial cable 114, and the inverting output 122 of the forward channel driver circuit 106 is coupled to the termination network 116.

Backchannel receiver circuitry 108 is coupled to forward channel driver circuitry 106 and receives backchannel data transmitted over the coaxial cable 114. More specifically, the reverse channel receiver circuit 108 includes a first input terminal 124 coupled to the reverse output 122 and a second input terminal 126 coupled to the non-reverse output 120. Back channel receiver circuitry 108 adds the signal received on coaxial cable 114 (i.e., the signal present on non-inverting output 120) to the signal present on inverting output 122 to remove forward channel data from the signal received via input terminal 126. The backchannel receiver circuitry 108 filters the summed signal to attenuate noise generated by the forward channel transmission. The backchannel data output by the backchannel receiver circuitry 108 may be provided to backchannel Clock and Data Recovery (CDR) circuitry or other circuitry for processing the backchannel data.

Forward channel receiver circuit 104 includes an input terminal 152 for receiving single-ended (unbalanced) forward channel data, forward channel receiver 110, and reverse channel driver circuit 112. Back channel driver circuit 112 includes a differential current mode drive circuit that receives back channel data for transmission and drives the data onto coaxial cable 114. Back channel driver circuit 112 provides the same signal at output terminal 132 and output terminal 134. Output terminal 132 is coupled to input terminal 152 and coaxial cable 114 to drive backchannel data to forward channel transmitter circuit 102. Output terminal 134 is coupled to reverse input 130 of forward channel receiver 110 and termination network 118.

The forward channel receiver 110 subtracts the backchannel data received on the backchannel input 130 from the signal on the coaxial cable 114 (i.e., the combined forward channel data and backchannel data) received at the non-backchannel input 128 to remove the backchannel data from the signal received via the non-backchannel input 128. The forward channel data output by the forward channel receiver 110 may be provided to forward channel Clock and Data Recovery (CDR) circuitry or other circuitry for processing the forward channel data.

Fig. 2 shows a signal example illustrating the operation of a bi-directional data link according to the present description. For simplicity, the signals of FIG. 2 are illustrated without circuit or cable delays. Forward channel driver circuit 106 drives forward channel data 136 to be transmitted on coaxial cable 114 and backchannel data 138 to be transmitted by backchannel driver circuit 112 onto coaxial cable 114. The backchannel data 138 to be transmitted may be encoded (e.g., manchester encoded) to reduce transmission bandwidth and facilitate clock recovery and data recovery. The encoding reduces the bandwidth of the backchannel data, thereby reducing interaction between the forward channel data and the backchannel data. The signals are summed on the coaxial cable 114 to form a signal 140 at the non-inverting output 120 of the forward channel driver circuit 106 and a signal 144 at the non-inverting input 128 of the forward channel receiver 110. The backchannel receiver circuitry 108 sums the signal 140 and the reverse forward channel data 142 to recreate backchannel data for transmission as an output signal 148 to the backchannel receiver circuitry 108. Forward channel receiver 110 subtracts the reverse channel data signal 146 received at 130 from the signal 144 received at non-reverse input 128 to recreate the forward channel data 136 to be transmitted as an output signal 150 of forward channel receiver 110.

Fig. 3 shows a schematic diagram of a back channel driver circuit 300 suitable for use in the bi-directional data link 100. Back channel driver circuit 300 is one embodiment of back channel driver circuit 112. Back channel driver circuit 300 includes a plurality of drive transistors, such as transistor 302, transistor 304, transistor 306, and transistor 308 shown in fig. 3, forming a differential current mode drive circuit 352. Transistors 302 and 304 are active side transistors that drive a common mode signal onto output terminal 132 and output terminal 134, respectively. Transistor 306 and transistor 308 are virtual side transistors that provide the virtual side of the differential driver formed by transistors 302-308. Transistor 302 includes a terminal 302C (e.g., a collector terminal) coupled to output terminal 132. Transistor 304 includes a terminal 304C (e.g., a collector terminal) coupled to output terminal 134. Transistor 306 includes a terminal 306C (e.g., a collector terminal) coupled to a terminal 308C (e.g., a collector terminal) of transistor 308.

Back channel driver circuit 300 includes a voltage regulator circuit 332, which voltage regulator circuit 332 sets the output common mode voltage of back channel driver circuit 300. For example, voltage regulator circuit 332 may set the output common mode voltage of back channel driver circuit 300 to about 2.1 volts. Voltage regulator circuit 332 includes an amplifier 334, a capacitor 336, a resistor 338, and a resistor 340. Amplifier 334 drives the output common mode voltage onto node 342. Resistor 338 and resistor 340 set the gain of amplifier 334. Capacitor 336 filters the voltage ripple to reduce noise on node 342.

Transistor 302 is coupled to 322 via a pull-up resistor 326. Transistor 304 is coupled to node 342 via pull-up resistor 328. In some implementations of the backchannel driver circuit 300, the pull-up resistor 326 and pull-up resistor 328 each may have a resistance of approximately 75 ohms. Transistor 306 and transistor 308 are coupled to node 342 via pull-up resistor 330. In some embodiments, the resistance of pull-up resistor 330 is approximately half the resistance of pull-up resistor 326.

Termination circuit 321 is coupled to transistor 306 and transistor 308 to reduce AC current imbalance in the differential driver. The termination circuit 321 includes a capacitor 320 and a resistor 322. Capacitor 320 is large enough to carry backchannel data and small enough to be integrated on one die with backchannel driver circuit 300. For example, capacitor 320 may have a capacitance of approximately 100 picofarads (pF) to transmit 156Mb/s (312Mb/s Manchester encoded) reverse channel data for transmission. Capacitor 320 includes a terminal 344 (i.e., terminal 306C and terminal 308C) coupled to transistor 306 and transistor 308, and a terminal 346 coupled to a terminal 348 of resistor 322. Terminal 350 of resistor 322 is connected to ground.

Transistor 302, transistor 304, transistor 306, and transistor 308 are each coupled to a current source 318 and to ground through a degeneration resistor. The degeneration resistor 310 and 316 reduces the noise gain in the backchannel driver circuit 300 while preserving the signal swing at the output terminal 132 to substantially reduce edge jitter in the forward data at the output of the forward channel receiver 110. For example, in the absence of a degeneration resistor, the backchannel driver circuit 300 may induce an edge jitter Root Mean Square (RMS) of approximately 625 femtoseconds at the output of the forward channel receiver 110. With the degeneration resistor, the edge jitter at the output of the forward channel receiver 110 may be about 300 femtoseconds RMS.

Transistor 302 is coupled to current source 318 through degeneration resistor 310. Transistor 304 is coupled to a current source 318 through degeneration resistor 312. Transistor 306 is coupled to a current source 318 through degeneration resistor 314. Transistor 308 is coupled to a current source 318 through degeneration resistor 316. Terminal 310A of degeneration resistor 310 is coupled to terminal 302E (i.e., the emitter terminal) of transistor 302, and terminal 310B of degeneration resistor 310 is coupled to ground via current source 318. Terminal 312A of degeneration resistor 312 is coupled to terminal 304E (i.e., the emitter terminal) of transistor 304, and terminal 312B of degeneration resistor 312 is coupled to ground via current source 318. Terminal 314A of degeneration resistor 314 is coupled to terminal 306E (i.e., the emitter terminal) of transistor 306, and terminal 314B of degeneration resistor 314 is coupled to ground via current source 318. Terminal 316A of degeneration resistor 316 is coupled to terminal 308E (i.e., the emitter terminal) of transistor 308, and terminal 316B of degeneration resistor 316 is connected to ground via current source 318.

Fig. 4 shows a schematic diagram of a backchannel receiver 400 suitable for use in the bi-directional data link 100. Reverse channel receiver 400 is one embodiment of reverse channel receiver circuitry 108. Backchannel receiver 400 includes a summing circuit 402, an active filter circuit 404, and a reference voltage circuit 430. Summing circuit 402 averages the signals received at input terminal 124 and input terminal 126. In the bi-directional data link 100, an input terminal 124 is connected to the inverting output 122 of the forward channel driver circuit 106, and an input terminal 126 is connected to the non-inverting output 120 of the forward channel driver circuit 106 (which is connected to the coaxial cable 114). In the bidirectional data link 100, the sum of the signal at the non-inverting output 120 and the signal at the inverting output 122 substantially removes the forward channel data 136 from the output signal of the summing circuit 402 (leaving the backchannel data 138). The summing circuit 402 includes resistors 406, 408. Resistor 406 includes a terminal 406A coupled to input terminal 126. Resistor 408 includes a terminal 408A coupled to input terminal 124. Terminal 406B of resistor 406 and terminal 408B of resistor 408 are coupled to terminal 410A of capacitor 410. Capacitor 410 couples summing circuit 402 to active filter circuit 404. Reference voltage circuit 430 is coupled to terminal 410B of capacitor 410 and a terminal of transistor 412 (i.e., gate terminal 412G) via a resistor 432. In some embodiments, capacitor 410 may have a value of about 2pf, and resistor 406 and resistor 408 may each have a value of about 5 kohms.

The active filter circuit 404 attenuates frequencies in the signal received from the summing circuit 402 that are outside the bandwidth of the backchannel data. For example, for reverse channel data transmitted at 156Mb/s (312Mb/s Manchester encoded), the active filter circuit 404 attenuates frequencies above the data rate of the Manchester encoded reverse channel data, which includes the forward channel data transmitted by the forward channel driver circuit 106. The active filter circuit 404 includes a transistor 412, a transistor 414, a transistor 418, and a transistor 420. The transistor 412 and the transistor 414 are arranged to form a differential amplifier 442. The transistor 412 is coupled to the summing circuit 402 and is controlled by a signal generated by the summing circuit 402. Transistor 414 is coupled to reference voltage circuit 430. Capacitor 422 is connected across the output of a differential amplifier 442 formed by transistor 412 and transistor 414. Terminal 422A of capacitor 422 is connected to output 438 of differential amplifier 442 and terminal 422B of capacitor 422 is connected to output 440 of differential amplifier 442. In some embodiments, the value of capacitor 422 may be about 65 femtofarads (fF).

Transistor 418 and transistor 420 are cross-coupled to form cross-coupled pair 416. The cross-coupled pair 416 is coupled to the transistor 412 and the transistor 414. Capacitor 424 is coupled to the output terminals of cross-coupled pair 416. Terminal 424A of capacitor 424 is connected to output 416A of cross-coupled pair 416 and terminal 424B of capacitor 424 is connected to output 416B of cross-coupled pair 416. In some embodiments, the value of capacitor 424 may be about 130 fF. Output terminal 434 and output terminal 436 provide the outputs of cross-coupled pair 416 to circuitry external to backchannel receiver 400. In an embodiment of backchannel receiver 400 that includes 130fF capacitor 424, 65fF capacitor 422, and 2pf capacitor 410, the corner frequency of backchannel receiver 400 may be approximately 290 megahertz (MHz), which transmits 312Mb/s manchester-encoded backchannel data.

Fig. 5 shows a schematic diagram of a reverse channel receiver 500 suitable for use in the bi-directional data link 100. Reverse channel receiver 500 is one embodiment of reverse channel receiver circuitry 108. Back channel receiver 500 may provide an improved Power Supply Rejection Ratio (PSRR) relative to some embodiments of back channel receiver circuitry 108 where the transfer function from the power supply to Vref (node 526) is different than the transfer function from the power supply to Vin (node 524). Back channel receiver 500 includes summing circuit 402 and active filter circuit 404, reference voltage circuit 530, and replica driver circuit 502 as described with respect to back channel receiver 400. The reference voltage circuit 530 is coupled to the active filter circuit 404 through resistor 432 and resistor 528.

The replica driver circuit 502 is coupled to the node 526 to improve matching of the transfer function from the power supply to the node 526 and the transfer function from the power supply to the node 524. The replica driver circuit 502 is a scaled replica of a portion of the forward channel driver circuit 106. Fig. 6 shows a schematic diagram of an example of a driver circuit 600 that may be used to implement the forward channel driver circuit 106. To save power, replica driver circuit 502 can scale down (e.g., by 22 x) the replica of one branch of 600. Replica driver circuit 502 includes transistor 504, transistor 506, resistor 508, resistor 510, resistor 514, and current source 512. Transistor 504 is diode-connected, having a terminal 504C (e.g., a collector terminal) connected to a power rail and a terminal 504B (e.g., a base terminal). A terminal 504E (e.g., an emitter terminal) of the transistor 504 is connected to a terminal 506G (e.g., a gate terminal) of the transistor 506 and is coupled to a terminal 506D (e.g., a drain terminal) of the transistor 506 via a resistor 508 and a resistor 510. A terminal 506S (e.g., a source terminal) of the transistor 506 is grounded via a current source 512. Resistor 514 is connected between ground and node 516, and node 516 connects resistor 508 and resistor 510.

Replica driver circuit 502 (i.e., node 516) is coupled to node 526 through resistor 522 and capacitor 520. The value of resistor 522 may be 5 kilo-ohms and the value of capacitor 520 may be 2pf to match the values of resistor 406 and capacitor 410 of summing circuit 402. Relative to some embodiments of backchannel receiver circuitry 108, backchannel receiver 500 may provide a PSRR improvement in excess of 20 dB.

The described embodiments may be modified and other embodiments may be modified within the scope of the claims.