阅读说明：本技术 高速信号链路 (High speed signal link ) 是由 武宁 于 2020-06-30 设计创作，主要内容包括：本申请公开了一种高速信号链路,包括设置多个叠层的印制电路板,印制电路板的信号近端相邻参考层的板层厚度值大于预设厚度阈值；预设厚度阈值不小于服务器芯片的平台设计指导书中的相应参考层的厚度值；每个需要设置信号差分线的叠层均包括满足特征阻抗值要求的第一差分线对和第二差分线对,第一差分线对的中心距大于第二差分线对的中心距,且第一差分线对的中心距与第二差分线对的中心距的差值不小于预设距离阈值。本申请的高速信号链路在满足高频信号长距离传输的现实需求基础上保证好的信号传输质量,同时还可解决现有技术中因更换电性能更好的板材、线缆或增加中途转接器件导致服务器生产制造成本大幅度增加且存在服务器产品性能隐患的弊端。(The application discloses a high-speed signal link, which comprises a printed circuit board provided with a plurality of laminated layers, wherein the thickness value of a board layer of a signal near end adjacent to a reference layer of the printed circuit board is greater than a preset thickness threshold value; presetting a thickness threshold not less than the thickness value of a corresponding reference layer in a platform design guide book of a server chip; each lamination layer needing to be provided with the signal differential line comprises a first differential line pair and a second differential line pair meeting the characteristic impedance value requirement, the center distance of the first differential line pair is larger than that of the second differential line pair, and the difference value between the center distance of the first differential line pair and the center distance of the second differential line pair is not smaller than a preset distance threshold value. The high-speed signal link of this application guarantees good signal transmission quality on the realistic demand basis that satisfies high frequency signal long distance transmission, still can solve simultaneously among the prior art because of changing better panel of electrical property, cable or increasing midway switching device and lead to server production manufacturing cost to increase by a wide margin and have the drawback of server product property hidden danger.)

1. A high speed signal link comprising a printed circuit board, said printed circuit board comprising a plurality of stacked layers;

the thickness value of a board layer of an adjacent reference layer at the signal near end of the printed circuit board is larger than a preset thickness threshold value; the preset thickness threshold value is not smaller than a standard thickness value of a corresponding reference layer in a printed circuit board with the same type as the printed circuit board;

each target lamination comprises a first differential line pair and a second differential line pair meeting the requirement of a characteristic impedance value, the center distance of the first differential line pair is greater than that of the second differential line pair, and the difference value between the center distance of the first differential line pair and the center distance of the second differential line pair is not less than a preset distance threshold value; the target lamination is a lamination provided with a signal difference line.

2. The high-speed signal link according to claim 1, wherein the thickness value of the prepreg layer in the inner stack of the near end of the pcb signal is determined based on a second preset thickness threshold and a preset thickness buffer value, and the second preset thickness threshold is not less than a standard thickness value of the prepreg layer in the pcb of the same type as the pcb.

3. The high-speed signal link of claim 2, wherein the standard thickness of the prepreg layer on the printed circuit board of the same type as the printed circuit board has a value of 5 mils, and the thickness of the prepreg layer on the inner stack near the signal end of the printed circuit board has a value of 6.2 mils.

4. The high-speed signal link of claim 1, wherein a core thickness of the inner stack of the near end of the printed circuit board signal is greater than a first predetermined thickness threshold that is not less than a standard thickness value of a printed circuit board core of the same type as the printed circuit board.

5. The high-speed signal link in accordance with claim 4, wherein said printed circuit board center core has a nominal thickness value of 4 mils for a printed circuit board of the same type as said printed circuit board, and wherein said inner layer stack near said printed circuit board signal end has a core thickness value of 5 mils.

6. The high-speed signal link of any one of claims 1 to 5, wherein the differential impedance line pair is 85ohm, the first differential line pair has a line width of 6.2mil and a spacing of 7.8 mil; the line width of the second differential line pair is 5.2 mils, and the distance is 4.3 mils.

7. The high-speed signal link of any one of claims 1 to 5, wherein the signal trace length of the printed circuit board is 12 inches.

8. The high-speed signal link of claim 7, wherein the board material of the printed circuit board is em528 type low loss board material or s6gx type low loss board material.

Technical Field

The present application relates to the field of signal integrity technology, and more particularly, to a high speed signal link.

Background

As the user demands the performance of the server more and more, the signal transmission rate of the server also becomes higher and higher. With the increase of the high-speed signal rate, in order to support the interconnection communication of long-distance high-speed signals and ensure the signal transmission quality of the high-speed signals on the server motherboard during the long-distance interconnection, the improvement of the server motherboard is needed.

Disclosure of Invention

The application provides a high-speed signal link, guarantees good signal transmission quality on the basis of satisfying high frequency signal long distance transmission demand, has still solved simultaneously among the prior art because of changing better panel of electrical property, cable or increasing midway switching device and lead to server production manufacturing cost to increase by a wide margin and have the drawback of producing property ability hidden danger.

In order to solve the above technical problems, embodiments of the present invention provide the following technical solutions:

the embodiment of the invention provides a high-speed signal link, which comprises a printed circuit board, a signal transmission unit and a signal processing unit, wherein the printed circuit board comprises a plurality of laminated layers;

the thickness value of a board layer of an adjacent reference layer at the signal near end of the printed circuit board is larger than a preset thickness threshold value; the preset thickness threshold value is not smaller than a standard thickness value of a corresponding reference layer in a printed circuit board with the same type as the printed circuit board;

each target lamination comprises a first differential line pair and a second differential line pair meeting the requirement of a characteristic impedance value, the center distance of the first differential line pair is greater than that of the second differential line pair, and the difference value between the center distance of the first differential line pair and the center distance of the second differential line pair is not less than a preset distance threshold value; the target lamination is a lamination provided with a signal difference line.

Optionally, the thickness value of the prepreg layer in the inner laminated structure at the near end of the signal of the printed circuit board is determined based on a second preset thickness threshold and a preset thickness buffer value, and the second preset thickness threshold is not smaller than the standard thickness value of the prepreg layer in the printed circuit board with the same type as the printed circuit board.

Optionally, the standard thickness value of the prepreg layer in the printed circuit board with the same type as the printed circuit board is 5mil, and the thickness value of the prepreg layer of the inner laminated structure at the signal near end of the printed circuit board is 6.2 mil.

Optionally, the thickness of the core board of the inner laminated structure at the signal near end of the printed circuit board is greater than a first preset thickness threshold, and the first preset thickness threshold is not less than the standard thickness value of the core board of the printed circuit board with the same type as the printed circuit board.

Optionally, the standard thickness value of the printed circuit board core board with the same printed circuit board model is 4 mils, and the thickness value of the core board of the inner laminated structure at the near end of the printed circuit board signal is 5 mils.

Optionally, the differential impedance line pair is 85ohm, the line width of the first differential line pair is 6.2mil, and the distance between the first differential line pair and the first differential line pair is 7.8 mil; the line width of the second differential line pair is 5.2 mils, and the distance is 4.3 mils.

Optionally, the signal trace length of the printed circuit board is 12 inch.

Optionally, the board material of the printed circuit board is em528 type low-loss board material or s6gx type low-loss board material.

The technical scheme provided by the application has the advantages that the thickness of the adjacent reference layer at the near end of the high-speed signal is properly increased, the phenomenon that the transmission quality of the signal is reduced due to the fact that the thickness of the adjacent reference layer at the near end of the signal is increased and the influence of difference Pair Pair to Pair crosstalk is increased is avoided, each layer of the differential signal lines which need to be arranged adopts two differential line pairs with wide center distance and narrow center distance which meet the requirement of characteristic impedance value, the characteristics of the differential line pairs with wide center distance and narrow center distance are utilized to carry out mutual compensation, the feasibility of long-distance transmission of high-speed signals can be realized on the premise of controllable production and manufacturing cost, thereby realizing the guarantee of good signal transmission quality on the basis of meeting the practical requirement of long-distance transmission of high-frequency signals, meanwhile, the defects that the production and manufacturing cost of the server is greatly increased and potential hazards of the performance of the server product exist due to the fact that plates and cables with better electrical performance are replaced or midway switching devices are added in the prior art can be overcome.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the related art, the drawings required to be used in the description of the embodiments or the related art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural framework diagram of an embodiment of a high-speed signal link according to an embodiment of the present invention;

fig. 2 is a schematic diagram illustrating the parameters of the stacked layer design of the PCB board of the high-speed signal link according to the embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating PCB layout parameters of a prior art high-speed signal link according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a pcie 5.02con to AIC interconnection topology, a required board type, and a supportable trace length provided in the embodiment of the present invention;

FIG. 5 is a schematic diagram of the type of board and the Loss value used in the high-speed signal interconnection topology of FIG. 3 according to an embodiment of the present invention;

fig. 6 is a schematic diagram of loss and trace length parameters based on the high speed interconnect topology supported in fig. 2 according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terms "first," "second," "third," "fourth," and the like in the description and claims of this application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may include other steps or elements not expressly listed.

Having described the technical solutions of the embodiments of the present invention, various non-limiting embodiments of the present application are described in detail below.

Referring first to fig. 1, fig. 1 is a schematic diagram of an implementation manner of a high-speed signal link according to an embodiment of the present invention, where the embodiment of the present invention may include the following:

a high-speed signal link may include a multi-layer printed circuit board, such as a 6-layer PCB, an 8-layer circuit board, or the like. Each printed circuit board includes a plurality of stacked layers, and for the internal stacked structure of each printed circuit board, as shown in fig. 1, the stacked structure may include, for example, a solder layer, a SIGNAL layer SIGNAL on the TOP layer, a prepreg layer preprg, a ground layer GND on the second layer, a core layer core, a SIGNAL layer on the third layer, a prepreg layer preprg, a ground layer GND on the fourth layer, a core layer, a SIGNAL layer on the fifth layer, a prepreg layer preprg, a ground layer on the sixth layer, and so on. Each lamination is separated by taking a prepreg layer or a core layer as a reference layer, the thickness value of the layer adjacent to the reference layer at the signal near end of each layer of PCB is greater than a preset thickness threshold value, the preset thickness threshold value is not less than the standard thickness value of the corresponding reference layer in the conventional printed circuit board with the same type as the printed circuit board in the current application scene, and the standard thickness value is the thickness information or an industry guidance value of the reference layer of the conventional PCB provided by a manufacturer, a manufacturer or a professional, namely the thickness value of each layer of the PCB with the same type or the same type as the PCB in the prior art. It should be noted that the reference layer types are multiple types, and there are multiple matching between the preset thickness threshold and the reference layer types. For a laminate such as a signal layer provided with differential signal lines, for convenience of explanation and no ambiguity, the present application is referred to as a target laminate, a pair of differential signal pairs in the prior art is changed into a first differential line pair and a second differential line pair meeting the requirement of characteristic impedance value, the center distance of the first differential line pair is greater than the center distance of the second differential line pair, and the difference between the center distance of the first differential line pair and the center distance of the second differential line pair is not less than a preset distance threshold; the preset distance threshold is set so that the center distances of the first differential line pair and the second differential line pair are obviously different, that is, the differential line pair of the present application is a differential line pair with two specifications of a wide center distance and a narrow center distance in relative terms, the width is a boundary of width parameters defined by those skilled in the art, for example, 14mil is the wide center distance, and 9.5 is the narrow center distance.

Due to the fact that the design development cost of the high-frequency signal is controlled under the long-distance transmission feasibility, the server mainboard does not adopt high-performance plates such as ultra-low-loss plates and cables, does not increase midway conversion devices, and the thickness of the adjacent reference layer at the near end of the high-speed signal is properly thickened. Because the thickness of the adjacent reference layer at the near end of the signal is increased, the influence of the Pair-to-Pair crosstalk is inevitably increased, and the transmission quality of the signal is naturally reduced, which is contrary to the requirement of ensuring the signal transmission quality, so that the method is realized by adopting two specifications of the Pair-to-Pair differential line meeting the requirement of the characteristic impedance value. The Narrow center distance NarrowPitch and the Wide center distance differential pair WidePitch characteristics are utilized to carry out mutual compensation, for example, the Narrow center distance NarrowPitch differential pair has the characteristics of smaller width distance and larger signal transmission IL (insertion loss), and the Wide Pitch differential pair has larger width distance and smaller signal transmission IL.

In the technical scheme provided by the embodiment of the invention, the thickness of the adjacent reference layer at the near end of the high-speed signal is properly increased, the phenomenon that the transmission quality of the signal is reduced due to the fact that the thickness of the adjacent reference layer at the near end of the signal is increased and the influence of difference Pair Pair to Pair crosstalk is increased is avoided, each layer of the differential signal lines which need to be arranged adopts two differential line pairs with wide center distance and narrow center distance which meet the requirement of characteristic impedance value, the characteristics of the differential line pairs with wide center distance and narrow center distance are utilized to carry out mutual compensation, the feasibility of long-distance transmission of high-speed signals can be realized on the premise of controllable production and manufacturing cost, thereby realizing the guarantee of good signal transmission quality on the basis of meeting the practical requirement of long-distance transmission of high-frequency signals, meanwhile, the defects that the production and manufacturing cost of the server is greatly increased and potential hazards of the performance of the server product exist due to the fact that plates and cables with better electrical performance are replaced or midway switching devices are added in the prior art can be overcome.

In order to make the technical solutions of the present application more obvious to those skilled in the art, the present application also provides an illustrative example, where the reference layers of the inner laminated structure at the signal end of the printed circuit board are a prepreg layer preprg and a core layer core, and as shown in fig. 2, the following may be included:

the thickness value of the prepreg layer in the inner laminated structure at the near end of the printed circuit board signal is determined based on a second preset thickness threshold value and a preset thickness buffer value, and the second preset thickness threshold value is not smaller than or not smaller than the standard thickness value of the prepreg layer in the printed circuit board with the same type as the printed circuit board. If the standard thickness value of the prepreg layer in the printed circuit board with the same type as the printed circuit board is 5mil, the second preset thickness threshold value can be 5+ smaller positive value mil, and the thickness value of the inner-layer-laminated prepreg layer at the signal near end of the printed circuit board can be set to be 6.2 mil. The preset thickness buffer value is to ensure that the PCB can still ensure good performance after compression, and can be 0.2mil if applicable.

The thickness of the core board of the inner laminated structure at the near end of the printed circuit board signal is larger than a first preset thickness threshold value, and the first preset thickness threshold value is the same as the standard thickness value of the core board in the printed circuit board with the same type of the printed circuit board. If the standard thickness value of the core board in the printed circuit board with the same type as the printed circuit board is 4 mils, the first preset thickness threshold value can be 4+ smaller positive value mils, and the thickness value of the core board of the inner lamination at the signal near end of the printed circuit board can be set to 5 mils.

For a PCB with 85ohm differential impedance line pairs, the line Width Trace Width of the first differential line pair can be set to be 6.2mil, and the Spacing can be set to be 7.8 mil; the line Width Trace Width of the second differential line pair may be set to 5.2 mils and the Spacing may be set to 4.3 mils, i.e., Pitch of the differential line pair of each target overlay is 14.0/9.5. It is understood that the stack design of the high-speed signal link is matched to the impedance, the above parameters are for a PCB of 85ohm, and one skilled in the art can select two differential line pairs of corresponding specifications based on the differential impedance line pair of the current PCB under the condition of satisfying the characteristic impedance value requirement. It should be noted that the parameters of the differential line pair in fig. 2 do not correspond to the same layer as the Thickness parameter thick and the copper foil Thickness parameter Cop, the first layer signal layer in the embodiment of the present invention is not an internal stacked structure, and in order not to increase the manufacturing cost, a differential line segment is still provided, and the first differential line pair and the second differential line pair are simultaneously provided in the subsequent signal layers. Based on the above parameters of the stacked structure, the signal trace length of the printed circuit board of the present application may be set to 12inch, and the board material of the printed circuit board may be any Low Loss board material, for example, em528 type Low Loss board material or s6gx type Low Loss board material.

In addition, in order to verify the effectiveness of the technical solution of the present application and effectively solve the prior art, the present application also performs a comparative analysis on the high-speed signal link based on the parameters shown in fig. 2 and the conventional high-speed signal link, as follows:

for the parameters of the current server motherboard, usually, the CPU chip manufacturer will provide the PDG (platform design Guide) rule to the development engineer for design reference, as shown in fig. 3, the Intel next generation platform uses a 4mil core/5mil preg design stack structure for the application stack information supported by PCIE5.0 (32Gbps) rate, based on the stack information in fig. 3, the line width spacing of the 85ohm differential impedance line is 5/6.2/5mil, that is, the normal pitch is 11.2mil design mode.

For the Intel PDG design guidance document, taking pcie 5.02connector and Riser to AIC topologies as examples, as shown in fig. 4, a high-speed signal link topology and a reference design rule table are shown, and it can be known from data of the table that a reference design index given by a current topology link is if max is supported: under the interconnection length of 10inch strip inner layer wires, an ultra low-loss board must be used, and reference documents suggest that the loss control index of the board cannot exceed 0.96db/inch @16GHz for inner layer signal wires at a frequency point of 16GHz, as shown in fig. 4. Meanwhile, the ultra low loss ull (ultra low loss) board is a type with better electrical performance, so the purchase cost of the board is very expensive and the purchase delivery period is longer.

The method is realized by properly thickening the thickness of the adjacent reference layer at the near end of the high-speed signal and combining two specifications of Wide and Narrow Pitch differential line pairs meeting the requirement of characteristic impedance value. As shown in fig. 2, the inner layer structure is changed from the original 4mil core/5mil preg structure to a 5mil core/6.2mil preg structure, and for the 85ohm differential impedance line pair, the Normal Pitch of 11.2mil (5.2/6/5.2mil differential pair) and the Normal center distance of 9.5mil (5.2/4.3/5.2mil differential pair) are used instead of the Normal Pitch of 11.2mil (5.2/6/5.2mil differential pair) corresponding to the existing layer structure.

Compared with the technical scheme of the present application, when a 5mil core/6mil pre-cured p sheet layer is adopted, under a condition that a Width Pitch is 14mil differential pair, and simultaneously, an ULL sheet material used in the prior art is also adopted, the loss simulation of the ULL sheet material is 0.8dB/inch @16GHz, the supportable trace length can reach 12 inches, and the narrow Pitch is 9.5mil differential pair, the loss simulation of the ULL sheet material is 1.0dB/inch 16GHz, and the supportable trace length is 9.6 inches. Therefore, the differential pair using the wide pitch can reduce the signal transmission loss and expand the signal trace length, while the narrow pitch differential pair can shorten the signal trace length due to the increase of the insertion loss. Meanwhile, considering that the change of the inner layer stacking structure from 4mil core to 5mil core increases the coupling crosstalk effect between the differential line Pair to Pair, when the inner layer adopts 5mil core, the coupling space value between the Wide Pitch (coupling space 23mil) and the Narrow Pitch (coupling space 22mil) differential Pair is slightly larger than the null distance 20mil in the prior art, but it can be known by referring to the data analysis summary table in fig. 5 that the value of Pitch2 (differential line itself + Pitch coupling space) in the Narrow Pitch is smaller than the differential line width distance + Pitch coupling null distance in the prior art, so that the Narrow Pitch differential line can be used to support short-distance signal transmission, and the structural space is reserved for the Wide Pitch to meet the topology of high-speed signal transmission.

In addition, when the ULL board with the same electrical property and better electrical property is adopted, the Loss index is obviously better than the numerical value in the prior art, so that the ULL board can be replaced by a Low Loss board under the condition of supporting the signal transmission 10inch wiring length before improvement, and thus, on the basis of meeting the feasibility of the current interconnection scheme, the Low Loss board is adopted, the product design and development cost can be greatly reduced, and the competitiveness of the product in the market is improved.

Therefore, the embodiment of the invention not only can ensure the signal transmission quality, but also can greatly reduce the development and design cost of the system interconnection of all board cards and components, and can effectively improve and reduce the transmission Loss of the whole signal link, so that the board card design can reduce the originally adopted ULL board to a Low Loss board, thereby reducing the board development cost and improving the product market competitiveness.

The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

A high speed signal link provided by the present application is described in detail above. The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present application.