Circuit for providing reverse current protection for high-side driver
阅读说明:本技术 为高侧驱动器提供反向电流保护的电路 (Circuit for providing reverse current protection for high-side driver ) 是由 S·N·伊斯沃兰 T·P·杜里埃 于 2019-03-05 设计创作,主要内容包括:一种在第一电压轨和第二电压轨(即VDD_HV和VDD_MV)之间操作的电子控制单元(ECU)(400),其包括放大器电路(304’)和单一电流感测电路(402、404、406、408),该单一电流感测电路经耦合以对总线引脚(OUTx)承载信号并保护总线管脚不受对地短路和对电池短路的影响。单一电流感测电路包括:将信号传递到总线引脚的开关电路(402);以及提供与总线引脚处的输出电流成比例的第二电流(IMrev)的正向电流感测电路(404)。当总线管脚(OUTx)上的电压高于给定值时,正向电流感测电路(404)使第二电流基本为零。单一电流感测电路还包括正向电流保护电路(406)和反向电流开关电路(408),反向电流开关电路(408)接收第二电流并在第二电流为零时断开与第二电压的连接。(An Electronic Control Unit (ECU) (400) operating between first and second voltage rails (i.e., VDD _ HV and VDD _ MV) includes an amplifier circuit (304') and a single current sensing circuit (402, 404, 406, 408) coupled to carry a signal to a bus pin (OUTx) and protect the bus pin from shorting to ground and shorting to a battery. The single current sensing circuit includes: a switching circuit (402) that passes signals to the bus pins; and a forward current sense circuit (404) providing a second current (IMrev) proportional to the output current at the bus pin. The forward current sense circuit (404) causes the second current to be substantially zero when the voltage on the bus pin (OUTx) is above a given value. The single current sensing circuit further includes a forward current protection circuit (406) and a reverse current switching circuit (408), the reverse current switching circuit (408) receiving the second current and disconnecting the second voltage when the second current is zero.)
1. An Electronic Control Unit (ECU) for a high-side driver, comprising:
an amplifier circuit comprising a first switching transistor coupled in series with a second switching transistor between a first voltage rail and a second voltage rail, the first voltage rail carrying a first voltage, the second voltage rail carrying a second voltage less than the first voltage, the amplifier circuit coupled to control corresponding gates in the first and second switching transistors; and
a single current sensing circuit coupled to protect bus pins on the high-side driver from both a short to ground and a short to battery, the single current sensing circuit comprising:
an input node between the first switching transistor and the second switching transistor;
a switch circuit coupled to pass current from the input node to the bus pin during normal operation;
a forward current sense circuit coupled to the input node and the first voltage rail, the forward current sense circuit coupled to provide a first current on a first output node and a second current on a second output node, each of the first and second currents proportional to an output current at the bus pin, wherein the first and second currents are substantially zero when a bus voltage on the bus pin is above a given value;
a reverse current switch circuit coupled to receive the second current and further coupled to the gate of the second switch transistor, the reverse current switch circuit coupled to turn off the second switch transistor when the second current output is zero; and
a forward current protection circuit coupled to the forward current sensing circuit, the first voltage rail, and a third voltage rail, the third voltage rail providing a third voltage less than the second voltage, the forward current protection circuit further coupled to open a switching circuit in response to a short to ground.
2. The electronic control unit for a high-side driver of claim 1, wherein the second switching transistor is a P-type metal oxide silicon (PMOS) transistor, the reverse current switching circuit comprising:
a first node coupled to receive the second current;
a first current pourer coupled between the first node and the third voltage rail;
a first N-type metal oxide silicon (NMOS) transistor coupled between a gate of the second switch transistor and the third voltage rail, the gate of the first NMOS transistor coupled to a point between the first node and the first current sink; and
a first resistor coupled between the gate of the second switching transistor and the third voltage rail.
3. The electronic control unit for a high-side driver of claim 2, wherein the switching circuit comprises:
a first current drawer coupled in series with a second resistor between the first voltage rail and the input node, the first current drawer providing a regulated voltage on a second node; and
a second NMOS transistor coupled in series with a third NMOS transistor between the input node and the bus pin, corresponding gates of the second and third NMOS transistors coupled to the second node and further coupled through first and second diodes to common sources of the first and second NMOS transistors.
4. The electronic control unit for a high-side driver of claim 3, wherein the forward current sensing circuit includes:
a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor, each of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor having a source coupled to the first voltage rail and having a corresponding gate coupled in common, a drain of the first PMOS transistor coupled to a gate of the first PMOS transistor, a drain of the second PMOS transistor providing the first current, and a drain of the third PMOS transistor providing the second current;
a fourth NMOS transistor coupled in series with a fifth NMOS transistor and a third diode between the drain of the first PMOS transistor and a third node coupled at the corresponding sources of the second and third NMOS transistors, the fifth NMOS transistor having a gate coupled to the corresponding gates of the second and third NMOS transistors;
a first operational amplifier having a non-inverting input coupled to the input node, an inverting input coupled to a fourth node between the third diode and the fifth NMOS transistor, and an output coupled to a gate of the fourth NMOS transistor.
5. The electronic control unit for a high-side driver of claim 4, wherein the forward current sensing circuit further comprises a second current sink coupled between the fourth node and the third voltage rail.
6. The electronic control unit for a high-side driver of claim 4, wherein the forward current protection circuit comprises:
a third resistor coupled in series with a sixth NMOS transistor, a fourth diode, and a seventh NMOS transistor between the first voltage rail and the third node, a gate of the sixth NMOS transistor coupled to the output of the first operational amplifier, a gate of the seventh NMOS transistor coupled to the gate of the second NMOS transistor;
a fourth resistor coupled in series with a third current pourer between the first voltage rail and the third voltage rail; and
a second operational amplifier having a non-inverting input coupled to a fifth node between the third resistor and the sixth NMOS transistor, an inverting input coupled to a sixth node between the fourth resistor and the third current sink, and an output coupled to the corresponding gates in the second NMOS transistor and the third NMOS transistor through a fifth diode.
7. The electronic control unit for a high-side driver of claim 1, wherein the amplifier circuit comprises an isolation amplifier.
8. The electronic control unit for a high-side driver of claim 2, wherein the amplifier circuit further comprises:
an eighth NMOS transistor coupled in series with a fourth PMOS transistor (M21) and a second current sink between the first voltage rail and the third voltage rail;
a second current drawer coupled in series with a fifth PMOS transistor between the first voltage rail and the third voltage rail; and
a third current drawer coupled in series with a sixth PMOS transistor, a terminal of the third current drawer coupled to the first voltage rail, a drain of the sixth PMOS transistor coupled to the gate of the second switch transistor, the fourth PMOS transistor having a gate coupled to a gate of the sixth PMOS transistor and a drain of the fourth PMOS transistor, the gate of the first switch transistor coupled to a node between the second current drawer and the fifth PMOS transistor.
9. The electronic control unit for a high-side driver of claim 1, wherein the first voltage is approximately 14V, the second voltage is approximately 7V, and the third voltage is local ground.
10. A transceiver chip, comprising:
a plurality of decoders; and
a plurality of transceivers, each of the plurality of transceivers coupled to a corresponding decoder of the plurality of decoders via a corresponding channel, one of the plurality of transceivers including an Electronic Control Unit (ECU) for a high-side driver, the ECU comprising: an amplifier circuit comprising a first switching transistor coupled in series with a second switching transistor between a first voltage rail and a second voltage rail, the amplifier circuit coupled to control corresponding gates in the first switching transistor and the second switching transistor; and a single current sensing circuit coupled to protect bus pins on the ECU from short circuits to ground and battery, the single current sensing circuit comprising:
an input node between the first switching transistor and the second switching transistor;
a switch circuit coupled to pass current from the input node to the bus pin during normal operation;
a forward current sense circuit coupled to the input node and the first voltage rail, the forward current sense circuit coupled to provide a first current on a first output node and a second current on a second output node, each of the first and second currents proportional to an output current at the bus pin, wherein the first and second currents are substantially zero when a bus voltage on the bus pin is above a selected value;
a reverse current switch circuit coupled to receive the second current and further coupled to the gate of the second switch transistor, the reverse current switch circuit coupled to turn off the second switch transistor when the second current is zero; and
a forward current protection circuit coupled to the forward current sensing circuit, the first voltage rail, and a third voltage rail, the forward current protection circuit further coupled to open the switching circuit in response to a short to ground.
11. The transceiver chip of claim 10, wherein the second switching transistor is a P-type metal oxide silicon (PMOS) transistor, the reverse current switching circuit comprising:
a first node coupled to receive the second current;
a first current pourer coupled between the first node and the third voltage rail;
a first N-type metal oxide silicon (NMOS) transistor coupled between a gate of the second switch transistor and the third voltage rail, the gate of the first NMOS transistor coupled to a point between the first node and the first current sink; and
a first resistor coupled between the gate of the second switching transistor and the third voltage rail.
12. The transceiver chip of claim 11, wherein the amplifier circuit further comprises:
an eighth NMOS transistor coupled in series with a fourth PMOS transistor (M21) and a second current sink between the first voltage rail and the third voltage rail;
a second current drawer coupled in series with a fifth PMOS transistor between the first voltage rail and the third voltage rail; and
a third current drawer coupled in series with a sixth PMOS transistor, a terminal of the third current drawer coupled to the first voltage rail, a drain of the sixth PMOS transistor coupled to the gate of the second switch transistor, the fourth PMOS transistor having a gate coupled to a gate of the sixth PMOS transistor and to a drain of the fourth PMOS transistor, and a gate of the first switch transistor coupled to a node between the second current drawer and the fifth PMOS transistor.
13. The transceiver chip of claim 10, wherein the plurality of transceivers are peripheral sensor interface transceivers.
14. A system on a chip (SOC), comprising:
a power module coupled to provide a first voltage rail, a second voltage rail, and a third voltage rail, the first voltage rail providing a first voltage, the second voltage rail providing a second voltage less than the first voltage, and the third voltage rail providing a third voltage less than the second voltage;
a plurality of first transceivers coupled to receive the second voltage rail and the third voltage rail; and
a plurality of second transceivers coupled to receive the first voltage rail, the second voltage rail, and the third voltage rail, each of the plurality of second transceivers coupled to a corresponding decoder of a plurality of decoders via a corresponding channel, one transceiver of the plurality of second transceivers comprising an ECU for a high side drive, the ECU comprising: an amplifier circuit comprising a first switching transistor coupled in series with a second switching transistor between the first voltage rail and the second voltage rail, the amplifier circuit coupled to control corresponding gates in the first switching transistor and the second switching transistor; and a single sensing circuit coupled to protect bus pins on the ECU from short circuits to ground and to a battery, the single sensing circuit comprising:
an input node between the first switching transistor and the second switching transistor;
a switch circuit coupled to pass current from the input node to the bus pin during normal operation;
a forward current sense circuit coupled to the input node and the first voltage rail, the forward current sense circuit coupled to provide a first current and a second current, each of the first current and the second current proportional to an output current at the bus pin, wherein the first current and the second current are substantially zero when a bus voltage on the bus pin is above a selected value;
a reverse current switch circuit coupled to receive the second current and further coupled to the gate of the second switch transistor, the reverse current switch circuit coupled to turn off the second switch transistor when the second current is zero; and
a forward current protection circuit coupled to the forward current sensing circuit, the first voltage rail, and the third voltage rail, the forward current protection circuit further coupled to open the switching circuit in response to a short to ground.
15. The system-on-chip of claim 14, wherein the second switching transistor is a P-type metal oxide silicon (PMOS) transistor, and the reverse current switching circuit comprises:
a first node coupled to receive the second current;
a first current pourer coupled between the first node and the third voltage rail;
a first N-type metal oxide silicon (NMOS) transistor coupled between a gate of the second switch transistor and the third voltage rail, the gate of the first NMOS transistor coupled to a point between the first node and the first current sink; and
a first resistor coupled between the gate of the second switching transistor and the third voltage rail.
16. The system on a chip of claim 15, wherein the amplifier circuit further comprises:
an eighth NMOS transistor coupled in series with a fourth PMOS transistor (M21) and a second current sink between the first voltage rail and the third voltage rail;
a second current drawer coupled in series with a fifth PMOS transistor between the first voltage rail and the third voltage rail; and
a third current drawer coupled in series with a sixth PMOS transistor, a terminal of the third current drawer coupled to the first voltage rail and a drain of the sixth PMOS transistor coupled to a gate of the second switch transistor, the fourth PMOS transistor having a gate coupled to a gate of the sixth PMOS transistor and a drain of the fourth PMOS transistor, and a gate of the first switch transistor coupled to a node between the second current drawer and the fifth PMOS transistor.
17. The system-on-chip of claim 14, wherein the plurality of second transceivers are peripheral sensor interface transceivers.
Technical Field
The present invention relates generally to electronic circuits, and more particularly to circuits that provide reverse current protection for high-side drivers.
Background
The Peripheral Sensor Interface (PSI) is a developing automotive standard, and PSI5 is a current version, considered as a replacement for the Local Interconnect Network (LIN). Many automotive applications use PSI protocols such as airbag acceleration sensors, ultrasound, powertrain, brake applications, and the like. An Electronic Control Unit (ECU) in the PSI transceiver provides power (e.g., base voltage) and synchronization pulses to the sensors, which begin collecting data from the sensors. The sensors are in turn responsive to current modulation data, which is sensed by the ECU and converted to a digital waveform. The transceiver bus pin (OUTx) may be shorted to ground or to the battery and require bidirectional current sensing for fault protection. Protection against ground shorts and against battery shorts typically uses two different circuits, which results in increased chip area and increased power consumption, as will be explained below. A smaller footprint and lower power consumption for the protection circuit are required.
Disclosure of Invention
The described examples provide a single current sensing path for both short to ground and short to battery protection, eliminating the use of two or more current sensing loops to provide both types of protection. This in turn provides efficiency in terms of the area required by the circuit and the power required to operate the circuit.
In one aspect, an Electronic Control Unit (ECU) for a high-side driver includes an amplifier circuit including a first switching transistor coupled in series with a second switching transistor between a first voltage rail (rail) carrying a first voltage and a second voltage rail carrying less than the first voltage, the amplifier circuit coupled to control corresponding gates in the first and second switching transistors; and a single current sensing circuit coupled to protect bus pins on the high-side driver from shorting to ground and shorting to the battery. The single current sensing circuit includes: an input node between the first switching transistor and the second switching transistor; a switching circuit coupled to pass current from an input node to a bus pin during normal operation; a forward current sensing circuit coupled to the input node and to the first voltage rail, the forward current sensing circuit coupled to provide a first current on the first output node and a second current on the second output node, each of the first current and the second current proportional to an output current at the bus pin, wherein the first current and the second current are substantially zero when the bus voltage on the bus pin is above a given value; a reverse current switching circuit coupled to receive the second current and further coupled to a gate of the second switching transistor, the reverse current switching circuit coupled to turn off the second switching transistor when the second current output is zero; and a forward current protection circuit coupled to the forward current sensing circuit, the first voltage rail, and a third voltage rail that provides a third voltage (which is less than the second voltage), the forward current protection circuit further coupled to open the switching circuit in response to a short to ground.
In another aspect, a transceiver chip includes a plurality of decoders; and a plurality of transceivers, each of the plurality of transceivers coupled to a corresponding decoder of the plurality of decoders via a corresponding channel, one of the plurality of transceivers including an Electronic Control Unit (ECU) for the high-side driver. The ECU includes: an amplifier circuit and a single current sensing circuit. The amplifier circuit includes a first switching transistor coupled in series with a second switching transistor between a first voltage rail and a second voltage rail, the amplifier circuit coupled to control corresponding gates of the first switching transistor and the second switching transistor; the single current sensing circuit is coupled to protect bus pins on the ECU from short circuits to ground and to the battery. The single current sensing circuit includes: an input node between the first switching transistor and the second switching transistor; a switching circuit coupled to pass current from an input node to a bus pin during normal operation; a forward current sensing circuit coupled to the input node and to the first voltage rail, the forward current sensing circuit coupled to provide a first current on the first output node and a second current on the second output node, each of the first current and the second current proportional to an output current at the bus pin, wherein the first current and the second current are substantially zero when the bus voltage on the bus pin is above a selected value; a reverse current switching circuit coupled to receive the second current and further coupled to a gate of the second switching transistor, the reverse current switching circuit coupled to turn off the second switching transistor when the second current is zero; and a forward current protection circuit coupled to the forward current sensing circuit, the first voltage rail, and the third voltage rail, the forward current protection circuit further coupled to open the switching circuit in response to a short to ground.
In yet another aspect, a system on a chip (SOC) includes a power module, a plurality of first transceivers, and a plurality of second transceivers. The power module is coupled to provide a first voltage rail, a second voltage rail, and a third voltage rail, the first voltage rail providing a first voltage, the second voltage rail providing a second voltage less than the first voltage, and the third voltage rail providing a third voltage less than the second voltage; a plurality of first transceivers coupled to receive the second voltage rail and the third voltage rail; the plurality of second transceivers are coupled to receive the first voltage rail, the second voltage rail, and the third voltage rail, each of the plurality of second transceivers is coupled to a corresponding decoder of the plurality of decoders via a corresponding channel, one transceiver of the plurality of second transceivers includes an ECU for a high-side driver. The ECU includes: an amplifier circuit and a single sensing circuit. The amplifier circuit includes a first switching transistor coupled in series with a second switching transistor between the first voltage rail and the second voltage rail, the amplifier circuit coupled to control corresponding gates of the first switching transistor and the second switching transistor; a single sensing circuit is coupled to protect bus pins on the ECU from short circuits to ground and to the battery. The single sensing circuit includes: an input node between the first switching transistor and the second switching transistor; a switching circuit coupled to pass current from an input node to a bus pin during normal operation; a forward current sense circuit coupled to the input node and the first voltage rail, the forward current sense circuit coupled to provide a first current and a second current, each of the first current and the second current proportional to an output current at the bus pin, wherein the first current and the second current are substantially zero when the bus voltage on the bus pin is above a selected value; a reverse current switching circuit coupled to receive the second current and further coupled to a gate of the second switching transistor, the reverse current switching circuit coupled to turn off the second switching transistor when the second current is zero; and a forward current protection circuit coupled to the forward current sensing circuit, the first voltage rail, and the third voltage rail, the forward current protection circuit further coupled to open the switching circuit in response to a short to ground.
Drawings
FIG. 1 depicts a high level schematic of an ECU that may use a high side driver of a sensing circuit in accordance with one embodiment of the present description.
Fig. 2 depicts a somewhat more detailed schematic of an ECU for a conventional high-side drive.
Fig. 3A and 3B together depict an embodiment of an ECU for a conventional high-side drive.
Fig. 4 depicts an implementation of a portion of an ECU for a high-side drive according to one embodiment of the present description.
Figure 5 depicts a high-level schematic diagram of a system including a standalone PSI5 transceiver chip that may use the described protection circuitry in accordance with one embodiment of the present specification.
FIG. 6 depicts a high-level schematic diagram of a system including a SOC that may use the described protection circuit, according to one embodiment of the present description.
Detailed Description
In the drawings, like numbering represents like elements. Different references to "an" or "an" embodiment in this specification are not necessarily to the same embodiment, and such references may mean at least one. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, such feature, structure, or characteristic may be used with other embodiments whether or not explicitly described. As used herein, the term "coupled" means either an indirect or direct electrical connection, unless otherwise defined as "communicatively coupled" (which may include a wireless connection). Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
Fig. 1 depicts a high-level schematic diagram of an
The low
The
Fig. 3A and 3B collectively depict an ECU 300 that may be used as a high-side driver circuit for the ECU 202. ECU 300 includes low voltage logic circuit 302, amplifier circuit 304 (which is again an isolation amplifier), forward
The signal generated by low voltage logic circuit 302 is provided to amplifier circuit 304. in the illustrated embodiment, amplifier circuit 304 is an isolated amplifier circuit that receives high voltage rail VDD _ HV, medium voltage rail VDD _ MV, and low voltage rail VDD _ LV. Voltage rails VDD _ HV, VDD _ MV, and VDD _ LV may be referred to as a first voltage rail, a second voltage rail, and a third voltage rail, respectively. In one embodiment, high voltage rail VDD _ HV carries a first voltage of about 14V, medium voltage rail VDD _ MV carries a second voltage of about 7V, and low voltage rail VDD _ LV carries a third voltage that is locally grounded, also referred to as a low voltage rail. In the embodiment shown in fig. 3A-3B, it is desirable to have the pulses generated by the amplifier circuit 304 have a very controlled shape to avoid Radio Frequency (RF) interference. Because of this need, the received signal is received on a non-inverting input of pulse shaping amplifier 318, pulse shaping amplifier 318 being coupled to each of high voltage rail VDD _ HV, medium voltage rail VDD _ MV, and low voltage rail VDD _ LV. The diode DHV provides protection against current flow upstream from the circuit shown.
Pulse-shaping amplifier 318 provides an inverting output coupled to the gate of a P-type metal-oxide-silicon (PMOS) transistor M4 and a non-inverting output coupled to the gate of NMOS transistor M3. PMOS transistor M4 has a source coupled to high voltage rail VDD _ HV, and NMOS transistor M3 has a source coupled to low voltage rail VDD _ LV. PMOS transistor M5 and NMOS transistor M6 are coupled in parallel between the drain of PMOS transistor M4 and the drain of NMOS transistor M3, the gate of PMOS transistor M5 is coupled to high voltage rail VDD _ HV through current puller Vbp, and the gate of NMOS transistor M6 is coupled to low voltage rail through current sink Vbn. PMOS transistor M2 is coupled in series with NMOS transistor M1 between VDD _ HV and VDD _ LV. The gate of PMOS transistor M2 is coupled to the drain of PMOS transistor M4, and the gate of NMOS transistor M1 is coupled to the drain of NMOS transistor M3. A node 320 between the drain of PMOS transistor M2 and the drain of NMOS transistor M1 is coupled to drive the gate of NMOS transistor Mb and the gate of PMOS transistor Mc, and is also coupled to the inverting input of pulse-shaping amplifier 318 through a voltage divider comprising resistor R7 and resistor R8 to provide a feedback loop. NMOS transistor Mb has a source coupled to VDD _ LV and a drain coupled to VDD _ HV through current sink 322; the PMOS transistor Mc has a source coupled to VDD _ HV through a current puller 324 and a drain coupled to VDD _ LV. Finally, NMOS switch transistor Msr and PMOS switch transistor Msn are coupled in series between high voltage rail VDD _ HV and medium voltage rail VDD _ MV. The gate of NMOS switch transistor Msr is coupled to node 326 between current puller 324 and PMOS transistor Mc, and the gate of PMOS switch transistor Msn is coupled to node 328 between NMOS transistor Mb and current filler 322. Node 330, located between the source of NMOS switch transistor Msr and the source of PMOS switch transistor Msn, provides signals to forward
Within forward
Also within the forward
Within the portion of the forward
The reverse
While the
Fig. 4 depicts a portion of the ECU 400 of the high-side driver circuit that eliminates the use of the second sensing circuit to regulate the short to the battery and uses a single current sensing circuit to protect the bus pin OUTx from both a short to ground and a short to the battery, i.e.: ensuring that too high or too low a bus voltage on bus pin OUTx does not cause damage to the chip. To highlight the changes made to
The single current sensing circuit comprises four sections, each enclosed by a dashed line: 1) a switch circuit 402 including a first current drawer Isg, a second resistor R2, a first diode D1 and a second diode D2, a second NMOS transistor M7F and a third NMOS transistor M7R, the second and third NMOS transistors M7F and M7R having one common source; 2) a forward current sensing circuit 404 including a first operational amplifier OA2, a third diode D3, a fourth NMOS transistor M16, a fifth NMOS transistor M9, and a first PMOS transistor M8, a second PMOS transistor M10, and a third PMOS transistor Mrev; 3) a forward current protection circuit 406 including a second operational amplifier Opf, a third resistor R3 and a fourth resistor R4, a fourth diode D4 and a fifth diode D5, a third current sink If _ ref, a sixth NMOS transistor M12 and a seventh NMOS transistor M11, and 4) a reverse current switch circuit 408 including a first current sink Csi1, a first NMOS transistor Mswitch and a first resistor R1, and the reverse current switch circuit 408 coupled to a gate of a PMOS switch transistor Msn. In the embodiment shown, the switching circuit 402, the forward current sensing circuit 404, and the forward current protection circuit 406 comprise the same devices as their counterparts in fig. 3A and 3B; and operates in the same manner except that a third diode D3 is added in the forward current sensing circuit 404 between the fourth NMOS transistor M16 and the fifth NMOS transistor M9 and a fourth diode D4 is added in the forward current protection circuit 406 between the sixth NMOS transistor M12 and the seventh NMOS transistor M11. The forward current sense circuit 404 is also modified to include an additional PMOS transistor Mrev having a gate coupled to the gate of the PMOS transistor M8 and the gate of the PMOS transistor M10. The PMOS transistor Mrev has a source coupled to VDD _ HV and a drain coupled to provide a current IMrev to the reverse current switch circuit 408 via node N8.
During normal operation of ECU 400, amplifier circuit 304' provides voltage VDD _ MV by turning on PMOS transistor Msn to provide a base voltage at node 330. When the pulse signal is provided by the amplifier circuit 304', the PMOS switch transistor Msn is turned off and the NMOS switch transistor Msr is turned on to provide the voltage VDD _ HV. Both the amplifier circuit 304 shown in fig. 3A and the modification shown as amplifier circuit 304' in fig. 4 provide pulses shaped to meet the specific requirements of automotive circuitry, e.g., to provide reduced noise. However, it should be understood that other amplifier circuits may be used with the single sensing circuit described herein. The single sensing circuit described is shown for use with an isolated amplifier circuit, but the single sensing circuit described may also be used with amplifier circuits that are not floating.
The output signal, i.e., the base voltage and/or the synchronization pulse, is transferred from node 330 (also referred to as the input node) to bus pin OUTx through switching circuit 402. The gates of the second and third NMOS transistors M7F and M7R are coupled to a regulated voltage provided at the second node N2, and the second node N2 keeps the second and third NMOS transistors M7F and M7R fully conductive unless the voltages on the gates of these transistors are below the threshold of these transistors, as will be discussed below. The output signal is also provided to the non-inverting input of the operational amplifier OA2, while the output of the operational amplifier OA2 is provided to the gate of the fourth NMOS transistor M16. The inverting input of the operational amplifier OA2 is supplied with a feedback value using the PMOS transistor M8 and the fourth and fifth NMOS transistors M16 and M9, the feedback value being taken from the fourth node N4 between the fourth and fifth NMOS transistors M16 and M9. The size of the fifth and seventh NMOS transistors M9 and M11 is proportional to the size of the second NMOS transistor M7F, for example, if the size of the second NMOS transistor M7F is 1000x1, the value of the fifth and seventh NMOS transistors M9 and M11 may be 10x1, and then one hundredth of the current of the second NMOS transistor M7F will be pulled (source). During normal operation of the ECU 400, the fourth NMOS transistor M16 and the sixth NMOS transistor M12 of the forward current sensing circuit 404 detect current, including changes caused by data emitted by the sensor, through the bus pin OUTx, and the forward current sensing circuit 404 provides a proportional current on both the first output node N7 and the second output node N8, the first output node N7 providing a proportional current Ircv (also referred to as a first current) to a processing circuit having a comparator to sense data sent from the sensor, and the second output node N8 providing a proportional current IMrev (also referred to as a second current) to the reverse current switching circuit 408. During a short to ground condition on bus pin OUTX, operational amplifier Opf regulates the current by limiting the voltage on the gate of second NMOS transistor M7F, while NMOS transistor Mswitch remains on.
The reverse current switch circuit 408 receives the proportional current IMrev at a first node N9, the first node N9 being coupled to VDD _ LV through a first current sink Csi1 such that the provided current is sunk at a constant rate. The first NMOS transistor Mswitch is coupled between the gate of the PMOS switch transistor Msn and VDD _ LV; resistor R1 is coupled in parallel with the first NMOS transistor Mswitch between the gate of PMOS switch transistor Msn and VDD _ LV. The gate of the first NMOS transistor Mswitch is coupled to a point between the first node N9 and the first current dump Csi 1. During normal operation of the ECU 400, the current IMrev provided at the first node N9 is greater than the current sunk by the first current sink Csi1, and the gate of the first NMOS transistor Mswitch remains conductive. With the first NMOS transistor Mswitch on, the gate of PMOS switch transistor Msn is coupled to VDD _ LV, which acts to keep PMOS switch transistor Msn on. However, when the short circuit to the battery occurs, the second current IMrev at the first node N9 becomes zero. This means that the voltage over the first NMOS transistor Mswitch will drop as the first current dumpster Csi1 dumps a current, allowing the first NMOS transistor Mswitch to turn off. This in turn allows the gate of PMOS switch transistor Msn to rise, turning off PMOS switch transistor Msn. It is to be noted that, in the
Fig. 5 depicts a high-level schematic diagram of a
FIG. 6 depicts a high-level schematic diagram of a system 600 including an SOC602, which SOC602 may use the described protection circuits, according to one embodiment of the present description. SOC602 is coupled to vehicle battery 601 and when the ignition switch is turned on/off, power module 604 provides high voltage rail VDD _ HV, medium voltage rail VDD _ MV, and low voltage rail VDD _ LV to the power supply lines. A plurality of transceiver systems may be provided on SOC602 and in the example shown, these include LIN transceiver 606 (which receives VDD _ MV and VDD _ LV), Flex Ray (FR) transceiver 608 (which also receives VDD _ MV and VDD _ LV), Controller Area Network (CAN) transceiver 610 and PSI5 transceiver 612, all of which receive all three VDD _ HV, VDD _ MV and VDD _ LV. As in a separate chip, the PSI5 transceiver 612 includes four transceivers (not shown separately), each coupled to a corresponding channel and decoder. The output of the decoder is provided to a data software process 622.
As described herein, an innovative circuit can protect bus pins of a high-side driver from ground and battery shorts. The described circuit uses less area on a chip and consumes less power because the circuit does not require a separate sensing circuit. The described protection circuit may be used with the high side driver of the PSI5 transceiver or other high side drivers. In addition, a stand-alone chip and SOC comprising the described circuit are also presented. With the described protection circuit, shorting the battery is operable to pass less than 10 milliamps of current.
In this specification, unless explicitly stated otherwise, the singular form of an element does not mean "one and only one" but "one or more"
The described embodiments may be modified and other embodiments may be modified within the scope of the claims.
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