阅读说明：本技术 用于量子电路模拟器的设备和方法 (Apparatus and method for quantum circuit simulator ) 是由 安德烈·埃米尔维奇·卡伦达罗夫 德米特里·谢尔盖维奇·科尔马科夫 尤里·亚历山德罗维奇·佐托夫 于 2019-03-29 设计创作，主要内容包括：本发明提出了一种用于量子电路模拟器的设备和包括至少一个这种设备的量子电路模拟器。所述设备用于：获取第一量子门序列；生成第二量子门序列,作为所述第一量子门序列的子序列；根据所述第二量子门序列计算局部量子比特集和全局量子比特集；生成量子门集群集,其中,每个集群包括使用贪婪算法合并在一起的所述第二量子门序列中的所述量子门的子集；根据所述集群的顺序生成第三量子门序列,所述第三量子门序列包含所述第二量子门序列中的所有量子门；将所述局部量子比特集和所述全局量子比特集提供给所述量子电路模拟器；将所述第三量子门序列输出到所述量子电路模拟器。(The invention proposes a device for a quantum circuit simulator and a quantum circuit simulator comprising at least one such device. The apparatus is for: obtaining a first quantum gate sequence; generating a second quantum gate sequence as a subsequence of the first quantum gate sequence; computing a local qubit set and a global qubit set from the second quantum gate sequence; generating clusters of quantum gates, wherein each cluster comprises a subset of the quantum gates in the second sequence of quantum gates merged together using a greedy algorithm; generating a third sequence of quantum gates according to the order of the clusters, the third sequence of quantum gates including all quantum gates in the second sequence of quantum gates; providing the local qubit set and the global qubit set to the quantum circuit simulator; outputting the third sequence of quantum gates to the quantum circuit simulator.)

1. An apparatus (100) for a quantum circuit simulator (110), the apparatus (100) being configured to:

obtaining a first quantum gate sequence (101);

generating a second sequence of quantum gates (102) by using a greedy algorithm, in particular a greedy algorithm with backtracking, the second sequence of quantum gates (102) being a subsequence of the first sequence of quantum gates (101);

computing a set of local qubits (103a) and a set of global qubits (103b) from the second sequence of quantum gates (102);

generating a set of clusters (104) of quantum gates, wherein each cluster (104) comprises a subset of the quantum gates of the second sequence of quantum gates (102) merged together by using a greedy algorithm;

generating a third sequence of quantum gates (105) according to the order of the clusters (104), the third sequence of quantum gates (105) comprising all quantum gates in the second sequence of quantum gates (102);

providing the set of local qubits (103a) and the set of global qubits (103b) to the quantum circuit simulator (110);

outputting the third sequence of quantum gates (105) to the quantum circuit simulator.

2. The apparatus (100) of claim 1, further configured, when generating the set of quantum gate clusters (104), to:

the cluster (104) comprising a greater number of sub-gates is ranked before the cluster (104) comprising a lesser number of sub-gates in the order of the clusters (104).

3. The apparatus (100) of claim 1 or 2, further configured to, when generating the set of quantum gate clusters (104):

the clusters (104) are generated according to the maximum possible number of quantum bits in the clusters (104).

4. The apparatus (100) of claim 3, further configured, when generating the set of quantum gate clusters (104), to:

selecting one by one all possible combinations of qubits associated with the second sequence of quantum gates (102) according to a maximum possible number of qubits in the cluster (104);

building a cluster (104) for each combination;

a cluster is selected in which the number of quantum gates is the greatest (104).

5. The apparatus (100) of claim 4, further configured, when generating the set of quantum gate clusters (104), to:

maintaining a set of locked qubits;

including quantum gates into a cluster (104) if a matrix representation of the quantum gates is diagonal;

skipping a quantum gate if at least one of the qubits acted upon by the quantum gate does not belong to the selected combination of qubits; and/or

Skipping a quantum gate if at least one of the qubits acted upon by the quantum gate is in the set of locked qubits;

if a quantum gate is skipped, adding all qubits acted upon by the quantum gate to the set of locked qubits;

otherwise, the quantum gates are included into the cluster (104).

6. The apparatus (100) of any of claims 1 to 5, further configured to, when generating the set of quantum gate clusters (104):

determining a cluster (104) comprising a maximum number of quantum gates;

outputting the quantum gates of the determined cluster (104), in particular inserting the outputted quantum gates into the third sequence of quantum gates (105);

deleting the output quantum gate from the second sequence of quantum gates (102).

7. The apparatus (100) of any of claims 1 to 6, further configured to, when computing the set of local qubits (103a) and the set of global qubits (103 b):

determining the set of local qubits (103a) and/or the set of global qubits (103b) according to a maximum number of local qubits and/or a maximum number of global qubits, respectively.

8. The apparatus (100) of any of claims 1 to 7, further configured to, when generating the second sequence of quantum gates (102):

merging quantum gates acting on a single qubit with adjacent quantum gates in the first sequence of quantum gates (101) acting on a subset of qubits comprising the same single qubit.

9. The apparatus (100) of any of claims 1 to 8, further configured to, when generating the second sequence of quantum gates (102):

including into the second sequence of quantum gates (102) quantum gates acting on a maximum of the maximum number of local qubits;

if the first sequence of quantum gates (101) comprises at least one quantum gate acting on a single qubit and another quantum gate acting on the same qubit and at least one other qubit, then the single qubit gate and the another multi-qubit gate are included together in the second sequence of quantum gates (102).

10. The apparatus (100) of any of claims 1 to 9, further configured to, when generating the second sequence of quantum gates (102):

creating a branch of the greedy algorithm, wherein quantum gates are included into the second sequence of quantum gates (102); and/or

Creating a branch of the greedy algorithm, wherein quantum gates in the first sequence of quantum gates (101) are skipped;

adding all qubits of said quantum gate effect to said set of local qubits (103a) if a quantum gate is included; alternatively, the first and second electrodes may be,

if a quantum gate is skipped, all qubits acted upon by the quantum gate are added to the set of locked qubits.

11. The apparatus (100) of claim 10, further configured, when generating the second sequence of quantum gates (102):

at most, a maximum number of branches of the greedy algorithm is created.

12. The apparatus (100) of claim 10 or 11, further configured to, when applying the branch of the greedy algorithm:

constructing the second sequence of quantum gates (102) with as many gates as possible,

each gate in the first sequence of quantum gates (101) is tested and, depending on the test result, either the gate is skipped or the gate is included in the second sequence of quantum gates (102).

13. The apparatus (100) of any of claims 10 to 12, further configured to, when generating the second sequence of quantum gates (102):

maintaining a set of locked qubits;

skipping a quantum gate if the application quantum gate requires more than a predetermined threshold of qubits to be local qubits; and/or

Skipping said qubit gate if at least one of said qubits acted upon by the qubit gate is in the locked qubit set,

if a quantum gate is skipped, all qubits acted upon by the quantum gate are added to the set of locked qubits.

14. The apparatus (100) of any of claims 1 to 13, further configured to, when generating the second sequence of quantum gates (102):

if the matrix representation of quantum gates is diagonal, including the quantum gates into the second sequence of quantum gates (102), without adding quantum bits of quantum gate effect to the set of local quantum bits (103 a); and/or

Including the quantum gate into the second sequence of quantum gates (102) if all qubits of a quantum gate role are already in the set of local qubits (103 a).

15. The apparatus (100) of any of claims 1 to 14, further configured to, when computing the set of local qubits (103a) and the set of global qubits (103 b):

constructing a set of all qubits of a quantum gate effect in the first quantum gate sequence (101);

including all qubits of a quantum gate role in the second quantum gate sequence (102) into the set of local qubits (103 a);

including all qubits in the set of all qubits and not in the local set of qubits (103a) into the global set of qubits (103 b).

16. A quantum circuit simulator (110), comprising a device (100) according to any of claims 1 to 15.

17. A method (700) for quantum gate and qubit scheduling for a quantum circuit simulator (110), the method comprising:

obtaining (701) a first sequence of quantum gates (101),

generating (702) a second sequence of quantum gates (102) by using a greedy algorithm, in particular a greedy algorithm with backtracking, the second sequence of quantum gates (102) being a subsequence of the first sequence of quantum gates (101);

computing (703) a set of local qubits (103a) and a set of global qubits (103b) from the second sequence of quantum gates (102);

generating (704) a set of clusters (104) of quantum gates, wherein each cluster (104) comprises a subset of the quantum gates of the second sequence of quantum gates (102) merged together by using a greedy algorithm;

generating (705) a third sequence of quantum gates (105) according to the order of the clusters (104), the third sequence of quantum gates (105) comprising all quantum gates in the second sequence of quantum gates (102);

providing (706) the set of local qubits (103a) and the set of global qubits (103b) to the quantum circuit simulator (110);

outputting (707) the third sequence of quantum gates (105) to the quantum circuit simulator (110).

18. A computer program product, characterized in that it comprises program code for controlling a device (100) according to any one of claims 1 to 15 or for performing a method (700) according to claim 17 when implemented on a processor.

Technical Field

The present invention relates to the field of quantum computing, and more particularly to the simulation of quantum circuits on classical computers. In particular, the invention relates to a device for a quantum circuit simulator, and a quantum circuit simulator comprising at least one such device. Furthermore, the invention relates to a method for quantum gate and qubit scheduling for a quantum circuit simulator, wherein the method can be performed by the apparatus.

Background

A generic quantum circuit simulator stores a mathematical representation of the entire state of a simulated quantum computer in memory. The size scale of this state is 2ⁿAnd n is the number of analog qubits of the quantum computer. For 40 qubits, the size of this state is 16 TiB. This requires the use of a multi-node computing system in order to distribute the large state across multiple memories of the node. During analog quantum circuits, a portion of the state needs to be accessed from a remote node.

To simulate quantum computation on a classical computer, one can use a linear algebraic representation of quantum computation (quantum circuit). In this representation, the state of an n qubit quantum circuit is to have orthogonal bases in Hilbert spaceVector of (2)The size of the space is equal to 2ⁿ. According to quantum computing theory, the following relationship holds:

in view of the above, a straightforward way to represent quantum computer states in memory is to store 2ⁿA complex number { alpha_iThese complex numbers are referred to as the amplitude of the corresponding ground state. Value | α_i|²Determining observation of the ground state i as output of a quantum circuit/computerProbability.

Quantum computation can be expressed as acting on the resulting statesVector of (2)Linear unitary operator U of (1):

since the basis in Hilbert space is defined, the operator U is defined by 2ⁿ×2ⁿAnd (5) representing the dimension matrix.

In quantum computing, a quantum gate is defined as a basic unitary operator, acting on one or several qubits. Practical quantum gates are 1 qubit, 2 qubit, and 3 qubit in size. Using these quantum gates, any quantum algorithm can be represented. According to equation (2) above, any quantum algorithm can be represented by the relation between the unitary matrix and the sequence of quantum gates and the operator U:

in other words, a quantum algorithm may be expressed as a tensor product of quantum gates, each acting on a subset of qubits.

Fig. 8 shows a typical set of quantum gates used in most common quantum algorithms. Among them, CNOT and CZ are examples of a special quantum gate, which are called controlled gates. Such a quantum gate acts on 2 or more qubits, where one or more qubits are used to control certain operations. The qubit that performs the operation is called the target, and the other qubits are called the control.

Using the graphical representation, a quantum circuit can be drawn for a quantum algorithm, as schematically shown in fig. 9. The numbered horizontal lines represent qubits, and the quantum gates acting on the qubits lie on the corresponding lines. The quantum gates are applied in left-to-right order. From the above relation (3), it can be concluded from the properties of the tensor product that the quantum gates acting on disjoint sets of qubits are swapped. A group of quantum gates sharing the same horizontal position is referred to as a layer of the quantum circuit.

As described above, the generic quantum circuit simulator stores 2 in computer memoryⁿArray of complex numbers (coefficient α of relation (1))_i). Using, for example, IEEE754 double-precision floating-point representation, this requires 16.2ⁿAnd (4) byte memory. One can readily see that as the number of qubits increases (e.g., 40 qubits require 16TiB memory), the memory requirements quickly become problematic for a computer. In this case, the simulator program must split the state vector into parts and store in the memory of several computers (nodes, as described above).

Let the quantum simulator operate on n ═ L + R quantum bits. Then, if a computer can only store 2 of the state vector^LElement, the number of required computer nodes is 2^R。

The natural way to select the basis in relation (1) above is to give a ground stateAssigning a state in which the qubit is |0 in accordance with the binary representation of the index i>Or |1>. For example: for three qubits, there are 8 ground statesIn the ground stateNext, all qubits are in state |0>In aQubit 1 in state |1>The other two are in state 0, inQubits 1 and 2 are in state |1>Qubit 0 in state |0>。

From the state vector distribution scheme, it is clear that when the states of the other R qubits are fixed equal to the binary representation of the node rank, each node stores all the amplitudes that determine the probabilities of |0> and |1> of the first L qubits. In this document, the first L qubits are referred to as local qubits and the last R qubits are referred to as global qubits.

When the quantum gates are applied to one or more local qubits, the matrix vector multiplication is performed locally on each node, without the need to access the amplitudes stored in the remote nodes, since the other qubits are not affected by the gates. When a quantum gate is applied to one or more global qubits, matrix vector multiplication cannot be performed because the compute nodes cannot directly access the memory of the remote computer. In this case, a data exchange mechanism is required.

One conventional approach provides a method of qubit reordering, which is performed if: qubits are renumbered, corresponding amplitudes are transmitted between nodes, and stored in the memory of the corresponding node according to the new qubit number and the level of the node. This process is called qubit swapping because qubits and amplitudes swap their positions, and is shown in fig. 11. This approach can be used to model quantum gates, which were originally applied to global qubits. In this case, it is only necessary to exchange numbers between the global qubits involved in the operation and some unused local qubits, and then to transmit the corresponding amplitudes between the nodes. Thereafter, the quantum gates acting on the local qubits can be modeled.

Distributed computing typically uses MPI libraries to perform data exchange between nodes, and thus the data exchange patterns in programs are represented by MPI operations. The qubit swap operation may be accomplished using a single MPI _ allcall operation. Any number of qubits less than or equal to R can be swapped at once. It is easy to prove that the amplitude of the transmission is equal in magnitude to

Where k is the number of global qubits exchanged. As is apparent from the above relation (4), less transmission data is required to exchange several qubits at a time than to exchange them sequentially one by one.

However, a typical quantum circuit may contain hundreds of thousands of gates. Without any optimization technique, each gate implies a matrix-vector multiplication, in the distributed case the amplitudes have to be transferred in large numbers between the nodes. Thus, in the above described approach, without carefully defining the set of qubits to be exchanged, there is additional overhead for data exchange if some of the qubits in the set are not included in a sufficient number of gate applications. This approach does not provide any suggestion on how to determine the optimal set of qubits to reorder.

Another approach describes an open source implementation of a distributed quantum circuit simulator (QuEST). In QuEST, the above described method of qubit reordering is used, but the implementation is limited to single qubit swapping.

The most complex approach to quantum circuit simulation uses a scheduling component (scheduler) that determines the order of gates to apply and the set of qubits to reorder. The gates are reordered into a sequence called a stage. A stage contains gates that act on local qubits. Within a stage, the gates form a subsequence called a cluster. Gates of the same cluster are fused into a single multi-qubit gate, which is modeled by a single matrix-vector multiplication. Between stages, qubit reordering is performed.

Fig. 12 shows such a gate and level cluster. Assuming qubits 0-2 are currently local and 3-4 global, the first stage consists of 2 clusters of gates outlined by gray lines and the second stage consists of clusters outlined by black lines. After applying gates for the first level qubits, reordering is performed: 3. 4 are exchanged with 1, 2 and then a second stage can be applied.

The main problem in implementing this approach is the cluster and level construction approach. The method does not describe any algorithm nor does it provide the source code of the scheduler.

In summary, although there is a major methodology for quantum circuit simulation, including gate scheduling, gate cluster construction, and qubit reordering, the problem of finding the optimal order of gates and qubits remains unsolved. All previous methods do not describe any method of computing qubits and gate permutations according to an explicit optimality criterion.

Disclosure of Invention

In view of the above problems and disadvantages, it is an object of embodiments of the present invention to improve upon existing approaches. The purpose is to provide a complex gate and quantum bit replacement calculation method for a quantum circuit simulator. This results in optimal data exchange and optimal quantum gate application scheduling in the quantum circuit simulator, and correspondingly reduces the amount of data transmitted between nodes. The computed permutations should provide a minimum number of matrix vector multiplications and a minimum number of data transfers. To this end, an apparatus and method should be provided that can be used in a distributed quantum circuit simulator for gate scheduling and qubit reordering scheduling.

This object is achieved by the embodiments of the invention described in the appended independent claims. Advantageous implementations of the invention are further defined in the dependent claims.

In particular, embodiments of the present invention provide an apparatus and method that compute optimal data exchange and quantum gate application scheduling, thereby significantly reducing the amount of data transferred between nodes, as well as the amount of arithmetic operations to be performed. All this will improve the performance of the quantum circuit simulator even by several times.

Embodiments of the present invention based on the relevance of tensor product operations allow the relationship (3) to be split into multiple factors in different ways, thereby constructing the factors from computational performance or memory consumption considerations:

the above relationship (5) and the exchange characteristics of the quantum gates are applied, laying the core of the embodiments of the present invention, optimizing the quantum circuit simulation by gate sequence replacement.

Based on the characteristics of the individual gates and using a greedy algorithm, the apparatus and method specifically compute permutations of gates and permutations of qubits, which results in a minimum number of clusters in a stage, and a minimum number of stages during simulation of the quantum circuit.

A first aspect of the invention provides apparatus for a quantum circuit simulator, the apparatus being for: obtaining a first quantum gate sequence; generating a second sequence of quantum gates by using a greedy algorithm, in particular a greedy algorithm with backtracking, the second sequence of quantum gates being a subsequence of the first sequence of quantum gates; computing a local qubit set and a global qubit set from the second quantum gate sequence; generating clusters of quantum gates, wherein each cluster comprises a subset of the quantum gates in the second sequence of quantum gates merged together using a greedy algorithm; generating a third sequence of quantum gates according to the order of the clusters, the third sequence of quantum gates including all quantum gates in the second sequence of quantum gates; providing the local qubit set and the global qubit set to the quantum circuit simulator; outputting the third sequence of quantum gates to the quantum circuit simulator.

The computed local and global qubit sets are in particular "optimal" local qubits and global qubit sets. Thus, "optimal" refers to the best state that the algorithm can do. That is, the algorithm searches for many variations of these qubit sets and may then select the qubit set with the largest gate number in the second sequence. The set of local qubits may be deliberately predefined before the device of the first aspect runs the algorithm. This means that the algorithm will include quantum gates that act on these qubits.

The apparatus of the first aspect may be for a distributed quantum circuit simulator and may provide gate scheduling and qubit reordering. In other words, the device can provide complex gate and qubit permutation calculations for a quantum circuit simulator. The computed permutations can result in optimal data exchange and quantum gate application scheduling in the quantum circuit simulator, thereby significantly reducing the amount of data transmitted between simulator nodes.

In one implementation of the first aspect, the apparatus is further configured to, when generating the set of quantum gates: the cluster comprising a larger number of sub-gates is ranked before the cluster comprising a smaller number of sub-gates in the order of the clusters.

In one implementation of the first aspect, the apparatus is further configured to, when generating the set of quantum gates: the clusters are generated according to the maximum possible number of quantum bits in the cluster.

The above implementation may improve the efficiency of the algorithm performed by the apparatus of the first aspect.

In one implementation of the first aspect, the apparatus is further configured to, when generating the set of quantum gates: selecting one by one all possible combinations of qubits associated with the second sequence of quantum gates according to a maximum possible number of qubits in the cluster; constructing a cluster for each combination; the cluster with the largest number of quantum gates is selected.

In one implementation of the first aspect, the apparatus is further configured to, when generating the set of quantum gates: maintaining a set of locked qubits; including quantum gates into a cluster if a matrix representation of the quantum gates is diagonal; skipping a quantum gate if at least one of the qubits acted upon by the quantum gate does not belong to the selected combination of qubits; and/or skipping a quantum gate if at least one of the quantum bits acted upon by the quantum gate is in the set of locked qubits; if a quantum gate is skipped, adding all qubits acted upon by the quantum gate to the set of locked qubits; otherwise, the quantum gates are included in the cluster.

In one implementation of the first aspect, the apparatus is further configured to, when generating the set of quantum gates: determining a cluster comprising a maximum number of quantum gates; outputting the quantum gates of the determined cluster, in particular inserting the output quantum gates into the third sequence of quantum gates; deleting the output quantum gate from the second sequence of quantum gates.

In one implementation of the first aspect, the apparatus is further configured to, when computing the set of local qubits and the set of global qubits: determining the set of local qubits and/or the set of global qubits according to a maximum number of local qubits and/or a maximum number of global qubits, respectively.

In one implementation of the first aspect, the apparatus is further configured to, when generating the second sequence of quantum gates: merging quantum gates acting on a single qubit with adjacent quantum gates in the first sequence of quantum gates acting on a subset of qubits comprising the same single qubit.

In one implementation of the first aspect, the apparatus is further configured to, when generating the second sequence of quantum gates: including into the second sequence of quantum gates a quantum gate that acts on a maximum of the maximum number of local qubits; if the first sequence of quantum gates comprises at least one quantum gate acting on a single qubit and another quantum gate acting on the same qubit and at least one other qubit, then the single qubit gate and the another multiple qubit gate are included together in the second sequence of quantum gates.

In one implementation of the first aspect, the apparatus is further configured to, when generating the second sequence of quantum gates: creating a branch of the greedy algorithm, wherein quantum gates are included into the second sequence of quantum gates; and/or creating branches of the greedy algorithm, wherein quantum gates in the first sequence of quantum gates are skipped; if a quantum gate is included, adding all qubits of the quantum gate effect to the local set of qubits; alternatively, if a quantum gate is skipped, all qubits acted upon by the quantum gate are added to the set of locked qubits.

In one implementation of the first aspect, the apparatus is further configured to, when generating the second sequence of quantum gates: at most, a maximum number of branches of the greedy algorithm is created.

In an implementation of the first aspect, the apparatus is further configured to, when applying the branch of the greedy algorithm: constructing the second sequence of quantum gates with as many gates as possible; each gate in the first sequence of quantum gates is tested and, depending on the test results, either the gate is skipped or the gate is included in the second sequence of quantum gates.

In one implementation of the first aspect, the apparatus is further configured to, when generating the second sequence of quantum gates: maintaining a set of locked qubits; skipping a quantum gate if the application quantum gate requires more than a predetermined threshold of qubits to be local qubits; and/or skipping a quantum gate if at least one of the qubits of the quantum gate effect is in a locked qubit set, and adding all of the qubits of the quantum gate effect to the locked qubit set if the quantum gate is skipped.

In one implementation of the first aspect, the apparatus is further configured to, when generating the second sequence of quantum gates: if the matrix representation of quantum gates is diagonal, including the quantum gates into the second sequence of quantum gates, without adding quantum bits of quantum gate effect to the set of local quantum bits; and/or including a quantum gate into the second sequence of quantum gates if all qubits of a quantum gate effect are already in the local set of qubits.

In one implementation of the first aspect, the apparatus is further configured to, when computing the set of local qubits and the set of global qubits: constructing a set of all qubits of a quantum gate effect in the first quantum gate sequence; including all qubits of a quantum gate role in the second quantum gate sequence into the local set of qubits; including all qubits in the set of all qubits and not in the local set of qubits into the global set of qubits.

A second aspect of the invention provides a quantum circuit simulator comprising an apparatus according to the first aspect or any implementation thereof.

A third aspect of the invention provides a method for quantum gate and qubit scheduling for a quantum circuit simulator, the method comprising: obtaining a first quantum gate sequence; generating a second sequence of quantum gates by using a greedy algorithm, in particular a greedy algorithm with backtracking, the second sequence of quantum gates being a subsequence of the first sequence of quantum gates; computing a local qubit set and a global qubit set from the second quantum gate sequence; generating clusters of quantum gates, wherein each cluster comprises a subset of the quantum gates in the second sequence of quantum gates merged together using a greedy algorithm; generating a third sequence of quantum gates according to the order of the clusters, the third sequence of quantum gates including all quantum gates in the second sequence of quantum gates; providing the local qubit set and the global qubit set to the quantum circuit simulator; outputting the third sequence of quantum gates to the quantum circuit simulator.

A fourth aspect of the present invention provides a computer program product comprising program code for controlling an apparatus according to the first aspect or any implementation thereof, or for performing, when implemented on a processor, a method of the third aspect or any implementation thereof.

In one implementation of the fourth aspect, the method further comprises, when generating the set cluster of quantum gates: the cluster comprising a larger number of sub-gates is ranked before the cluster comprising a smaller number of sub-gates in the order of the clusters.

In one implementation of the fourth aspect, the method further comprises, when generating the set cluster of quantum gates: the clusters are generated according to the maximum possible number of quantum bits in the cluster.

In one implementation of the fourth aspect, the method further comprises, when generating the set cluster of quantum gates: selecting one by one all possible combinations of qubits associated with the second sequence of quantum gates according to a maximum possible number of qubits in the cluster; constructing a cluster for each combination; the cluster with the largest number of quantum gates is selected.

In one implementation of the fourth aspect, the method further comprises, when generating the set cluster of quantum gates: maintaining a set of locked qubits; including quantum gates into a cluster if a matrix representation of the quantum gates is diagonal; skipping a quantum gate if at least one of the qubits acted upon by the quantum gate does not belong to the selected combination of qubits; and/or skipping a quantum gate if at least one of the quantum bits acted upon by the quantum gate is in the set of locked qubits; if a quantum gate is skipped, adding all qubits acted upon by the quantum gate to the set of locked qubits; otherwise, the quantum gates are included in the cluster.

In one implementation of the fourth aspect, the method further comprises, when generating the set cluster of quantum gates: determining a cluster comprising a maximum number of quantum gates; outputting the quantum gates of the determined cluster, in particular inserting the output quantum gates into the third sequence of quantum gates; deleting the output quantum gate from the second sequence of quantum gates.

In one implementation of the fourth aspect, the method further comprises, when computing the set of local qubits and the set of global qubits: determining the set of local qubits and/or the set of global qubits according to a maximum number of local qubits and/or a maximum number of global qubits, respectively.

In one implementation of the fourth aspect, the method further comprises, when generating the second sequence of quantum gates: merging quantum gates acting on a single qubit with adjacent quantum gates in the first sequence of quantum gates acting on a subset of qubits comprising the same single qubit.

In one implementation of the fourth aspect, the method further comprises, when generating the second sequence of quantum gates: including into the second sequence of quantum gates a quantum gate that acts on a maximum of the maximum number of local qubits; if the first sequence of quantum gates comprises at least one quantum gate acting on a single qubit and another quantum gate acting on the same qubit and at least one other qubit, then the single qubit gate and the another multiple qubit gate are included together in the second sequence of quantum gates.

In one implementation of the fourth aspect, the method further comprises, when generating the second sequence of quantum gates: creating a branch of the greedy algorithm, wherein quantum gates are included into the second sequence of quantum gates; and/or creating branches of the greedy algorithm, wherein quantum gates in the first sequence of quantum gates are skipped; if a quantum gate is included, adding all qubits of the quantum gate effect to the local set of qubits; alternatively, if a quantum gate is skipped, all qubits acted upon by the quantum gate are added to the set of locked qubits.

In one implementation of the fourth aspect, the method further comprises, when generating the second sequence of quantum gates: at most, a maximum number of branches of the greedy algorithm is created.

In an implementation of the fourth aspect, the method further comprises, when applying the branch of the greedy algorithm: constructing the second sequence of quantum gates with as many gates as possible; each gate in the first sequence of quantum gates is tested and, depending on the test results, either the gate is skipped or the gate is included in the second sequence of quantum gates.

In one implementation of the fourth aspect, the method further comprises, when generating the second sequence of quantum gates: maintaining a set of locked qubits; skipping a quantum gate if the application quantum gate requires more than a predetermined threshold of qubits to be local qubits; and/or skipping a quantum gate if at least one of the qubits acted upon by the quantum gate is in a locked set of qubits; if a quantum gate is skipped, all qubits acted upon by the quantum gate are added to the set of locked qubits.

In one implementation of the fourth aspect, the method further comprises, when generating the second sequence of quantum gates: if the matrix representation of quantum gates is diagonal, including the quantum gates into the second sequence of quantum gates, without adding quantum bits of quantum gate effect to the set of local quantum bits; and/or including a quantum gate into the second sequence of quantum gates if all qubits of a quantum gate effect are already in the local set of qubits.

In one implementation of the fourth aspect, the method further comprises, when computing the set of local qubits and the set of global qubits: constructing a set of all qubits of a quantum gate effect in the first quantum gate sequence; including all qubits of a quantum gate role in the second quantum gate sequence into the local set of qubits; including all qubits in the set of all qubits and not in the local set of qubits into the global set of qubits.

It should be noted that all devices, elements, units and modules described in the present application may be implemented in software or hardware elements or any type of combination thereof. All steps performed by the various entities described in the present application and the functions described to be performed by the various entities are intended to indicate that the respective entities are adapted or arranged to perform the respective steps and functions. Although in the following description of specific embodiments specific functions or steps performed by an external entity are not reflected in the description of specific detailed elements of the entity performing the specific steps or functions, it should be clear to a skilled person that the methods and functions may be implemented in corresponding hardware or software elements or any combination thereof.

Drawings

The following description of specific embodiments, taken in conjunction with the accompanying drawings, set forth the various aspects and implementations of the invention described above.

FIG. 1 shows an apparatus for a quantum circuit simulator, according to an embodiment of the invention.

Fig. 2 shows pseudo code of a cluster scheduling method performed by an apparatus for a quantum circuit simulator according to an embodiment of the invention.

Fig. 3 shows a block diagram of a cluster scheduling method performed by an apparatus for a quantum circuit simulator, according to an embodiment of the invention.

FIG. 4 illustrates pseudo code for a stage scheduling method performed by an apparatus for a quantum circuit simulator, according to an embodiment of the invention.

FIG. 5 shows a block diagram of a stage scheduling method performed by an apparatus for a quantum circuit simulator, according to an embodiment of the invention.

The scheduler results on the different upper circuits are shown in fig. 6(a), and the results of a 30-level upper circuit simulation for a quantum circuit simulator in accordance with an embodiment of the invention compared to a QuEST simulator on an 8-node cluster are shown in fig. 6 (b).

FIG. 7 illustrates a method for quantum gate and qubit scheduling for a quantum circuit simulator in accordance with an embodiment of the invention.

Fig. 8 shows a typical quantum gate and its quantum circuit representation.

Fig. 9 shows a graphical representation of a quantum circuit for a quantum algorithm.

Fig. 10 shows a scheme of state vector distribution.

Fig. 11 shows qubit swapping.

Fig. 12 shows a cluster of gates and stages.

Detailed Description

Fig. 1 shows an apparatus 100 according to an embodiment of the invention. The apparatus 100 is suitable for use in a quantum circuit simulator 110. The apparatus 100 may be part of a quantum circuit simulator 110 or may be connected to the quantum circuit simulator 110. The apparatus 100 is particularly useful for scheduling quantum gates and qubits of a quantum circuit simulator 110 in order to improve the performance of the quantum circuit simulator. The quantum circuit simulator 110 may be one or more classical computers or computer nodes that together are used to simulate the execution of a quantum circuit on a quantum computer. The quantum circuit simulator 110 may include at least one device 100 or may work with at least one device 100.

The apparatus 100 is configured to obtain a first sequence of quantum gates 101 from a quantum circuit or the like received as an input to the apparatus 100. The quantum circuit may be a quantum circuit to be simulated on/by the quantum circuit simulator 110. The apparatus 100 is further configured to generate a second quantum gate sequence 102, the second quantum gate sequence 102 being a subsequence of the first quantum gate sequence 101. Thus, the apparatus 100 uses a greedy algorithm, in particular with backtracking. That is, the second sequence of quantum gates 102 is generated from the first sequence of quantum gates 101 using a greedy algorithm with backtracking.

Furthermore, the apparatus 100 is configured to compute a set of local qubits 103a and a set of global qubits 103b, respectively, based on the generated second sequence of quantum gates 102. These qubit sets may be referred to as optimal or final qubit sets. Further, the apparatus 100 is also for generating a set of clusters 104 of quantum gates, wherein each cluster 104 includes a subset of quantum gates in the second sequence of quantum gates 102 merged together by using a greedy algorithm. The greedy algorithm may be similar in nature to the greedy algorithm used to generate the second sequence 102. The apparatus 100 is then used to generate a third sequence of quantum gates 105 according to the order of the cluster 104 of quantum gates, the third sequence of quantum gates 105 containing all quantum gates in the second sequence of quantum gates 102.

Finally, device 100 is configured to provide local qubit set 103a and global qubit set 103b to a quantum circuit simulator 110, and to output a third sequence of quantum gates 105 to the quantum circuit simulator. From these inputs, the quantum circuit simulator 110 may simulate a quantum circuit, with less data needing to be transferred between nodes of the simulator 110, and with less arithmetic operations being performed.

It is noted that in the apparatus 100 of fig. 1, the generation of the cluster 104 of quantum gates and the generation of the third sequence of quantum gates 105 may be referred to as a cluster scheduling algorithm. The algorithm allows the apparatus 100 to perform quantum gate scheduling of the simulator 110. The computation and output of qubit sets 103a and 103b may be referred to as a stage scheduling algorithm. The algorithm allows the device 100 to perform qubit scheduling for the simulator 110.

Fig. 2 shows pseudo code of a cluster scheduling algorithm that may be executed by the apparatus 100 according to an embodiment of the invention, in particular the apparatus 100 of fig. 1, to generate a set of clusters 104 and to output a third sequence of quantum gates 105. Fig. 3 further shows a block diagram of a cluster scheduling algorithm.

The cluster scheduling algorithm has two parameters: "qubits", i.e., the set of all qubits involved in the input sequence of the quantum gate; and k, which is the maximum possible number of quantum bits in cluster 104. The algorithm also takes as input a sequence of quantum gates, in particular the second sequence of quantum gates 102.

The algorithm further merges the quantum gates into a quantum gate cluster 104. Therefore, it attempts to minimize the total number of clusters 104 generated. Furthermore, the algorithm uses a greedy approach that: (a) find a cluster 104 containing the largest number of quantum gates; (b) returning the cluster 104 as a result; and removes the quantum gate cluster 104 from the input sequence of quantum gates; (c) (a) is performed again.

In step (a), the algorithm may select all possible combinations of k qubits one by one; from this combination, a sequence of quantum gates containing only qubits can be generated, wherein the quantum gates can be combined in one cluster 104; the largest size list may be selected as the next cluster 104.

The device 100 may also immediately merge single-qubit quantum gates. A single qubit gate g acting on a qubit q does not change the total number of stages if there is at least one multiple qubit gate acting on a qubit q. Thus, the quantum gate g can be immediately merged (merged) to any adjacent quantum gate containing a qubit q. Such optimization facilitates a significant speed up of the stage scheduling algorithm, which may be performed by the apparatus 100 and described below.

Fig. 4 illustrates pseudo code of a stage scheduling algorithm that may be executed by apparatus 100, in particular apparatus 100 of fig. 1, in accordance with an embodiment of the present invention to schedule and output qubits. Fig. 5 shows a block diagram of a stage scheduling algorithm.

The level scheduling algorithm has two parameters: l is_maxRepresents the maximum number of local qubits; b is_maxAnd represents the maximum number of branches to be created. The algorithm takes as input a list of quantum gates. The algorithm returns a set 103a of qubits that must be local during the current stage. Thus, the algorithm attemptsThe total number of stages is minimized. In particular, the algorithm uses a greedy approach, i.e., it constructs stages that contain as many quantum gates as possible.

The algorithm can also trace back quantum gate sequences and can maintain: (a) locals, a set of qubits that are intended to be local during a stage; (b) locked, i.e., a set of locked qubits (qubits that skip some operations); (c) b, the maximum possible number of new branches in this branch of the backtracking; (d) n, the number of quantum gates taken in this stage.

The process of the algorithm can be specifically analyzed according to the following cases:

a number of sub-gates must be skipped if at least one of the gate qubits or the gate control qubits is locked.

Otherwise, if the gate matrix is diagonal, it can also be applied to local and global qubits without adding any requirements to the qubits.

Otherwise, if the application of this quantum gate requires too many qubits to be local, the gate is skipped.

Otherwise, if all gate qubits have been required to be local, then the quantum gates can also be applied without adding any requirements.

Otherwise, if the application/skip gate cannot be uniquely determined, the algorithm branches on two branches: one branch skips the gate; the other branch applies this gate.

When the algorithm jumps the gate, all its qubits can be locked. When the algorithm decides to apply the off-diagonal gate, all its qubits may need to be local. If all qubits are locked during backtracking, the algorithm may return to the previous level of recursion.

Some qubits may be intentionally kept local, e.g., a set of locals qubits is pre-filled before starting the algorithm. This makes it possible to perform other optimizations in the simulator 110, since the memory placement layout of the amplitudes to be swapped can be adjusted.

The result of the method performed by the apparatus 100 is shown in fig. 6 (a). Device 100 has been tested with 3 global qubits and a different number of total qubits. The exchange of all global qubits with the same number of local qubits is applied according to the permutation between the resulting stages.

In fig. 6(b), a quantum circuit simulator 110 according to an embodiment of the invention (i.e. comprising the apparatus 100 shown in fig. 1) is compared with a QuEST simulator, in particular a QuEST simulator on an 8-node cluster. The simulator 110 according to embodiments of the present invention improves performance by an order of magnitude due to the reduced number of matrix-vector multiplications. This is because the device 100 implements cluster level algorithms/methods, and level scheduling algorithms/methods reduce the amount of data transmission.

FIG. 7 illustrates a method 700 according to an embodiment of the invention. Method 700 is for quantum gate and qubit scheduling for quantum circuit simulator 110. The method 700 may be performed by the apparatus 100 of fig. 1 or by a quantum circuit simulator 110 comprising the apparatus 100.

The method comprises the following steps: step 701, acquiring a first quantum gate sequence 101; step 702, generating a second quantum gate sequence 102 by using a greedy algorithm, in particular a greedy algorithm with backtracking, where the second quantum gate sequence 102 is a subsequence of the first quantum gate sequence 101; step 703, calculating a local qubit set 103a and a global qubit set 103b according to the second quantum gate sequence 102; step 704, generating a set of quantum gate clusters 104, wherein each cluster 104 comprises a subset of the quantum gates of the second sequence of quantum gates 102 merged together by using a greedy algorithm; step 705, generating a third quantum gate sequence 105 according to the order of the cluster 104, where the third quantum gate sequence 105 includes all quantum gates in the second quantum gate sequence 102; step 706, providing the local qubit set 103a and the global qubit set 103b to the quantum circuit simulator 110; step 707, outputting the third quantum gate sequence 105 to the quantum circuit simulator 110.

The invention has been described in connection with various embodiments and implementations as examples. However, other variations will become apparent to those skilled in the art and may be made in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims as well as in the description, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.