阅读说明：本技术 开关电路、混频器及电子设备 (Switching circuit, mixer, and electronic device ) 是由 周永丽 金香菊 赖砚 于 2019-04-30 设计创作，主要内容包括：本申请实施例公开了一种开关电路、混频器及电子设备,该开关电路包括第一金属氧化物半导体MOS管、第二MOS管、第三MOS管以及第四MOS管,该第一MOS管的栅极和该第四MOS管的栅极均连接第一端口,该第二MOS管的栅极和该第三MOS管的栅极均连接第二端口；该第一MOS管的栅极与该第一端口之间的引线的长度、该第二MOS管的栅极与该第二端口之间的引线的长度、该第三MOS管的栅极与该第二端口之间的引线的长度、该第四MOS管的栅极与该第一端口之间的引线的长度均相等；线性度较高。(The embodiment of the application discloses a switching circuit, a frequency mixer and electronic equipment, wherein the switching circuit comprises a first Metal Oxide Semiconductor (MOS) transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor, the grid electrode of the first MOS transistor and the grid electrode of the fourth MOS transistor are connected with a first port, and the grid electrode of the second MOS transistor and the grid electrode of the third MOS transistor are connected with a second port; the length of a lead between the grid electrode of the first MOS tube and the first port, the length of a lead between the grid electrode of the second MOS tube and the second port, the length of a lead between the grid electrode of the third MOS tube and the second port, and the length of a lead between the grid electrode of the fourth MOS tube and the first port are all equal; the linearity is high.)

A switch circuit is characterized by comprising a first Metal Oxide Semiconductor (MOS) transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor, wherein the grid electrode of the first MOS transistor and the grid electrode of the fourth MOS transistor are connected with a first port, and the grid electrode of the second MOS transistor and the grid electrode of the third MOS transistor are connected with a second port;

the length of a lead between the grid electrode of the first MOS tube and the first port, the length of a lead between the grid electrode of the second MOS tube and the second port, the length of a lead between the grid electrode of the third MOS tube and the second port, and the length of a lead between the grid electrode of the fourth MOS tube and the first port are all equal.

The switching circuit of claim 1,

a first lead between the grid electrode of the first MOS tube and the grid electrode of the fourth MOS tube passes through a first position, a second lead between the grid electrode of the second MOS tube and the grid electrode of the third MOS tube passes through a second position, and the first position and the second position are the same positions of different layers in the switch circuit; the length from the grid electrode of the first MOS tube to the lead of the first position, the length from the grid electrode of the second MOS tube to the lead of the second position, the length from the grid electrode of the third MOS tube to the lead of the second position and the length from the grid electrode of the fourth MOS tube to the lead of the first position are equal.

The switching circuit of claim 2,

the first MOS tube and the third MOS tube are aligned left and right and are symmetrical along a first symmetry axis, the second MOS tube and the fourth MOS tube are aligned left and right and are symmetrical along the first symmetry axis, the first MOS tube and the second MOS tube are aligned front and back and are symmetrical along a second symmetry axis, the third MOS tube and the fourth MOS tube are aligned front and back and are symmetrical along the second symmetry axis, and the first symmetry axis and the second symmetry axis are perpendicular to each other.

The switching circuit of claim 3,

one end of a third lead is connected with the third position of the first lead, and the other end of the third lead is connected with the first port; one end of a fourth lead is connected with the fourth position of the second lead, and the other end of the fourth lead is connected with the second port; the third position and the fourth position are symmetrical along the first axis of symmetry; the switching circuit is symmetrical along the first axis of symmetry.

The switch circuit according to any one of claims 1 to 4, wherein the gate of the first MOS transistor and the gate of the fourth MOS transistor are directly connected to form the first lead, the gate of the second MOS transistor and the gate of the third MOS transistor are directly connected to form the second lead, and the first lead and the second lead are both straight lines.

The switching circuit of claim 4, wherein a portion of the third lead is located on one side of the first axis of symmetry and another portion of the third lead is located on the other side of the first axis of symmetry; a portion of the fourth lead is located on one side of the first axis of symmetry and another portion of the fourth lead is located on the other side of the first axis of symmetry; the third lead passes through a fifth position, the fourth lead passes through a sixth position, and the fifth position and the sixth position are the same position of different layers in the switch circuit.

The switch circuit of claim 6, wherein the first portion of the third lead and a portion of the second lead are located at the same position in different layers of the switch circuit, the second portion of the third lead is parallel to the first axis of symmetry, the third portion of the third lead is located on either side of the first axis of symmetry, and the fourth portion of the third lead is parallel to the first axis of symmetry; a first part of the fourth lead and a part of the first lead are located at the same position of different layers in the switch circuit, a second part of the fourth lead is parallel to the first symmetry axis, a third part of the fourth lead is located on two sides of the first symmetry axis, and a fourth part of the fourth lead is parallel to the first symmetry axis; a third portion of the third lead passes through the fifth location and a third portion of the fourth lead passes through the sixth location.

The switching circuit of claim 5, wherein the third lead is located on one side of the first axis of symmetry and the fourth lead is located on the other side of the first axis of symmetry; a first portion of the third lead and a portion of the second lead are located at the same position in different layers of the switching circuit, and a second portion of the third lead is parallel to the first axis of symmetry; the first portion of the fourth lead and a portion of the first lead are located at the same position in different layers of the switch circuit, and the second portion of the fourth lead is parallel to the first axis of symmetry.

The switch circuit of any one of claims 4, 6, 7 or 8, wherein the third position and the first position are the same position and the fourth position and the second position are the same position.

A mixer comprising a switching circuit according to any one of claims 1 to 9.

The mixer of claim 10, wherein the first port and the second port are local oscillator ports that receive a driving voltage; the source electrode of the first MOS tube and the source electrode of the second MOS tube are both connected with a first input port, and the source electrode of the third MOS tube and the source electrode of the fourth MOS tube are both connected with a second input port; the drain electrode of the first MOS tube and the drain electrode of the third MOS tube are both connected with a first output port, and the drain electrode of the second MOS tube and the drain electrode of the fourth MOS tube are both connected with a second output port.

The mixer of claim 11, wherein the first input port and the second input port are each coupled to a low noise amplifier, and wherein the first output port and the second output port are each coupled to a transimpedance amplifier.

A mixer is characterized in that the mixer comprises a first MOS pipe group and a second MOS pipe group, and the circuit structure of the second MOS pipe group is the same as that of the first MOS pipe group; the first MOS tube group and the second MOS tube group are aligned left and right and are symmetrical along a reference symmetry axis; the first MOS tube group comprises a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube, a grid electrode of the first MOS tube and a grid electrode of the fourth MOS tube are connected with a first local oscillator port, and a grid electrode of the second MOS tube and a grid electrode of the third MOS tube are connected with a second local oscillator port;

the length of a lead between the grid of the first MOS tube and the first local oscillator port, the length of a lead between the grid of the second MOS tube and the second local oscillator port, the length of a lead between the grid of the third MOS tube and the second local oscillator port, and the length of a lead between the grid of the fourth MOS tube and the first local oscillator port are all equal.

The layout structure according to claim 13, wherein the first MOS transistor group and the second MOS transistor group are placed on different deep N-wells.

An electronic device comprising a mixer according to any of claims 10 to 14.