阅读说明：本技术 一种延迟过电流保护的电路及设计方法 (Circuit for delaying over-current protection and design method ) 是由 杨益昌 于 2020-05-28 设计创作，主要内容包括：本发明提供一种延迟过电流保护的电路及设计方法,包括：包括电源管理IC以及接在所述电源管理IC外部的回路；所述回路包括：第一保护电阻R1、第二保护电阻R2、n通道MOS管Q3、充电延时电路和比较电路；所述第一保护电阻R1与所述n通道MOS管Q3的D极分别连接电源管理IC,所述第二保护电阻R2连接n通道MOS管Q3的S极；所述n通道MOS管Q3的G极与比较电路的输出端连接,所述充电延时电路的输入端和比较电路的输入端分别与所述电源管理IC的输出端负极连接；所述第一保护电阻R1、第二保护电阻R2与充电延时电路均接地。本发明针对瞬间增加输出电流会触发过电流保护机制的情况,延迟过电流保护,从而增加电源管理IC使用上的便利性。(The invention provides a circuit for delaying overcurrent protection and a design method, comprising the following steps: the power management circuit comprises a power management IC and a loop connected outside the power management IC; the circuit comprises: the charging circuit comprises a first protection resistor R1, a second protection resistor R2, an n-channel MOS transistor Q3, a charging delay circuit and a comparison circuit; the first protection resistor R1 and the D pole of the n-channel MOS tube Q3 are respectively connected with a power management IC, and the second protection resistor R2 is connected with the S pole of the n-channel MOS tube Q3; the G pole of the n-channel MOS tube Q3 is connected with the output end of the comparison circuit, and the input end of the charging delay circuit and the input end of the comparison circuit are respectively connected with the negative pole of the output end of the power management IC; the first protection resistor R1, the second protection resistor R2 and the charging delay circuit are all grounded. The invention delays the overcurrent protection aiming at the condition that the overcurrent protection mechanism is triggered by the instant increase of the output current, thereby increasing the convenience of the use of the power management IC.)

1. A circuit for delaying overcurrent protection is characterized by comprising a power management IC and a loop connected outside the power management IC; the circuit comprises: the charging circuit comprises a first protection resistor R1, a second protection resistor R2, an n-channel MOS transistor Q3, a charging delay circuit and a comparison circuit; the first protection resistor R1 and the D pole of the n-channel MOS tube Q3 are respectively connected with a power management IC, and the second protection resistor R2 is connected with the S pole of the n-channel MOS tube Q3; the G pole of the n-channel MOS tube Q3 is connected with the output end of the comparison circuit, and the input end of the charging delay circuit and the input end of the comparison circuit are respectively connected with the negative pole of the output end of the power management IC; the first protection resistor R1, the second protection resistor R2 and the charging delay circuit are all grounded.

2. The circuit of claim 1, wherein the comparison circuit comprises: an inverter and a first comparator COMP 1; the charging delay circuit includes: a second comparator COMP2, a third protection resistor R3 and a capacitor C1; the output end of the inverter and the output end of a second comparator COMP2 are respectively connected with the G pole of the n-channel MOS transistor Q3; the input end of the inverter is connected with the output end of a first comparator COMP 1; the output end of the second comparator COMP2 is connected with a third protection resistor R3; the third protection resistor R3 is connected with a capacitor C1, and the capacitor C1 is grounded.

3. The circuit of claim 2, wherein the output terminal of the power management IC is connected in series with a low impedance resistor R4; the input end of the first comparator COMP1 and the input end of the second comparator COMP2 are respectively connected in parallel to two ends of the low impedance resistor R4.

4. A method for designing a delayed overcurrent protection, comprising:

an n-channel MOS transistor Q3 and a second protection resistor R2 connected with the first protection resistor R1 in parallel are added for reducing an overcurrent protection point in a normal working state;

a low-impedance resistor R4 and a comparison circuit are added for setting an overcurrent protection point when the output current is in an overlarge state;

a charging delay circuit is added for delaying the overcurrent protection time in a charging mode;

the trigger time for delaying the overcurrent protection is determined by testing the saturation point of the regulated charge.

5. The method of claim 4, further comprising:

the n-channel MOS transistor Q3 is set to the on state during initialization.

6. The design method of delaying overcurrent protection as recited in claim 4, wherein in the adding of the low impedance resistor R4 and the comparison circuit, the design method further comprises:

adding a first comparator COMP1, and setting the first comparator COMP1 to monitor the voltage state of a low-impedance resistor R4;

an inverter is added, and the inverter is arranged to receive the signal of the first comparator COMP1 and control the n-channel MOS transistor Q3 to be cut off.

7. The method of claim 4, wherein in the circuit for increasing charging delay, the method further comprises:

the capacitor C1 is added for delaying the overcurrent protection triggering time in a charging saturation mode;

a second comparator COMP2 is added to control the conduction of an n-channel MOS transistor Q3 after the capacitor C1 is charged to saturation;

the third protection resistor R3 is added for increasing the stability of the circuit.

Technical Field

The invention belongs to the technical field of power supply safety, and particularly relates to a circuit for delaying overcurrent protection and a design method.

Background

In general, the overcurrent protection of a power management IC is implemented by changing the resistance value outside the IC to adjust the magnitude of the overcurrent protection, and the larger the resistance is, the larger the overcurrent protection point is, and the smaller the resistance is, the smaller the overcurrent protection point is;

as shown in fig. 1, a conventional power management IC sets an overcurrent protection mode, and realizes current protection by externally connecting a protection resistor. As shown in fig. 2, a comparator is arranged in the power management IC, and a current source at the negative terminal of the comparator generates a reference voltage V-after flowing through the protection resistor; the positive end of the comparator is the voltage V + detected on the output inductor; if the output current increases, the voltage peak value on the inductor will increase, if the output current increases to exceed the reference voltage of the negative terminal V-of the comparator, the protection mechanism will be started, and the power management IC will be shut down and the system will be informed.

If the output is dynamically loaded or needs to increase the output current instantly in a short time, the over-current protection mechanism of the power management IC is triggered, which causes inconvenience in use.

Disclosure of Invention

In view of the above-mentioned deficiencies of the prior art, the present invention provides a circuit for delaying over-current protection and a design method thereof to solve the above-mentioned technical problems.

In a first aspect, the present invention provides a circuit for delayed overcurrent protection, including a power management IC and a loop external to the power management IC; the circuit comprises: the charging circuit comprises a first protection resistor R1, a second protection resistor R2, an n-channel MOS transistor Q3, a charging delay circuit and a comparison circuit; the first protection resistor R1 and the D pole of the n-channel MOS tube Q3 are respectively connected with a power management IC, and the second protection resistor R2 is connected with the S pole of the n-channel MOS tube Q3; the G pole of the n-channel MOS tube Q3 is connected with the output end of the comparison circuit, and the input end of the charging delay circuit and the input end of the comparison circuit are respectively connected with the negative pole of the output end of the power management IC; the first protection resistor R1, the second protection resistor R2 and the charging delay circuit are all grounded.

Further, the comparison circuit includes: an inverter and a first comparator COMP 1; the charging delay circuit includes: a second comparator COMP2, a third protection resistor R3 and a capacitor C1; the output end of the inverter and the output end of a second comparator COMP2 are respectively connected with the G pole of the n-channel MOS transistor Q3; the input end of the inverter is connected with the output end of a first comparator COMP 1; the output end of the second comparator COMP2 is connected with a third protection resistor R3; the third protection resistor R3 is connected with a capacitor C1, and the capacitor C1 is grounded.

Further, the negative electrode of the output end of the power management IC is connected with a low-impedance resistor R4 in series; the input end of the first comparator COMP1 and the input end of the second comparator COMP2 are respectively connected in parallel to two ends of the low impedance resistor R4.

In a second aspect, the present invention provides a design method for delaying overcurrent protection, including:

an n-channel MOS transistor Q3 and a second protection resistor R2 connected with the first protection resistor R1 in parallel are added for reducing an overcurrent protection point in a normal working state;

a low-impedance resistor R4 and a comparison circuit are added for setting an overcurrent protection point when the output current is in an overlarge state;

a charging delay circuit is added for delaying the overcurrent protection time in a charging mode;

the trigger time for delaying the overcurrent protection is determined by testing the saturation point of the regulated charge.

Further, the design method further includes:

the n-channel MOS transistor Q3 is set to the on state during initialization.

Further, in the adding of the low impedance resistor R4 and the comparison circuit, the design method further includes:

adding a first comparator COMP1, and setting the first comparator COMP1 to monitor the voltage state of a low-impedance resistor R4;

an inverter is added, and the inverter is arranged to receive the signal of the first comparator COMP1 and control the n-channel MOS transistor Q3 to be cut off.

Further, in the circuit for increasing charging delay, the design method further includes:

the capacitor C1 is added for delaying the overcurrent protection triggering time in a charging saturation mode;

a second comparator COMP2 is added to control the conduction of an n-channel MOS transistor Q3 after the capacitor C1 is charged to saturation;

the third protection resistor R3 is added for increasing the stability of the circuit.

The beneficial effect of the invention is that,

aiming at the condition that the overcurrent protection mechanism is triggered by the instant increase of the output current, the circuit and the design method delay the current set point of the overcurrent protection through the charging function of the capacitor C1 and adjust the capacitance value of the capacitor C1 to delay the triggering time of the overcurrent protection, thereby increasing the convenience of the use of a power management IC.

In addition, the invention has reliable design principle, simple structure and very wide application prospect.

Drawings

In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an overcurrent protection resistor arrangement according to the prior art;

FIG. 2 is a schematic diagram of the internal structure of a prior art power management IC of the present invention;

fig. 3 is a schematic circuit diagram of an embodiment of the present invention.

Detailed Description

In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it is to be understood that the terms "first", "second", and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art through specific situations.

The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.