阅读说明：本技术 提供电流补偿的系统和装置 (System and apparatus for providing current compensation ) 是由 M·G·隆美尔 K·瓦根索纳 R·格兰卡里奇 M·U·舒伦克 于 2019-02-19 设计创作，主要内容包括：为了提供用于动力系统的自适应泄漏补偿：第一电流路径(324)包括第一晶体管(306)和第二晶体管(310)；第二电流路径(326)包括第三晶体管(330)和第四晶体管(332)；电流镜(328)包括第五晶体管(334)和第六晶体管(336)。在第一晶体管(306)和第三晶体管(330)之间存在第一比率(N)。在第二晶体管(310)和第四晶体管(332)之间存在第二比率(M)。在第五晶体管(334)和第六晶体管(336)之间存在第三比率(N*)。第三比率(N*)大于或等于第二比率(M)。第二比率(M)大于或等于第一比率(N)。(To provide adaptive leakage compensation for a power system: the first current path (324) comprises a first transistor (306) and a second transistor (310); the second current path (326) comprises a third transistor (330) and a fourth transistor (332); the current mirror (328) includes a fifth transistor (334) and a sixth transistor (336). There is a first ratio (N) between the first transistor (306) and the third transistor (330). There is a second ratio (M) between the second transistor (310) and the fourth transistor (332). A third ratio (N) exists between the fifth transistor (334) and the sixth transistor (336). The third ratio (N) is greater than or equal to the second ratio (M). The second ratio (M) is greater than or equal to the first ratio (N).)

1. An apparatus, comprising:

a first current path including a first transistor including a first gate, a first drain, and a first source, and a second transistor including a second gate, a second drain, and a second source, the first drain coupled to the second drain;

a second current path including a third transistor and a fourth transistor, the third transistor including a third gate, a third drain, and a third source, the fourth transistor including a fourth gate, a fourth drain, and a fourth source, the third source coupled to the first source and the third gate, the third drain coupled to the fourth drain, the fourth source coupled to the fourth gate and the second source; and

a current mirror including a fifth transistor and a sixth transistor, the fifth transistor including a fifth gate, a fifth drain, and a fifth source, the sixth transistor including a sixth gate, a sixth drain, and a sixth source, the fifth drain coupled to the third drain, the sixth gate, and the fifth gate, the sixth drain coupled to the second drain, the fifth source coupled to the sixth source and the fourth source, wherein a first ratio exists between the first transistor and the third transistor, a second ratio exists between the second transistor and the fourth transistor, and a third ratio exists between the fifth transistor and the sixth transistor, the third ratio being greater than or equal to the second ratio, the second ratio being greater than or equal to the first ratio.

2. The apparatus of claim 1, wherein the first transistor and the third transistor are PMOS transistors, and the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor are NMOS transistors.

3. The apparatus of claim 1, wherein the first ratio is based on a first channel width of the first transistor and a second channel width of the third transistor, the second ratio is based on a third channel width of the second transistor and a fourth channel width of the fourth transistor, and the third ratio is based on a fifth channel width of the fifth transistor and a sixth channel width of the sixth transistor.

4. The apparatus of claim 1, wherein the first current path is coupled to the second current path and the current mirror.

5. The apparatus of claim 1, wherein the second current path is coupled to the first current path and the current mirror.

6. An apparatus, comprising:

a regulator configured to regulate a flow of current through the power converter using the first transistor and the second transistor;

a sensor configured to:

detecting a first current associated with the first transistor and a second current associated with the second transistor, wherein the first current is detected by a third transistor via a current mirror configuration and the second current is detected by a fourth transistor via the current mirror configuration; and is

Determining a difference between the first current and the second current; and

an adaptive compensation circuit configured to adjust a third current through an output of the power converter based on the difference between the first current and the second current.

7. The apparatus of claim 6, wherein the first current is a first leakage current and the second current is a second leakage current.

8. The apparatus of claim 7, wherein the first leakage current is a first current flowing from a first drain of the first transistor and the second leakage current is a second current flowing into a second drain of the second transistor.

9. The apparatus of claim 6, wherein the adjustment is deducting the difference between the first current and the second current from the output of the power converter.

10. The apparatus of claim 6, wherein the adaptive compensation circuit increases an efficiency of the power converter.

11. The apparatus of claim 6, wherein the adaptive compensation circuit may adjust the third current when the first transistor and the second transistor are off.

12. A system, comprising:

a regulator coupled to an output of a power converter, the regulator configured to regulate current in the power converter;

a sensor configured to: detecting a first current associated with a first transistor and a second current associated with a second transistor, wherein the first current is detected by a third transistor via a current mirror configuration and the second current is detected by a fourth transistor via the current mirror configuration; and determining a difference between the first current and the second current; and

an adaptive compensation circuit that adjusts a third current through the output of the power converter based on the difference between the first current and the second current.

13. The system of claim 12, wherein the first current is a first leakage current and the second current is a second leakage current.

14. The system of claim 13, wherein the first leakage current is a first current flowing from a first drain of the first transistor and the second leakage current is a second current flowing into a second drain of the second transistor.

15. The system of claim 12, wherein the adjustment is subtracting the difference between the first current and the second current from the output of the power converter.

16. The system of claim 12, wherein the adaptive compensation circuit increases the efficiency of the power converter.

17. The system of claim 12, wherein the adaptive compensation circuit can adjust the third current when the first transistor and the second transistor are off.

18. The system of claim 12, wherein the regulator comprises a set of synchronous transistors comprising a high-side transistor and a low-side transistor.

19. The system of claim 18, wherein the low-side transistor may be a diode.

Technical Field

The present application relates generally to power converters, and more particularly to methods and apparatus to provide current compensation.

Background

A power converter is a circuit that converts an input voltage to a desired output voltage. One type of power converter is a switched mode power supply in which a switch is used to convert an input voltage to a desired output voltage. A switched mode power supply may convert an Alternating Current (AC) voltage to a Direct Current (DC) voltage, or may convert a DC voltage of one level to a DC voltage of another level. For example, a buck converter converts an input DC voltage to a lower desired output DC voltage by controlling transistors and/or switches to charge and/or discharge inductors and/or capacitors to maintain the desired output DC voltage.

Disclosure of Invention

Certain examples disclosed herein improve the efficiency of a power converter by removing leakage current from the output of the power converter for low quiescent current applications. An example apparatus includes: a first current path comprising a first transistor comprising a first gate, a first drain, and a first source, and a second transistor comprising a second gate, a second drain, and a second source, the first drain coupled to the second drain; a second current path including a third transistor including a third gate, a third drain, and a third source, and a fourth transistor including a fourth gate, a fourth drain, and a fourth source, the third source coupled to the first source and the third gate, the third drain coupled to the fourth drain, and the fourth source coupled to the fourth gate and the second source; and a current mirror including a fifth transistor and a sixth transistor, the fifth transistor including a fifth gate, a fifth drain, and a fifth source, the sixth transistor including a sixth gate, a sixth drain, and a sixth source, the fifth drain coupled to the third drain, the sixth gate, and the fifth gate, the sixth drain coupled to the second drain, and the fifth source coupled to the sixth source and the fourth source, wherein there is a first ratio between the first transistor and the third transistor, a second ratio between the second transistor and the fourth transistor, and a third ratio between the fifth transistor and the sixth transistor, the third ratio being greater than or equal to the second ratio, the second ratio being greater than or equal to the first ratio.

Drawings

Fig. 1 is a diagram of an example buck converter.

Fig. 2 is a diagram of an example power converter including a sensor and an adaptive compensation circuit.

FIG. 3 is a diagram of an example circuit implementation of the sensor and adaptive compensation circuit of FIG. 2.

Fig. 4 is a graph showing output voltage versus ambient temperature for the circuits of fig. 2 and 3 with and without adaptive compensation.

Fig. 5 is a graph showing leakage current versus ambient temperature for the circuits of fig. 2 and 3 with and without adaptive compensation.

Fig. 6 is a graph illustrating the efficiency improvement of the buck converter 100 when using the adaptive compensation circuit of fig. 2 and 3.

Fig. 7 is a flow diagram representing machine readable instructions that may be executed to implement the adaptive compensation circuit of fig. 2.

Fig. 8 is a block diagram of an example processor platform that may execute the example instructions of fig. 7 to implement the adaptive compensation circuit of fig. 2 and 3.

Detailed Description

The figures are not drawn to scale. Generally, the same reference numbers will be used throughout the drawings and the description will refer to the same or like parts.

Power converters (e.g., buck converters, boost converters, AC-AC converters, DC-DC converters, AC-DC converters, etc.) may include power switches (e.g., relays, diodes, etc.) that switch current from one path to another. Such switches may be solid-state in nature and therefore do not cause a physical disconnection between the multiple paths that cause current to flow. In some cases, a small amount of leakage current (i.e., current that flows when the ideal current is zero) may flow through the switch and into an undesired path. In high power ultra-low quiescent current applications, the leakage current will increase as the ambient temperature around the switch increases. The increase in leakage current may cause the voltage at the output of the power converter to run away and may cause failure of the connected circuit. To prevent leakage current from rising with temperature, compensation circuitry may be added to the power converter to draw leakage current from the output. Traditionally, compensation circuits are based on worst-case leakage current drawn or subtracted from the output. Another common compensation circuit will draw either a high side leakage current or a low side leakage current from the output. The other compensation circuit mirrors the leakage current directly from the sensing device to the output voltage.

When an electronic device is attached to a charging source, leakage currents occur due to the non-ideal characteristics of the electronic device, causing the source to slowly discharge. Typically, leakage current occurs because when an electronic device (e.g., transistor, diode, etc.) connected to a charging source is intended to be turned off, the electronic device conducts a small amount of current. When the device is in a low quiescent current application, the device will sit idle for a long time. Leakage currents are typically in the microampere range, while currents through devices in power converter applications when not in an idle state are in the range of tens of amperes to hundreds of amperes.

Leakage currents occur in the semiconductor due to the tunneling of mobile charge carriers through the insulating region. For example, mobile charge carriers may tunnel between junctions of differently doped semiconductors (e.g., P-type, N-type). When the device is off and no current is provided, leakage current in a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) may occur from source to drain and allow current to flow in the intended conduction path. Leakage current will increase the power consumption of the device regardless of the ambient temperature, which may cause serious failure of the device if the leakage current increases indefinitely.

In a switched mode power supply, the efficiency of the power supply can be improved by using a set of synchronous switches. The set of synchronous switches may be two switches that operate such that when the high-side switch (e.g., transistor) is on, the low-side switch (e.g., transistor) is off, and when the high-side switch is off, the low-side switch is on. An example implementation of a synchronous switch may be a high-side transistor as a PMOS transistor and a low-side transistor as an NMOS transistor. In this example embodiment, the high-side PMOS transistor has a wider channel than the low-side NMOS transistor. The larger width of the channel of the PMOS transistor is due to the lower mobility of carriers in the PMOS transistor than in the NMOS transistor. The larger width of the channel allows for similar switching speeds of turning on and off between the PMOS transistor and the NMOS transistor. However, due to the larger width of the channel, the leakage current of the high-side PMOS transistor is typically larger than the leakage current of the low-side NMOS transistor. This will cause a net value of the high side leakage current and the low side leakage current to flow to the output of the switched mode power supply. Different embodiments of a set of synchronous switches may use PMOS transistors, NMOS transistors, Bipolar Junction Transistors (BJTs), junction gate field effect transistors (JFETs), diodes, etc., or any combination thereof.

A more adaptive, comprehensive and complete solution to the increase in leakage current with temperature is to actively sense the leakage current in a set of synchronous switches, determine the difference between the leakage currents, and simply remove the difference from the output of the power converter. As described herein, current may be drawn by the output when the high-side transistor has a greater leakage current than the low-side transistor. In addition, the solution is adaptive and excess leakage current in the output of the power converter can be removed across any ambient temperature of the power converter. Total power dissipated by leakage current through the high-side transistor and the low-side transistor(s) ((

) The efficiency of a power converter using this transistor can be affected as follows:

examples disclosed herein provide an adaptive approach to reduce leakage current (e.g., to improve efficiency) of such transistors and power converters (e.g., buck converters, boost converters, AC-AC converters, DC-DC converters, AC-DC converters, etc.) in which they are deployed. The leakage current affects the total power dissipation of the power converter and therefore reducing the amount of leakage current reduces the total power dissipated by the leakage current in the above referenced equationWhen the leakage current through the transistor decreases, the power dissipated by the transistor will decrease. Furthermore, no current will flow to the output of the power converter. This will prevent any voltage build up at the output capacitor when the transistor is intended to be turned off. The resulting effect of reducing leakage current through the transistor is that the efficiency of the power converter under various loads will be improved.

Fig. 1 is a diagram of an example buck converter 100. Buck converter 100 has an example input voltage node V_in102, which is referenced to an example Ground Node (GND) 104. The buck converter 100 includes a high-side transistor 106 (M)_HS) Having a node V coupled to the input voltage_in102, respectively. In the example of fig. 1, the drain of the high-side transistor 106 is coupled to the switch node SW 108. The switch node SW 108 is coupled to a low-side transistor 110 (M)_LS) Of the substrate. The source of the low-side transistor 110 is coupled to the Ground Node (GND) 104. The current through the high-side transistor 106 is labeled I_HSAnd the current through the low-side transistor 110 is labeled I_LS. The switch node SW 108 is coupled to an inductor 112, and the inductor 112 is coupled to the positive terminal of a capacitor 114. The negative terminal of capacitor 114 is coupled to ground node (gnd) 116. The positive terminal of the capacitor 114 is also coupled to the output voltage node V_O118, output voltage node V_O118 may be a voltage source for other circuits not shown in fig. 1. Electric powerInductor 112, capacitor 114, and output voltage node V_O118 comprise the output stage of the buck converter 100. The current through the output stage is marked I_OS。

The high-side transistor 106 and the low-side transistor 110 are examples of a set of synchronous transistors (e.g., switches) in the buck converter 100. The high-side transistor 106 and the low-side transistor 110 may be controlled by control signals 120 and 122 applied to the gates of the high-side transistor 106 and the low-side transistor 110, respectively.

The function of a DC power converter is to temporarily store input energy in electronic components (e.g., inductors, capacitors, inductive elements, capacitive elements, etc.) and then discharge that energy at different voltages at an output load. In the buck converter 100, when the high-side transistor 106 is on and the low-side transistor 110 is off, the current (I) flows_HS) From input voltage node V_in102 to inductor 112, which charges at a linear rate. When inductor 112 charges, it stores energy in a current (I) flowing through inductor 112_OS) In the magnetic field generated. In addition, when the high-side transistor 106 is turned on and the low-side transistor 110 is turned off, the capacitor 114 also charges to the desired output voltage level and provides current from the input to the load. When the high-side transistor is off, the low-side transistor turns on current in the buck converter 100 to continue flowing to the load. The energy stored in the magnetic field of the inductor 112 dissipates and in so doing generates a current that will flow through the circuit and to the load. The current (I) flowing through the output stage of the buck converter 100_OS) Will be equal to the current (I) flowing through the low-side transistor 110_LS) Of the amplitude of (c). Electric current (I)_OS) From the inductor 112 to the capacitor 114 and the load, while the capacitor 114 maintains the desired output voltage of the buck converter 100 and the load receives power. Current returns to the inductor 112 by flowing through the Ground Node (GND)116, the Ground Node (GND)104 and the low-side transistor 110. The switching mode described above allows a continuous current to flow into the load of the buck converter 100.

The controller may be implemented to control the high-side transistor 106 and the low-side transistor 110 such that the two transistors alternate between the high-side transistor 106 being on and the low-side transistor 110 being off, and the high-side transistor 106 being off and the low-side transistor 110 being on. This may be done at a frequency and duty cycle determined by the controller so that the output voltage of the buck converter 100 may be maintained at the desired output voltage and within a safe operating region of the buck converter 100.

FIG. 2 illustrates an example power converter 200 that includes an input voltage node V referenced to a Ground Node (GND)204_in202. An output stage 208, a regulator 224, a sensor 226, and an adaptive compensation circuit 228.

In the illustrated example, the output stage 208 includes an inductor 212, a capacitor 214, a ground node (gnd)216, and an output voltage node V _O218. The output stage 208 may include a node V that will input a voltage when driven by the regulator 224_inThe voltage at 202 is converted to a component of the desired output voltage (e.g., a capacitor, an inductor, an inductive element, a capacitive element, etc.). The output stage 208 is coupled to the regulator 224 and the adaptive compensation circuit 228.

An inductor 212 is coupled to the drain of the high-side transistor 206 and the drain of the low-side transistor 210. Inductor 212 is further coupled to the positive terminal of capacitor 214, which forms output voltage node V _O218, the output voltage node V _O218 may be a voltage source for other circuits not shown in fig. 2. The negative terminal of capacitor 214 is coupled to ground node (gnd) 216.

In the illustrated example of fig. 2, the regulator 224 is configured with a high-side transistor 206 (M)_HS) And a low side transistor 210 (M)_LS) And any type of power transistor (e.g., transistor 206 or 210, MOSFET, Insulated Gate Bipolar Transistor (IGBT), etc.) may be utilized. Power transistors can be designed to operate quickly with low rise and fall times, can withstand sustained high currents, can block current at high voltages, and can operate at various temperatures being set. The source of the high-side transistor 206 is coupled to the input voltage node V _in202. The drain of the high-side transistor 206 is coupled to the drain of the low-side transistor 210. The source of the low-side transistor 210 is coupled to the Ground Node (GND) 204. In some examples, a high-side crystalThe transistor 206 and the low-side transistor 210 are flipped (toggle) to allow the output current to flow to the output stage 208 or to the Ground Node (GND)204, depending on the state of the high-side transistor 206 and the low-side transistor 210. For example, when the high-side transistor 206 is enabled and the low-side transistor 210 is disabled, the input voltage node V_inThe input voltage at 202 is shorted to the output stage 208 via the high-side transistor 206, causing an output current to flow through the high-side transistor 206 and to the output stage 208. When the high-side transistor 206 is enabled and the low-side transistor 210 is disabled, the current (I) flowing through the high-side transistor 206_HS) Is equal to the current (I) flowing through the output stage 208_OS) Of the amplitude of (c). When the high-side transistor 206 is disabled and the low-side transistor 210 is enabled, current is provided from the inductor 212. When the high-side transistor 206 is disabled and the low-side transistor 210 is enabled, current returns to the inductor 212 by flowing through the Ground Node (GND)216, the Ground Node (GND)204, and the low-side transistor 210. When the high-side transistor 206 is disabled and the low-side transistor 210 is enabled, the current (I) flowing through the output stage 208_OS) Is equal to the current (I) flowing through the low-side transistor 210_LS) Of the amplitude of (c). Thus, one or more control signals 220 and 222 may be applied to the gates of the high-side transistor 206 and the low-side transistor 210 to switch the flow of current to input the voltage node V_inNode V for converting input voltage at 202 to output voltage_OA desired output voltage at 218 (e.g., such as in a power converter).

In the illustrated example of FIG. 2, the sensor is coupled to the input voltage node V _in202. Ground Node (GND)204, regulator 224, and adaptive compensation circuit 228. The sensors 226 may be implemented as hardware or software. As a hardware implementation, the sensor 226 may include a sensing Field Effect Transistor (FET), a shunt resistor, a current transformer, a fiber optic sensor, a fluxgate transformer, and the like. For a hardware implementation, an amplifier is used to convert the output of one of the above sensors to a control signal for the rest of the power converter 200. As a software implementation, the microcontroller may receive a signal from either the high-side transistor 206 or the low-side transistor 210 for monitoring, and thenAnd then generates an output based on the signal to communicate with another portion of the power converter 200. The sensor 226 allows the current (I) flowing through the high-side transistor 206 to be detected when the transistor is off_HS) And the current (I) through the low side transistor 210_LS). This allows other portions of the power converter 200 to determine whether compensation for leakage current is required. If compensation is determined to be needed based on the current sensed by the sensor 226, the adaptive compensation circuit 228 will apply compensation (e.g., make an adjustment) to the output stage 208.

In the illustrated example, the adaptive compensation circuit 228 is coupled to the sensor 226 and to the output stage 208. The adaptive compensation circuit 228 may be implemented as hardware or software. As a hardware implementation, the adaptive compensation circuit 228 may be a current mirror, a zener diode current source, a transistor current source with diode compensation, or the like. As a software implementation, the adaptive compensation circuit 228 may receive a signal from the sensor 226 and generate another signal based on the signal to compensate for the current through the output stage 208. The adaptive compensation circuit 228 allows the leakage current (I) flowing through the high-side transistor 206 to be removed or subtracted from the output stage 208_HS) And leakage current (I) through the low side transistor 210_LS) The difference of (a). This is done after determining that compensation for leakage current is required. Leakage current I when the high-side transistor 206 and the low-side transistor 210 are off_HSAnd leakage current I_LSIs the current (I) flowing through the output stage 208_OS)。

Fig. 3 is an illustration of an example hardware implementation of the power converter 200 as shown in the block diagram of fig. 2. The power converter 300 includes an input voltage node V referenced to a Ground Node (GND)304_in302. Output stage 308, regulator 324, sensor 326, and adaptive compensation circuit 328. The output stage 208 of fig. 2 is represented as output stage 308. The regulator 224 of fig. 2 is represented as regulator 324. The sensor 226 of FIG. 2 is represented in hardware as sensor 326. The adaptive compensation circuit 228 of fig. 2 is represented in hardware as an adaptive compensation circuit 328.

In the illustrated example of fig. 3, the regulator 324 regulates the current (I) through the output stage 308_OS) The flow of (c). The regulator 324 can regulatePower converter 300 such that at input voltage node V_inThe input voltage at 302 is shorted to the output stage 308, allowing current to flow from the input voltage node V_in302 to the output stage 308. When current flows from input voltage node V_in302 flow through the high-side transistor 306 (M) to the output stage 308_HS) Current (I) of_HS) Is equal to the current (I) flowing through the output stage 308_OS) Of the amplitude of (c). Alternatively, regulator 324 may regulate power converter 300 such that current flows between regulator 324 and output stage 308. When current flows between the regulator 324 and the output stage 308, the current (I) flowing through the output stage_OS) Is equal to the current through the low side transistor 310 (M)_HS) Current (I) of_LS) Of the amplitude of (c). Leakage current I when control signals 320 and 322 are configured to cause high-side transistor 306 and low-side transistor 310 to turn off_HSAnd leakage current I_LSMay flow through the regulator 324 and to the output stage 308. This leakage current may be sensed by sensor 326 and then mirrored to adaptive compensation circuit 328. The current mirrored to the adaptive compensation circuit 328 is then used to subtract the leakage current (I) from the output stage 308_OS) Thereby, the negative effects of leakage current (e.g., power loss, malfunction, etc.) may be eliminated.

In the illustrated example, the output stage 308 includes an inductor 312, a capacitor 314, a ground node (gnd)316, and an output voltage node V_O318. The output stage 308 may include a node V that will input a voltage when driven by the regulator 324_inThe input voltage at 302 is converted to a component of the desired output voltage (e.g., a capacitor, an inductor, an inductive element, a capacitive element, etc.). The output stage 308 is coupled to the regulator 324 and the adaptive compensation circuit 328.

An inductor 312 is coupled to the drain of the high-side transistor 306 and the drain of the low-side transistor 310. The inductor 312 is further coupled to a positive terminal of a capacitor 314, which forms an output voltage node V_O318, the output voltage node V_O318 may be a voltage source for other circuits not shown in fig. 3. The negative terminal of capacitor 314 is coupled to ground node (gnd) 316.

In the illustrated example of fig. 3, the regulator 324 is configured with a high-side transistor 306 and a low-side transistor 310, and may utilize any type of power transistor (e.g., transistor 306 or 310, MOSFET, Insulated Gate Bipolar Transistor (IGBT), etc.). Power transistors can be designed to operate quickly with low rise and fall times, can withstand sustained high currents, can block current at high voltages, and can operate at various temperatures being set. The source of the high-side transistor 306 is coupled to the input voltage node Vin 302. The drain of the high-side transistor 306 is coupled to the drain of the low-side transistor 310. The high-side PMOS transistor 306 and the low-side NMOS transistor 310 form a first current path. The source of the low-side transistor 310 is coupled to the Ground Node (GND) 304. In some examples, the high-side transistor 306 and the low-side transistor 310 are flipped to allow the output current to flow to the output stage 308 or to the Ground Node (GND)304, depending on the state of the high-side transistor 306 and the low-side transistor 310. For example, when the high-side transistor 306 is enabled and the low-side transistor 310 is disabled, the input voltage at the input voltage node Vin 302 is shorted to the output stage 308 via the high-side transistor 306, resulting in an output current flowing to the output stage 308. When the high-side transistor 306 is disabled and the low-side transistor 310 is enabled, the output current flows out to a ground node (gnd)316 via the low-side transistor 310. Accordingly, one or more control signals 320 and 322 may be applied to the gates of the high-side transistor 306 and the low-side transistor 310 to switch the flow of current to convert the input voltage at the input voltage node Vin 302 to the output voltage node V_O318 (e.g., in a power converter).

In the illustrated example of fig. 3, the sensor 326 is coupled to the regulator 324, the adaptive compensation circuit 328, the input voltage node Vin 302, the Ground Node (GND) 304. The sensor 326 uses a sense MOSFET to sense leakage current (I) flowing through the high-side transistor 306_HS) And leakage current (I) through the low side transistor 310 in the regulator 324_LS). The high-side transistor 306 is a PMOS transistor. The low-side transistor 310 is an NMOS transistor. The high-side PMOS transistor 306 is coupled to the high-side sense transistor 330 (M)_HS-SENSE). High side sensingThe transistor 330 is a PMOS transistor. The coupling between the high-side PMOS transistor 306 and the high-side sensing PMOS transistor 330 is an example of PMOS sensing. May be based on leakage current (I) flowing through the high-side PMOS transistor 306_HS) And the sense current (I) flowing through the high-side sense PMOS transistor 330_HS-SENSE) The proportional relationship (N) (i.e., the ratio) between them to perform PMOS sensing. The ratio (N) may be based on the channel width of the PMOS transistor for the high-side PMOS transistor 306 and the channel width of the PMOS transistor for the high-side sensing PMOS transistor 330, such that the ratio N-M_HS/M_HS-SENSE. The low side NMOS transistor 310 is coupled to a low side sense transistor 332 (M)_LS-SENSE). The low side sense transistor 332 is an NMOS transistor. The coupling between the low side NMOS transistor 310 and the low side sense NMOS transistor 332 is an example of NMOS sensing. May be based on leakage current (I) flowing through the low side NMOS transistor 310_LS) And the sense current (I) flowing through the low side sense NMOS transistor 332_LS-SENSE) The proportional relationship (M) (i.e., the ratio) between them. The ratio M may be based on the channel width of the NMOS transistor for the low side NMOS transistor 310 and the channel width of the NMOS transistor for the low side sense NMOS transistor 332, such that the ratio M-M_LS/M_LS-SENSE. The high side sense transistor 330 and the low side sense transistor 332 form a second current path. The drain of the high-side sense PMOS transistor 330 and the drain of the low-side sense NMOS transistor 332 at a node SW_LeakageAt 338 are coupled together. Sense current I through high side sense PMOS transistor 330_HS-SENSEAnd the sense current I through the low side sense NMOS transistor 332_LS-SENSEThe difference between them passes through the node SW_Leakage338 to the adaptive compensation circuit 328. The difference is proportional to the leakage current that will flow to the output stage 308. Alternatively, the sensing techniques described above (e.g., PMOS sensing, NMOS sensing) are not limited to PMOS transistors and NMOS transistors, but may be implemented with any type of transistor (e.g., PMOS transistors, NMOS transistors, BJTs, IGBTs, JFETs, etc.).

In the illustrated example of FIG. 3, the adaptive compensation circuit 328 is at node SW_LeakageAt 338 to the sensor 326. The adaptive compensation circuit 328 also operates on the high-side PMOS transistorThe connection between the drain of the transistor 306, the drain of the low side NMOS transistor 310, and the inductor 312 is coupled to the output stage 308. Alternatively, the adaptive compensation circuit 328 may be coupled to the output stage 308 of the power converter 300 at the positive terminal of the capacitor 314. Adaptive compensation circuit 328 via node SW_Leakage338 receives the differential current (I) from sensor 326_DIFF). The adaptive compensation circuit 328 is set in a current mirror configuration such that the reference MOSFET 334 (M)_REF) And a mirror MOSFET 336 (M)_Mirror) Forming a current mirror. Reference MOSFET 334 receives the difference current (I)_DIFF). The reference MOSFET 334 is coupled to the mirror MOSFET 336 at the gate of the reference MOSFET 334 and the gate of the mirror MOSFET 336. The adaptive compensation circuit 328 generates a compensation current (I) that flows from the output stage 308 to the mirror MOSFET 336_COMP). Differential current (I)_DIFF) And a compensation current (I)_COMP) Is proportional based on the ratio (N), so the ratio N-M_Mirror/M_REF. The target ratio N is designed such that the compensation current (I)_COMP) Is the precise leakage current (I) flowing to the output stage 308_OS). Thus, the total leakage current (I) is removed from the output stage 308_OS). In order to ensure this compensation current (I)_COMP) And leakage current (I) to the output stage 308_OS) Likewise, the ratio between the sense MOSFET and the high-side PMOS and low-side NMOS MOSFETs and the ratio between the reference MOSFET 334 and the mirror MOSFET 336 must be as follows: n is more than or equal to N and more than or equal to M.

In the illustrated example of fig. 3, the high-side PMOS transistor 306 and the low-side NMOS transistor 310 may control the flow of current to the output stage 308. The high-side PMOS transistor 306 may be controlled by a control signal 320 applied to the gate of the high-side PMOS transistor 306. Further, the low side NMOS transistor 310 may be controlled by a control signal 322 applied to the gate of the low side NMOS transistor 310. When the high-side PMOS transistor 306 is on and the low-side NMOS transistor 310 is off, current flows from the input voltage node V_in302 to the output stage 308. When the high-side PMOS transistor 306 is on and the low-side NMOS transistor 310 is off, the current (I) flowing through the high-side PMOS transistor 306_HS) Is equal to the current (I) flowing through the output stage 308_OS) Of the amplitude of (c). At this pointIn one case, the current charges the inductor 312 and the capacitor 314 such that energy is stored in the inductor 312 in the form of a magnetic field and energy is stored in the capacitor 314 in the form of an electric field. When the high-side PMOS transistor 306 is off and the low-side NMOS transistor 310 is on, current flows between the low-side NMOS transistor 310 and the output stage 308. When the high-side PMOS transistor 306 is turned off and the low-side NMOS transistor 310 is turned on, the current (I) flowing through the output stage 308_OS) Is equal to the current (I) flowing through the low side NMOS transistor 310_LS) Of the amplitude of (c). In this case, the energy stored in the magnetic field of inductor 312 dissipates to produce a current flow, and the energy stored in the electric field of capacitor 314 is used to maintain output voltage node V_O318. The controller may be implemented to control the high-side transistor 306 and the low-side transistor 310 such that the two transistors alternate between the high-side transistor 306 being on and the low-side transistor 310 being off, and the high-side transistor 306 being off and the low-side transistor 310 being on. This can be done at a frequency and duty cycle determined by the controller so that the output voltage node V_OThe output voltage at (a) may be maintained at the desired output voltage and within a safe operating region of the power converter 300. When the high-side PMOS transistor 306 is off and the low-side NMOS transistor 310 is off, leakage current may be drawn from the input voltage V_in302 to the output stage 308 of the power converter 300. In this case, the high-side sensing PMOS transistor 330 will sense the leakage current (I) flowing through the high-side PMOS transistor 306_HS) And the low side sense NMOS transistor 332 will sense the leakage current (I) flowing through the low side NMOS transistor 310_LS). Sensing the current I_HS-SENSEAnd sensing the current I_LS-SENSEDifference current (I) between_DIFF) Will flow to adaptive compensation network 328, as will leakage current I_HSAnd leakage current I_LSThe difference between will flow to the output stage 308. When the high-side PMOS transistor 306 and the low-side NMOS transistor 310 are turned off, the leakage current I_HSAnd leakage current I_LSThe difference between is the current (I) flowing through the output stage 308_OS). The reference MOSFET 334 may receive the difference current as an input to the adaptive compensation circuit 328. Then, the adaptive compensation circuit 32 is crossed8, applying the difference current (I)_DIFF) From reference MOSFET 334 to mirror MOSFET 336. Mirror MOSFET 336 generates a compensation current (I)_COMP) The compensation current is then subtracted from the output stage 308, thereby eliminating the leakage current (I)_OS) The influence of (c).

The sensor 326 and adaptive compensation circuit 328 are active regardless of whether the high-side PMOS transistor 306 and the low-side NMOS transistor 310 are conducting. When the high-side PMOS transistor 306 and the low-side NMOS transistor 310 are in an OFF state, the compensation current (I)_COMP) Is such that leakage current (I) flows to the output stage 308_OS) Is fully compensated and at the output voltage node V_OThere is no resulting charging of the output voltage at 318. However, when the high-side PMOS transistor 306 and the low-side NMOS transistor 310 are used as a set of synchronous transistors, the current (I) is compensated_COMP) Is negligible and thus the power converter 300 operates as intended.

Fig. 4 is an example graph 400 of output voltage versus ambient temperature for the buck converter 100 of fig. 3. Graph 400 includes two curves: an output voltage 402 without leakage current compensation and a target output voltage 404 with leakage current compensation. The two curves 402, 404 are set with respect to the ambient temperature of the buck converter 100. The ambient temperature range is-50 ℃ to 200 ℃. The output voltage 402 without leakage current compensation ranges from about 0VDC to almost 30VDC with increasing ambient temperature. This is because the leakage current flows to the output stage of the buck converter 100. Without the adaptive compensation circuit 228, the voltage maintained by the capacitor 114 in the output stage would rise indefinitely and would cause power loss and possibly damage to the buck converter 100 or the application in which the buck converter 100 is used. The target output voltage 404 with leakage current compensation maintains a constant voltage of about 0VDC as the ambient temperature increases. This is due to the presence of the adaptive compensation circuit 228. This allows the leakage current to be withdrawn from the output stage of the buck converter 100 regardless of the ambient temperature. This saves power and prevents potential damage to the buck converter 100 or the application in which the buck converter 100 is used. Furthermore, only excessive leakage currents are compensated. This allows the output voltage to remain within regulation and provides a low output current to a connected load. In addition, with the presence of the adaptive compensation circuit 228, power conversion efficiency can be maximized over a wide load range.

Fig. 5 is an example graph 500 of output load current versus ambient temperature for the buck converter 100 of fig. 1. Graph 500 includes two curves: an output load current without leakage current compensation 502 and an output load current with leakage current compensation 504. The two curves 502, 504 are set relative to the ambient temperature of the buck converter 100. The ambient temperature ranges from-50 ℃ to 200 ℃ as the ambient temperature increases. The output load current 502 without leakage current compensation ranges from about 0 μ A to almost 3 μ A. This is because the leakage current flows to the output stage of the buck converter 100. Without the adaptive compensation circuit 228, the leakage current flowing through the high-side PMOS transistor 106 and the low-side NMOS transistor 110 would increase indefinitely and would cause power loss and possibly damage to the buck converter 100 or the application in which the buck converter 100 is used. The output load current 504 with leakage current compensation maintains a constant current of approximately 0 μ Α. This is due to the presence of the adaptive compensation circuit 228. This allows the leakage current to be withdrawn from the output stage of the buck converter 100 regardless of the ambient temperature. This saves power and prevents potential damage to the buck converter 100 or the application in which the buck converter 100 is used. Furthermore, only excessive leakage currents are compensated. This allows the output voltage of the buck converter to remain within the regulation range and provide a lower output current to the connected load. In addition, with the presence of the adaptive compensation circuit 228, power conversion efficiency can be maximized over a wide load range.

Fig. 6 is an example graph 600 of efficiency versus load current for the buck converter 100 of fig. 1. The load current reflects the current flowing through the load connected to the buck converter 100. The graph 600 includes a first region 602, a second region 604, a third region 606, and a curve 608. In the graph 600, a first region 602 corresponds to the efficiency of the buck converter 100 at a load current of 1 μ Α using conventional compensation techniques. The second region 604 corresponds to the efficiency of the buck converter 100 at a load current of 10 μ Α using conventional compensation techniques. The third region 606 corresponds to the efficiency of the buck converter 100 at a load current of 1 μ Α using the adaptive compensation circuit of fig. 2. The efficiency at the first region 602 is approximately 50%, while the efficiency at the second region 604 is approximately 85%. The third region 606 has an efficiency of about 85%. The efficiency improvement seen on the graph between the first region 602 and the third region 606 is due to the use of the adaptive compensation circuit of fig. 2. Curve 608 corresponds to the efficiency curve of the buck converter 100 when the adaptive compensation circuit of fig. 2 is used. This allows for improved efficiency over a wide range of load values.

Although an example manner of implementing the adaptive compensation circuit of fig. 2 is shown in fig. 3, one or more of the elements, processes and/or devices shown in fig. 3 may be combined, divided, rearranged, omitted, eliminated and/or implemented in any other way. Further, the example sensor 226 and the example adaptive compensation circuit 228 of fig. 2 may be implemented by hardware, software, firmware, and/or any combination of hardware, software, and/or firmware. Thus, for example, any of the example sensor 226 and the example adaptive compensation circuit 228 may be implemented by one or more analog or digital circuits, logic circuits, programmable processor(s), programmable controller(s), Graphics Processing Unit (GPU), digital signal processor(s) (DSP), application specific integrated circuit(s) (ASIC), programmable logic device(s) (PLD), and/or field programmable logic device(s) (FPLD). When reading any apparatus or system claims of this patent to encompass pure software and/or firmware implementations, at least one of the example sensor 226 and the example adaptive compensation circuit 228 is expressly defined herein to include a non-transitory computer-readable storage device or storage disk, such as a memory, a Digital Versatile Disk (DVD), a Compact Disk (CD), a blu-ray disk, etc., that contains the software and/or firmware. Still further, the example sensor 226 and the example adaptive compensation circuit 228 of FIG. 2 may include one or more elements, processes, and/or devices in addition to or in place of those shown in FIG. 3, and/or may include any or all of more than one of the illustrated elements, processes, and devices. As used herein, the phrase "communication" (including variations thereof) encompasses direct communication and/or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and/or constant communication, but additionally includes selective communication at regular intervals, scheduled intervals, aperiodic intervals, and/or one-time events.

A flowchart representative of example hardware logic, machine readable instructions, a hardware implemented state machine, and/or any combination thereof to implement the sensor 226 and adaptive compensation circuit 228 of fig. 2 is shown in fig. 7. The machine-readable instructions may be executable programs or portions of executable programs for execution by a computer processor, such as the processor 812 shown in the example processor platform 800 discussed below in connection with fig. 8. The program may be embodied in software stored in a non-transitory computer readable storage medium such as a CD-ROM, floppy disk, hard drive, DVD, blu-ray disk, or memory associated with the processor 812, but the entire program and/or parts thereof could alternatively be executed by a device other than the processor 812 and/or embodied in firmware or dedicated hardware. Further, although the example program is described with reference to the flowchart shown in FIG. 7, many other methods of implementing the example sensor 226 and the example adaptive compensation circuit 228 may alternatively be used. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., discrete and/or integrated analog and/or digital circuits, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuitry, etc.) configured to perform the corresponding operations without the execution of software or firmware.

As described above, the example process of fig. 7 may be implemented using executable instructions (e.g., computer and/or machine readable instructions) stored on a non-transitory computer and/or machine readable medium such as a hard disk drive, a flash memory, a read-only memory, a compact disk, a digital versatile disk, a cache, a random-access memory and/or any other storage device or storage disk in which information is stored for any duration (e.g., for extended periods of time, permanently, brief instances, for temporarily buffering, and/or for caching of the information). As used herein, the term "non-transitory computer-readable medium" is expressly defined to include any type of computer-readable storage device and/or storage disk and to exclude propagating signals and to exclude transmission media.

The terms "comprising" and "including" (and all forms and tenses thereof) are used herein as open-ended terms. Thus, whenever a claim recites "comprising" or "including" (e.g., comprising, including, included, including, having) in any form as a preface or in the recitation of any kind of claim, it should be understood that additional elements, terms, etc. may be present without departing from the scope of the corresponding claim or recitation. As used herein, the phrase "at least" when used as a transitional term, such as in the preamble of a claim, is open-ended in the same manner that the terms "comprising" and "including" are open-ended. The term "and/or" when used in the form of, for example, A, B and/or C, refers to any combination or subset of A, B, C: such as (1) only a, (2) only B, (3) only C, (4) a and B, (5) a and C, (6) B and C, and (7) a and B and C. As used in the context of describing structures, components, items, objects, and/or things, the phrase "at least one of a and B" is intended to mean an embodiment that includes any one of: (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and/or things, the phrase "at least one of a or B" is intended to mean an embodiment that includes any one of: (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. As used herein in the context of describing the execution or performance of processes, instructions, actions, activities, and/or steps, the phrase "at least one of a and B" is intended to mean an embodiment that includes any of the following: (1) at least A, (2) at least B and (3) at least A and at least B. Similarly, as used herein in the context of describing the execution or performance of processes, instructions, actions, activities, and/or steps, the phrase "at least one of a or B" is intended to mean an embodiment that includes any of the following: (1) at least A, (2) at least B and (3) at least A and at least B.

The routine of fig. 7 illustrates a process 700 for executing the sensor 226 and the adaptive compensation circuit 228 of fig. 2. The process 700 includes a block 702, which is the beginning of the process 700. Process 700 includes block 704, which is a block that may instruct a processor to measure a first current and a second current. The first current may be associated with the high-side PMOS transistor 206 and the second current may be associated with the low-side NMOS transistor 210. The sensor 326 is shown as an example hardware implementation of block 704. In an example hardware implementation, the high-side sensing PMOS transistor 330 senses the first current and the low-side sensing NMOS transistor 332 senses the second current.

The next block in the process 700 is block 706, which is a block that may instruct the processor to determine whether the difference between the first current and the second current is positive. If the processor finds that the current is not positive, process 700 returns to block 704. If the processor determines that the difference is positive, process 700 passes to block 708. Alternatively, block 706 may be implemented as hardware as opposed to software. As hardware, block 706 may be implemented as a coupling between sensor 326 and adaptive compensation circuit 328. This coupling allows compensation only when the difference current is positive.

The next block in process 700 is block 708, which is a block that may instruct the processor to generate a compensation current. The next block in the process 700 is block 710, which is a block that may instruct the processor to apply the compensation current generated from block 708 to the output stage 308 shown in fig. 3. Alternatively, block 708 and block 710 may be implemented as hardware. As a hardware implementation, block 708 may be implemented as an adaptive compensation circuit 328 that generates a compensation current. Additionally, block 710 may be implemented as a coupling between the adaptive compensation circuit 328 and the output stage 308. This coupling may allow the adaptive compensation circuit 328 to apply a compensation current to the output stage 308.

FIG. 8 is a block diagram configured to execute the instructions of FIG. 7 to implement the sensors 226 and 226 of FIG. 2A block diagram of an example processor platform 800 of the adaptive compensation circuit 228. The processor platform 800 may be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cell phone, a smart phone, such as an iPad), a mobile device^TMTablet, etc.), a Personal Digital Assistant (PDA), an internet appliance, a DVD player, a CD player, a digital video recorder, a blu-ray player, a game player, a personal video recorder, a set-top box, a headset or other wearable device, or any other type of computing device.

The processor platform 800 of the illustrated example includes a processor 812. The processor 812 of the illustrated example is hardware. For example, the processor 812 may be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. The hardware processor may be a semiconductor-based (e.g., silicon-based) device. In this example, the processor implements a sensor 226 and an adaptive compensation circuit 228.

The processor 812 of the illustrated example includes local memory 813 (e.g., a cache). The processor 812 of the illustrated example communicates with a main memory including a volatile memory 814 and a non-volatile memory 816 via a bus 818. The volatile memory 814 may be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM),

Dynamic random access memory

And/or any other type of random access memory device. The non-volatile memory 816 may be implemented by flash memory and/or any other desired type of storage device. Access to the main memory 814, 816 is controlled by a memory controller.

The processor platform 800 of the illustrated example also includes an interface circuit 820. The interface circuit 820 may be implemented via, for example, an Ethernet interface, a Universal Serial Bus (USB),Any type of interface standard implementation of an interface, a Near Field Communication (NFC) interface, and/or a PCI Express interface.

In the example shown, one or more input devices 822 are connected to the interface circuit 820. Input device(s) 822 allow a user to enter data and/or commands into the processor 812. The input device(s) may be implemented by, for example, audio sensors, microphones, cameras (still or video), keyboards, buttons, mice, touch screens, track pads, track balls, etc., and/or voice recognition systems.

One or more output devices 824 are also connected to the interface circuit 820 of the illustrated example. The output devices 824 may be implemented, for example, by display devices (e.g., Light Emitting Diodes (LEDs), Organic Light Emitting Diodes (OLEDs), Liquid Crystal Displays (LCDs), cathode ray tube displays (CRTs), in-situ switching (IPS) displays, touch screens, etc.), tactile output devices, printers, and/or speakers. Thus, the interface circuit 820 of the illustrated example generally includes a graphics driver card, a graphics driver chip, and/or a graphics driver processor.

The interface circuit 820 of the illustrated example also includes communication devices such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and/or network interfaces to facilitate the exchange of data with external machines (e.g., any kind of computing device) via the network 826. The communication may be via, for example, an ethernet connection, a Digital Subscriber Line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a landline wireless system, a cellular telephone system, or the like.

The processor platform 800 of the illustrated example also includes one or more mass storage devices 828 for storing software and/or data. Examples of such mass storage devices 828 include floppy disk drives, hard disk drives, optical disk drives, blu-ray disk drives, Redundant Array of Independent Disks (RAID) systems, and Digital Versatile Disk (DVD) drives.

The machine-executable instructions 832 of fig. 6 may be stored in the mass storage device 828, in the volatile memory 814, in the non-volatile memory 816, and/or on a removable non-transitory computer readable storage medium such as a CD or DVD.

In light of the foregoing, it will be appreciated that example methods, apparatus, and articles of manufacture have been disclosed that allow power converters in low quiescent current applications to have improved efficiency. The adaptive compensation circuit 328 allows for complete compensation of leakage current flowing to the output stage 308 of the power converter 300. The previous compensation does not fully compensate for the leakage current to the output stage 308 and uses a worst case compensation current that negatively impacts the efficiency of the power converter. Furthermore, because the previous compensation mirrored the leakage current directly from the sensing device to the output voltage, the previous compensation did not fully compensate for the leakage current through the output stage 308. As a complete solution, the adaptive compensation circuit 328 fully compensates for leakage current through the output stage 308. The present disclosure provides a complete solution for maintaining the output voltage of a power converter within a desired value and maintaining a low output current connected to a load, thereby improving the efficiency of the power converter in low quiescent current applications. The presence of the adaptive compensation circuit 328 allows for improved power conversion efficiency over a wide load range. The disclosed methods, apparatus, and articles of manufacture improve the efficiency of using a computing device by adaptively removing leakage current from an output stage of a power converter. This improves the efficiency of the power converter in which the invention is implemented, as well as the overall application itself. The leakage current is removed from the output stage only in the idle state of the power converter. Accordingly, the disclosed methods, apparatus, and articles of manufacture involve one or more improvements in computer functionality.

Patent application No. us62/632,255 filed on 2018, 2/19 is incorporated herein by reference in its entirety.

Modifications in the described embodiments are possible within the scope of the claims, and other embodiments are possible.