阅读说明：本技术 固态多开关器件 (Solid state multi-switch device ) 是由 C·S·那慕杜理 R·普拉萨德 于 2021-03-16 设计创作，主要内容包括：一种固态开关组件,包括基板和固定到基板的电绝缘层。第一、第二、第三和第四功率迹线被固定到电绝缘层。第一半导体器件布置在第一功率迹线上以控制第一功率迹线和第二功率迹线之间的功率流,第二半导体器件布置在第二功率迹线上以控制第二功率迹线和第三功率迹线之间的功率流,并且第三半导体器件布置在第三功率迹线上以控制第三和第四功率迹线之间的功率流。第一信号导体与第一半导体器件通信。第二信号导体与第二半导体器件通信。第三信号导体与第三半导体器件通信。(A solid state switch assembly includes a substrate and an electrically insulating layer secured to the substrate. The first, second, third and fourth power traces are secured to the electrically insulating layer. A first semiconductor device is disposed on the first power trace to control power flow between the first power trace and the second power trace, a second semiconductor device is disposed on the second power trace to control power flow between the second power trace and the third power trace, and a third semiconductor device is disposed on the third power trace to control power flow between the third and fourth power traces. The first signal conductor is in communication with the first semiconductor device. The second signal conductor is in communication with the second semiconductor device. A third signal conductor is in communication with the third semiconductor device.)

1. An electronic solid state switch assembly comprising:

a substrate;

an electrically insulating layer secured to the substrate;

a first power trace secured to the electrically insulating layer, wherein the first power trace includes a positive power supply terminal;

a second power trace secured to the electrically insulating layer, wherein the second power trace includes a first power node;

a third power trace secured to the electrically insulating layer, wherein the third power trace includes a second power node;

a fourth power trace secured to the electrically insulating layer, wherein the fourth power trace includes a negative power supply terminal;

a first set of power semiconductor devices disposed on the first power trace to control power flow between the first power trace and the second power trace via a first plurality of electrical junctions;

a second group of power semiconductor devices disposed on the second power trace to control power flow between the second power trace and the third power trace via a second plurality of electrical junctions;

a third set of power semiconductor devices disposed on the third power trace to control power flow between the third power trace and the fourth power trace via a third plurality of electrical junctions;

a first signal conductor secured to the electrically insulating layer between the first and second power traces, wherein the first signal conductor is in communication with the first set of power semiconductor devices;

a second signal conductor secured to the electrically insulating layer between the second and third power traces, wherein the second signal conductor is in communication with the second set of power semiconductor devices; and

a third signal conductor secured to the electrically insulating layer between the third and fourth power traces, wherein the third signal conductor is in communication with the third set of power semiconductor devices.

2. The electronic solid state switch assembly of claim 1, wherein the first, second, third and fourth power traces comprise electrically isolated conductive planar elements on the substrate.

3. The electronic solid state switch assembly of claim 2, wherein the first, second, third and fourth power traces further comprise electrically conductive rectangular planar elements arranged in parallel and electrically isolated on the substrate.

4. The electronic solid state switch assembly of claim 2, wherein the electrically conductive planar elements of the first, second, third and fourth power traces are made of a metallic material selected from the group consisting of: copper, aluminum, and alloys thereof.

5. The electronic solid state switch assembly as claimed in claim 1 wherein said electrically insulating layer is thermally conductive.

6. The electronic solid state switch assembly of claim 1, further comprising a heat sink thermally connected to the substrate.

7. The electronic solid state switch assembly of claim 1, wherein each power semiconductor device of the first, second, and third sets of power semiconductor devices is configured to block power of at least a magnitude of 650 volts to 1200 volts.

8. The electronic solid state switch assembly of claim 1, wherein the electronic solid state switch assembly is configured to: when controlled to a conductive state, at least 400 amps of direct current is continuously delivered at a voltage drop of less than 1 volt.

9. The electronic solid state switch assembly of claim 1, wherein the substrate is between two and three millimeters thick, a first set of power semiconductor devices disposed on the first power trace are electrically connected in parallel with each other, a second set of power semiconductor devices disposed on the second power trace are electrically connected in parallel with each other, and a third set of power semiconductor devices disposed on the third power trace are electrically connected in parallel with each other.

10. The electronic solid state switch assembly of claim 1, further comprising a solder layer disposed between the substrate and the electrically insulating layer, wherein the electrically insulating layer comprises a ceramic material, and wherein the substrate comprises copper.

Background

On-board battery systems may employ multiple battery packs arranged to supply high voltage DC power to the electrified powertrain. The battery packs may be arranged in parallel to supply power to the electrified powertrain for operation, and arranged in series during recharging.

Existing gate driver circuits are designed for inverter applications, are high power consuming, bulky, and not suitable for integration into solid state switches. If the power supply has significant inductance, the solid state switch cannot absorb high energy during turn-off under short circuit or overload conditions. Therefore, there is a need to develop low power consumption and compact gate drivers and protection circuits for solid state switches. Further, there is a need for a switching device that is capable of delivering electrical power for operation and charging of an electrified powertrain, that is compact in size, lightweight, capable of managing temperature, has fast switching speeds, and is quiet.

Disclosure of Invention

The concepts described herein relate to electronic solid state switch assemblies, including electronic solid state switch assemblies that may be employed in high voltage battery systems that include multiple battery packs. The disclosed switch assembly is intended to be lightweight, fast in switching speed and quiet in operation. Further, the disclosed switching assembly may achieve one or more desired benefits, including continuous delivery of at least 400 amps of direct current with a voltage drop of less than 1 volt; expandable; have fast fault interrupting capability; with current limiting in the event of a fault; and has repeatability and reliability.

An electronic solid state switching assembly (multi-switch device) is described that includes a substrate and an electrically insulating layer secured to the substrate. A first power trace is secured to the electrically insulating layer, wherein the first power trace includes a positive power supply terminal; a second power trace secured to the electrically insulating layer, wherein the second power trace includes a first power node; a third power trace is secured to the electrically insulating layer, wherein the third power trace includes a second power node; and a fourth power trace is secured to the electrically insulating layer, wherein the fourth power trace includes a negative power supply terminal. A first set of power semiconductor devices is disposed on the first power trace to control power flow between the first power trace and the second power trace via the first plurality of electrical junctions, a second set of power semiconductor devices is disposed on the second power trace to control power flow between the second power trace and the third power trace via the second plurality of electrical junctions, and a third set of power semiconductor devices is disposed on the third power trace to control power flow between the third power trace and the fourth power trace via the third plurality of electrical junctions. A first signal conductor is secured to the electrically insulating layer between the first and second power traces, wherein the first signal conductor is in communication with the first set of power semiconductor devices. A second signal conductor is secured to the electrically insulating layer between the second and third power traces, wherein the second signal conductor is in communication with the second set of power semiconductor devices. A third signal conductor is secured to the electrically insulating layer between the third and fourth power traces, wherein the third signal conductor is in communication with the third set of power semiconductor devices.

Another aspect of the present disclosure includes: the first, second, third and fourth power traces are electrically isolated conductive planar elements on the substrate.

Another aspect of the present disclosure includes: the first, second, third and fourth power traces are electrically isolated electrically conductive rectangular planar elements arranged in parallel on the substrate.

Another aspect of the present disclosure includes: the conductive planar elements of the first, second, third and fourth power traces are made of a metallic material selected from the group consisting of copper, aluminum and alloys thereof.

Another aspect of the present disclosure includes: the electrically insulating layer is thermally conductive.

Another aspect of the present disclosure includes a heat sink thermally connected to the substrate.

Another aspect of the disclosure includes: each power semiconductor device is configured to block electrical power of a magnitude between 650 volts and 1200 volts.

Another aspect of the present disclosure includes an electronic solid state switch assembly configured to continuously deliver at least 400 amps of direct current at a voltage drop of less than 1 volt when controlled to a conductive state.

Another aspect of the disclosure includes the substrate having a thickness between two millimeters and three millimeters, and the plurality of semiconductor dies are electrically connected to each other in parallel.

Another aspect of the present disclosure includes a solder layer disposed between a substrate and an electrically insulating layer, wherein the electrically insulating layer comprises a ceramic material, and wherein the substrate comprises copper, aluminum, molybdenum, alloys thereof, or a thermally conductive metal matrix composite, such as AlSiC or copper graphite foam.

Another aspect of the present disclosure includes a conductive trace comprising a metallic material, wherein the metallic material is selected from the group consisting of copper, aluminum, and alloys thereof.

Another aspect of the present disclosure includes the first, second and third pluralities of power semiconductor devices being Metal Oxide Silicon Field Effect Transistors (MOSFETs).

Another aspect of the present disclosure includes an electronic solid state switch assembly including a substrate and an electrically insulating layer secured to the substrate. A first power trace is secured to the electrically insulating layer, wherein the first power trace includes a positive power supply terminal. A second power trace is secured to the electrically insulating layer, wherein the second power trace includes a first power node. A third power trace is secured to the electrically insulating layer, wherein the third power trace includes a second power node. A fourth power trace is secured to the electrically insulating layer, wherein the fourth power trace includes a third power node. A fifth power trace is secured to the electrically insulating layer, wherein the fifth power trace includes a negative power supply terminal. A first group of power semiconductor devices is disposed on the first power trace to control power flow between the first power trace and the second power trace via the first plurality of electrical junctions. A second group of power semiconductor devices is disposed on the second power trace to control power flow between the second power trace and the third power trace via the second plurality of electrical junctions. A third group of power semiconductor devices is disposed on the fourth power trace to control power flow between the third power trace and the fourth power trace via a third plurality of electrical junctions. A fourth set of power semiconductor devices is disposed on the fourth power trace to control power flow between the fourth power trace and the fifth power trace via a fourth plurality of electrical junctions. A first signal conductor is secured to the electrically insulating layer between the first and second power traces, wherein the first signal conductor is in communication with the first set of power semiconductor devices, and a second signal conductor is secured to the electrically insulating layer between the second and third power traces, wherein the second signal conductor is in communication with the second set of power semiconductor devices. A third signal conductor is secured to the electrically insulating layer between the third and fourth power traces, wherein the third signal conductor is in communication with the third set of power semiconductor devices. A fourth signal conductor is secured to the electrically insulating layer between the fourth and fifth power traces, wherein the fourth signal conductor is in communication with a fourth set of power semiconductor devices.

Another aspect of the present disclosure includes a reconfigurable battery system comprising: a high voltage bus comprising a positive high voltage bus and a negative high voltage bus; a first battery pack and a second battery pack electrically connected between the positive high voltage bus and the negative high voltage bus; and an electronic solid state switch assembly comprising: a first power trace including a positive power supply terminal, a second power trace including a first power node, a third power trace including a second power node, and a fourth power trace including a negative power supply terminal. A positive power terminal of the electronic solid state switch assembly is electrically connected to the positive high voltage bus. The first power node of the electronic solid state switching assembly is electrically connected to the anode of the first battery pack. The second power node of the electronic solid state switching assembly is electrically connected to the cathode of the second battery pack. A negative power terminal of the electronic solid state switch assembly is electrically connected to the negative high voltage bus. A cathode of the first battery pack is electrically connected to the negative high voltage bus. The anode of the second battery is electrically connected to the positive high voltage bus. The electronic solid state switch assembly includes a substrate, an electrically insulating layer secured to the substrate, a first set of power semiconductor devices arranged to control power flow between the first power trace and the second power trace, a second set of power semiconductor devices arranged to control power flow between the second power trace and the third power trace, and a third set of power semiconductor devices arranged to control power flow between the third power trace and the fourth power trace.

The invention provides the following technical scheme:

1. an electronic solid state switch assembly comprising:

a substrate;

an electrically insulating layer secured to the substrate;

a first power trace secured to the electrically insulating layer, wherein the first power trace includes a positive power supply terminal;

a second power trace secured to the electrically insulating layer, wherein the second power trace includes a first power node;

a third power trace secured to the electrically insulating layer, wherein the third power trace includes a second power node;

a fourth power trace secured to the electrically insulating layer, wherein the fourth power trace includes a negative power supply terminal;

a first set of power semiconductor devices disposed on the first power trace to control power flow between the first power trace and the second power trace via a first plurality of electrical junctions;

a second group of power semiconductor devices disposed on the second power trace to control power flow between the second power trace and the third power trace via a second plurality of electrical junctions;

a third set of power semiconductor devices disposed on the third power trace to control power flow between the third power trace and the fourth power trace via a third plurality of electrical junctions;

a first signal conductor secured to the electrically insulating layer between the first and second power traces, wherein the first signal conductor is in communication with the first set of power semiconductor devices;

a second signal conductor secured to the electrically insulating layer between the second and third power traces, wherein the second signal conductor is in communication with the second set of power semiconductor devices; and

a third signal conductor secured to the electrically insulating layer between the third and fourth power traces, wherein the third signal conductor is in communication with the third set of power semiconductor devices.

2. The electronic solid state switch assembly of claim 1 wherein the first, second, third and fourth power traces comprise electrically isolated conductive planar elements on the substrate.

3. The electronic solid state switch assembly of claim 2 wherein the first, second, third and fourth power traces further comprise electrically conductive rectangular planar elements arranged in parallel and electrically isolated on the substrate.

4. The electronic solid state switch assembly of claim 2 wherein the electrically conductive planar elements of the first, second, third and fourth power traces are made of a metallic material selected from the group consisting of: copper, aluminum, and alloys thereof.

5. The electronic solid state switch assembly as recited in claim 1, wherein the electrically insulating layer is thermally conductive.

6. The electronic solid state switch assembly of claim 1 further comprising a heat sink thermally coupled to the substrate.

7. The electronic solid state switch assembly of claim 1 wherein each power semiconductor device of the first, second and third groups of power semiconductor devices is configured to block power of at least 650 to 1200 volts magnitude.

8. The electronic solid state switch assembly of claim 1, wherein the electronic solid state switch assembly is configured to: when controlled to a conductive state, at least 400 amps of direct current is continuously delivered at a voltage drop of less than 1 volt.

9. The electronic solid state switch assembly of claim 1 wherein the substrate is between two and three millimeters thick, a first set of power semiconductor devices disposed on the first power trace are electrically connected in parallel with each other, a second set of power semiconductor devices disposed on the second power trace are electrically connected in parallel with each other, and a third set of power semiconductor devices disposed on the third power trace are electrically connected in parallel with each other.

10. The electronic solid state switch assembly of claim 1 further comprising a solder layer disposed between the substrate and the electrically insulating layer, wherein the electrically insulating layer comprises a ceramic material, and wherein the substrate comprises copper.

11. The electronic solid state switch assembly of claim 1 wherein the conductive trace comprises a metallic material selected from the group consisting of: copper, aluminum, and alloys thereof.

12. The electronic solid state switch assembly of claim 1 wherein the first, second and third groups of power semiconductor devices comprise metal oxide silicon field effect transistor devices (MOSFETs).

13. A reconfigurable battery system comprising:

a high voltage bus comprising a positive high voltage bus and a negative high voltage bus;

a first battery pack and a second battery pack electrically connected between the positive high voltage bus and the negative high voltage bus; and

an electronic solid state switch assembly comprising: a first power trace including a positive power supply terminal, a second power trace including a first power node, a third power trace including a second power node, and a fourth power trace including a negative power supply terminal;

wherein a positive power terminal of the electronic solid state switch assembly is electrically connected to the positive high voltage bus;

wherein the first power node of the electronic solid state switching assembly is electrically connected to the anode of the first battery pack;

wherein the second power node of the electronic solid state switching assembly is electrically connected to the cathode of the second battery pack;

wherein a negative power terminal of the electronic solid state switch assembly is electrically connected to the negative high voltage bus;

wherein a cathode of the first battery pack is electrically connected to the negative high voltage bus;

wherein the anode of the second battery is electrically connected to the positive high voltage bus; and is

Wherein the electronic solid state switch assembly comprises:

a substrate, a first electrode and a second electrode,

an electrically insulating layer secured to the substrate,

a first set of power semiconductor devices arranged to control power flow between the first power trace and the second power trace,

a second group of power semiconductor devices arranged to control power flow between the second power trace and the third power trace, an

A third set of power semiconductor devices arranged to control power flow between the third power trace and the fourth power trace.

14. The reconfigurable battery system according to claim 13, further comprising:

a first plurality of signal conductors secured to the electrically insulating layer;

a first plurality of electrical junctions electrically connecting the first plurality of signal conductors to the first set of power semiconductor devices;

a second plurality of signal conductors secured to the electrically insulating layer;

a second plurality of electrical junctions electrically connecting the second plurality of signal conductors to the second set of power semiconductor devices;

a third plurality of signal conductors secured to the electrically insulating layer; and

a third plurality of electrical junctions electrically connecting the third plurality of signal conductors to the third group of power semiconductor devices.

15. The reconfigurable battery system of claim 14 wherein the reconfigurable battery system is deployed to supply electrical power to an electrified powertrain system.

16. The reconfigurable battery system of claim 14 wherein the first, second, third, and fourth power traces comprise electrically isolated conductive planar elements on the substrate.

17. The reconfigurable battery system of claim 16 wherein the first, second, third and fourth power traces further comprise electrically conductive rectangular planar elements arranged in parallel and electrically isolated on the substrate.

18. The reconfigurable battery system of claim 17 wherein the electrically conductive planar elements of the first, second, third and fourth power traces are made of a metallic material selected from the group consisting of copper, aluminum and alloys thereof.

19. The reconfigurable battery system of claim 13 wherein each power semiconductor device in the first, second and third groups of power semiconductor devices is configured to block power of at least 650 to 1200 volts in magnitude.

20. An electronic solid state switch assembly comprising:

a substrate;

an electrically insulating layer secured to the substrate;

a first power trace secured to the electrically insulating layer, wherein the first power trace includes a positive power supply terminal;

a second power trace secured to the electrically insulating layer, wherein the second power trace includes a first power node;

a third power trace secured to the electrically insulating layer, wherein the third power trace includes a second power node;

a fourth power trace secured to the electrically insulating layer, wherein the third power trace includes a third power node;

a fifth power trace secured to the electrically insulating layer, wherein the fourth power trace includes a negative power supply terminal;

a first set of power semiconductor devices disposed on the first power trace to control power flow between the first power trace and the second power trace via a first plurality of electrical junctions;

a second group of power semiconductor devices disposed on the second power trace to control power flow between the second power trace and the third power trace via a second plurality of electrical junctions;

a third set of power semiconductor devices disposed on the third power trace to control power flow between the third power trace and the fourth power trace via a third plurality of electrical junctions;

a fourth set of power semiconductor devices disposed on the fourth power trace to control power flow between the fourth power trace and the fifth power trace via a fourth plurality of electrical junctions;

a first signal conductor secured to the electrically insulating layer between the first and second power traces, wherein the first signal conductor is in communication with the first set of power semiconductor devices;

a second signal conductor secured to the electrically insulating layer between the second and third power traces, wherein the second signal conductor is in communication with the second set of power semiconductor devices;

a third signal conductor secured to the electrically insulating layer between the third and fourth power traces, wherein the third signal conductor is in communication with the third set of power semiconductor devices; and

a fourth signal conductor secured to the electrically insulating layer between the fourth and fifth power traces, wherein the fourth signal conductor is in communication with the fourth set of power semiconductor devices.

The above features and advantages and other features and advantages of the present teachings are readily apparent from the following detailed description of some of the best modes and other embodiments for carrying out the present teachings when taken in connection with the accompanying drawings, as defined in the appended claims.

Drawings

Fig. 1 is a schematic diagram of a reconfigurable battery system including an electronic solid state switch assembly according to the present disclosure.

Fig. 2 is a schematic diagram of one embodiment of the electronic solid state switch assembly of fig. 1.

Fig. 3 is a schematic top view of one embodiment of the electronic solid state switch assembly of fig. 1.

Fig. 4 is a schematic diagram of a second embodiment of the electronic solid state switch assembly of fig. 1.

Fig. 5 is a schematic top view of a second embodiment of the electronic solid state switch assembly of fig. 1.

The accompanying drawings are not necessarily to scale and may present a somewhat simplified representation of various preferred features of the disclosure as disclosed herein, including, for example, particular sizes, orientations, positions, and shapes. The details associated with these features will be determined in part by the particular intended application and use environment.

Detailed Description

As described and illustrated herein, the components of the disclosed embodiments can be arranged and designed in a wide variety of different configurations. The following detailed description is, therefore, not to be taken in a limiting sense, but is made merely representative of possible embodiments of the claimed disclosure. Furthermore, although numerous specific details are set forth in the following description in order to provide a thorough understanding of the embodiments disclosed herein, some embodiments may be practiced without these details. Moreover, for the purpose of clarity, certain technical material that is understood in the related art has not been described in detail in order to avoid unnecessarily obscuring the present disclosure. For convenience and clarity only, directional terms, such as top, bottom, left side, right side, upper, above, below, rear and front, may be used with reference to the drawings. These and similar directional terms should not be construed to limit the scope of the present disclosure. Further, as shown and described herein, the present disclosure may be practiced without elements that are not specifically disclosed herein.

Embodiments of the disclosure may be described herein in terms of functional and/or logical block components and various processing steps. It should be appreciated that such block components may be realized by a plurality of hardware, software, and/or firmware components configured to perform the specified functions. For example, embodiments of the present disclosure may employ various integrated circuit components, e.g., memory elements, digital signal processing elements, logic elements, look-up tables, or the like, which may carry out a variety of functions under the control of one or more microprocessors or other control devices. Further, those skilled in the art will appreciate that embodiments of the present disclosure can be practiced in conjunction with a variety of systems, and that the systems described herein are merely exemplary embodiments of the disclosure.

For the sake of brevity, techniques related to signal processing, data fusion, signaling, control, and other functional aspects of the systems (and the individual operating components of the systems) may not be described in detail herein. Furthermore, the connecting lines shown in the various figures contained herein are intended to represent example functional relationships and/or physical couplings between the various elements. It should be noted that alternative or additional functional relationships or physical connections may be present in an embodiment of the disclosure.

Fig. 1 schematically illustrates a reconfigurable battery system 100 that includes a first battery pack 10, a second battery pack 20, and an embodiment of a DC electronic solid-state multi-switching device (multi-switching device) 40. Operation of the reconfigurable battery system 100 is monitored and controlled by the switch controller 45 and/or the vehicle charge controller 35. The reconfigurable battery system 100 is disposed between a positive high voltage bus (HV +) 32 and a negative high voltage bus (HV-) 34, which are elements of the high voltage bus 30. In one embodiment, the reconfigurable battery system 100 is deployed to supply electrical power to an electrified powertrain system of a vehicle. The positive high voltage bus (HV +) 32 and the negative high voltage bus (HV-) 34 are electrically connected to a DC power source (not shown) and may be electrically connected to a charging receptacle 36. First battery pack 10 and second battery pack 20 are configured as electrochemical devices that are rechargeable and capable of storing electrical energy, such as supercapacitors, batteries, battery cells, or any combination thereof.

The multi-switching device 40 is disposed between the first and second battery packs 10, 20. Multi-switch device 40 includes a plurality of switches, which in one embodiment include power semiconductor device S150, power semiconductor device S260, and power semiconductor device S370. The power semiconductor devices S150, S260 and S370 are arranged in series between a first power supply terminal 46 'and a second power supply terminal 49', interposing a first and a second power node 47 ', 48', respectively. In one embodiment, and as described herein, the first power supply terminal 46 'is connected to HV + 32, and the second power supply terminal 49' is connected to HV-34. The activation and deactivation of power semiconductor device S150, power semiconductor device S260, and power semiconductor device S370 is controlled by switch controller 45. The first power terminal 46' is electrically connected to the anode 22 of the second battery pack 20 and supplies power to the semiconductor device S150. The power semiconductor device S150 is arranged to electrically connect the first power supply terminal 46 'and the anode 12 of the first battery pack 10 at the first power node 47'. The power semiconductor device S370 is arranged to electrically connect the cathode 21 of the second battery pack 20 and the second power terminal 49 'at the second power node 48'. The power semiconductor device S260 is arranged to electrically connect the anode 12 of the first battery stack 10 and the cathode 21 of the second battery stack 20. The cathode 11 of the first battery pack 10 is electrically connected to the first power supply terminal 46 ', and the anode 22 of the second battery pack 20 is electrically connected to the first power supply terminal 46'.

Reconfigurable battery system 100 facilitates a first arrangement in which power semiconductor device S150 and power semiconductor device S370 are closed and power semiconductor device S260 is open, resulting in first and second battery packs 10, 20 being electrically connected in parallel between HV + 32 and HV-34. Reconfigurable battery system 100 facilitates a second arrangement in which power semiconductor device S150 and power semiconductor device S370 are open and power semiconductor device S260 is closed, resulting in first and second battery packs 10, 20 being electrically connected in series between HV + 32 and HV-34. This may facilitate a fast charging event. Reconfigurable battery system 100 facilitates a third arrangement where power semiconductor device S150 and power semiconductor device S260 are open and power semiconductor device S370 is closed, resulting in first battery pack 10 being isolated and taken offline and second battery pack 20 being electrically connected between HV + 32 and HV-34. This facilitates fault tolerant operation in the event of detection of a fault associated with the first battery pack 10. Reconfigurable battery system 100 facilitates a fourth arrangement where power semiconductor device S260 and power semiconductor device S370 are open and power semiconductor device S150 is closed, resulting in second battery pack 20 being isolated and taken off-line and first battery pack 10 being electrically connected between HV + 32 and HV-34. This facilitates fault tolerant operation in the event of a fault associated with the second battery pack 20 being detected.

Power semiconductor devices S150, S260 and S370 are low-loss switching devices. In the present disclosure, the term "low-loss switching device" refers to a solid-state relay having no moving parts; in contrast, solid state relays use the electrical and optical properties of solid state semiconductors to perform their input to output isolation and switching functions. By way of non-limiting example, solid state relays include MOS Controlled Thyristors (MCTs), gallium nitride (GaN) Field Effect Transistors (FETs), Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), silicon carbide junction field effect transistors (SiC JFETs), Insulated Gate Bipolar Transistors (IGBTs), or any other suitable low loss device having suitable voltage and current ratings.

The reconfigurable battery system 100 of the present disclosure provides flexible fast charging of the battery system, such as may be used on electrified vehicles (e.g., hybrid or electric vehicles). By employing a reconfigurable battery system 100, charging time can be minimized when connected to a high power Direct Current (DC) quick charging station (not shown). The voltage of the high power DC quick charging station may be 800 volts. The charging station includes a charging port capable of supplying DC voltage or Alternating Current (AC) voltage, or both, to the reconfigurable battery system 100 via the charging receptacle 36. The charging receptacle 36 is configured to receive a charging port to charge the reconfigurable battery system 100 and may receive AC charging power and/or DC charging power. Further, the charging receptacle 36 may be configured to communicate with a charging station either directly or through a charging port. In this way, the charging receptacle 36 may receive and transmit communication and port verification signals from the charging port.

Fig. 2 and 3 show the electrical arrangement and physical layout of multi-switching device 40, including power semiconductor device S150, power semiconductor device S260, and power semiconductor device S370, electrically connected in series between first power supply terminal 46 'and second power supply terminal 49'. When arranged as a MOSFET device, the power semiconductor device S150 includes a drain 51, a source 52, and a gate 53; the power semiconductor device S260 includes a drain electrode 61, a source electrode 62, and a gate electrode 63; and the power semiconductor device S370 includes a drain 71, a source 72, and a gate 73. The first power node 47 'is disposed between the power semiconductor device S150 and the power semiconductor device S260, and the second power node 48' is disposed between the power semiconductor device S260 and the power semiconductor device S370. In one embodiment, and as described with reference to fig. 1 and 2, power semiconductor device S150 is arranged to electrically connect HV + 32 and anode 12 of first battery stack 10 at first power node 47'. Power semiconductor device S370 is arranged to electrically connect cathode 21 of second battery stack 20 and HV-34 at second power node 48'. The power semiconductor device S260 is arranged to electrically connect the anode 12 of the first battery stack 10 and the cathode 21 of the second battery stack 20. The first power supply terminal 46 'is electrically connected to HV + 32 and the second power supply terminal 49' is electrically connected to HV-34.

The multi-switch device 40 is contained in a housing (not shown) that is configured to hold and encapsulate hardware and may be made in whole or in part of an electrically insulating and rigid material, such as a rigid polymeric material. Due to the configuration described herein, the mass of the multi-switching device 40 does not exceed 400 grams.

Referring to fig. 2 and 3, the multi-switching device 40 includes a substrate 41 having mounting holes on opposite sides of the substrate 41. The substrate 41 has a maximum thickness BT of between two and three millimeters to minimize the overall size of the multi-switching device 40. Furthermore, the substrate 41 has a substantially planar shape and is therefore of a flat configuration. Further, the substrate 41 may be made in whole or in part of a thermally conductive material, such as a metal or metal matrix composite. For example, the substrate 41 may be made in whole or in part of copper, aluminum, molybdenum, or alloys thereof, or metal matrix composites (such as AlSiC or copper graphite foam), and may be mounted to a heat sink. The substrate 41 may include optimally shaped pin fins (pin fin).

The multi-switching device 40 comprises an electrically insulating layer 42 provided on a substrate 41. In one embodiment, electrically insulating layer 42 is also thermally conductive. The electrically insulating layer 42 may be made in whole or in part of a ceramic or polymer material. Suitable ceramic materials for electrically insulating layer 42 include, but are not limited to, aluminum oxide (Al)₂O₃) Aluminum nitride (AlN), aluminum silicon carbide (AlSiC), silicon nitride (Si)₃N₄) Diamond, gallium oxide, and the like. The polymeric material may include mylar, Kapton, etc.

The multi-switch device 40 may include a solder layer (not shown) disposed between the substrate 41 and the electrically insulating layer 42 to connect the substrate 41 to the electrically insulating layer 42. The term "solder" refers to low melting point alloys, especially alloys based on lead and tin or (for higher temperatures) brass or silver, for joining metals that are less fusible. The solder layer is disposed directly on the substrate 41 to facilitate and enhance the connection between the solder layer and the substrate 41. Each of the substrate 41, the electrical insulation layer 42, and the solder layer has a planar shape to minimize the size coupled by the multi-switching device 40.

Multi-switch device 40 also includes a metal sheet (not shown) that is directly coupled to electrically insulating layer 42 to form a directly bonded substrate. The thickness of the directly bonded substrate is between 0.1 mm and 0.8 mm to minimize the size of the multi-switching device 40. The metal sheet may be bonded directly to the electrically insulating and thermally conductive layers to form a directly bonded substrate. The metal sheet may be made entirely or partially of copper and thus form a Directly Bonded Copper (DBC) substrate in conjunction with the electrically insulating layer 42. The metal sheet may be made in whole or in part of aluminum to form a Direct Bonded Aluminum (DBA) substrate in conjunction with the electrically insulating layer 42. The metal sheet may be directly attached to (and disposed directly on) the solder layer to enhance the structural integrity of the multi-switch device 40. In this way, the metal sheet is disposed on top of the electrically insulating layer 42 (e.g., ceramic layer). In other words, the metal sheet is bonded to the electrical insulation layer 42.

The multi-switch device 40 includes a first conductive trace (first power trace) 46, a second conductive trace (second power trace) 47, a third conductive trace (third power trace) 48, and a fourth conductive trace (fourth power trace) 49. The first power trace 46 includes a first power terminal 46 ', the second power trace 47 includes a first power node 47', the third power trace 48 includes a second power node 48 ', and the fourth power trace 49 includes a second power terminal 49'. The first power trace 46, the second power trace 47, the third power trace 48, and the fourth power trace 49 are disposed directly on the electrically insulating layer 42 to minimize the size occupied by the multi-switch device 40.

The first power trace 46, the second power trace 47, the third power trace 48, and the fourth power trace 49 are disposed directly on the electrically insulating layer 42 and are bonded or otherwise secured directly to the electrically insulating layer 42 to enhance the structural integrity of the multi-switch device 40. The first power trace 46, the second power trace 47, the third power trace 48, and the fourth power trace 49 each have a planar shape to minimize the size thereof. The first power trace 46, the second power trace 47, the third power trace 48, and the fourth power trace 49 are each made, in whole or in part, of a metallic material, such as copper or aluminum or an alloy thereof.

The multi-switch device 40 further includes a first gate signal conductor 56 and associated first gate signal terminal 56 ', a first source signal conductor 57 and associated first source signal terminal 57'; a second gate signal conductor 66 and associated second gate signal terminal 66 ', a second source signal conductor 67 and associated second source signal terminal 67'; a third gate signal conductor 76 and an associated third gate signal terminal 76 ', and a third source signal conductor 77 and an associated third source signal terminal 77'; all of which are disposed directly on the electrically insulating layer 42, made entirely or partially of a metallic material, such as copper or aluminum or alloys thereof, and bonded directly to the electrically insulating layer 42 (e.g., a ceramic layer).

The control input delivered through the signal conductors 56, 57, 66, 67, 76, 77 draws near zero power (i.e., less than 0.5 watts) to maintain the multi-switching device 40 in either an ON (ON) state or an OFF (OFF) state.

The multi-switch device 40 includes a plurality of power semiconductor devices including a first group of power semiconductor devices 50, a second group of power semiconductor devices 60, and a third group of power semiconductor devices 70. In one embodiment, each power semiconductor device is configured as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and includes a source terminal S, a gate terminal G, and a drain terminal D. This comprises a first group of power semiconductor devices 50, each power semiconductor device 50 having a source terminal S52, a gate terminal G53 and a drain terminal D51. This includes a second group of power semiconductor devices 60, each having a source terminal S62, a gate terminal G63 and a drain terminal D61. This includes a third group of power semiconductor devices 50, each power semiconductor device 50 having a source terminal S72, a gate terminal G73 and a drain terminal D71. In one embodiment, each power semiconductor device has a minimum area of 20 square millimeters to share and deliver 400 amps of current.

The first set of power semiconductor devices 50 is disposed directly on the first power trace 46 to facilitate or control current flow between the first power trace 46 and the second power trace 47 via the first electrical junction 55.

A second set of power semiconductor devices 60 is disposed directly on the second power trace 47 to facilitate or control current flow between the second power trace 47 and the third power trace 48 via a second electrical junction 65.

A third set of power semiconductor devices 70 is disposed directly on the third power trace 48 to facilitate or control current flow between the third power trace 48 and the fourth power trace 49 via a third electrical junction 75.

Each of the first, second and third electrical junctions 55, 65, 75 may be made of single or multiple high current aluminum or copper strip junctions or foil junctions to minimize parasitic inductance and resistance.

The depicted embodiment shows an amount of eight of the first set of power semiconductor devices 50 arranged in parallel, an amount of eight of the second set of power semiconductor devices 60 arranged in parallel, and an amount of eight of the third set of power semiconductor devices 70 arranged in parallel, the multi-switching devices 40 may each include between four and sixteen (each having a voltage rating from 650 to 1200 volts) to carry current, thereby enhancing scalability.

Each power semiconductor device includes a semiconductor material such as silicon, silicon carbide, gallium oxide and nitride, graphene or diamond.

The power semiconductor devices are arranged in a predetermined pattern to maintain substantially equal current and temperature profiles. The spacing and terminal position are selected to maintain substantially equal current and temperature distribution therebetween. In one embodiment, each power semiconductor device has less than 3.5 to 4.5 m- Ω cm²The specific on-resistance of. The placement of the power semiconductor devices and the pattern of the directly bonded substrate are selected to achieve equal current distribution and low parasitic inductance. The multi-switching device 40 may include a plurality of damping resistors, each damping resistor being electrically connected to the gate terminal of a respective one of the series-connected power semiconductor devices to prevent or at least minimize power oscillations. The power semiconductor devices are electrically connected in parallel to achieve a scalable current rating (e.g., a multiple of 100A), and the multi-switch device 40 includes an electrically insulating layer 42 (e.g., a ceramic layer) having a predetermined thermal stack height and pattern. For optimal thermal management, the pitch P between adjacent power semiconductor devices is greater than 1 mm and less than 3 mm. The term "pitch" refers to the distance between an edge of one of the power semiconductor devices and the nearest edge of an adjacent one of the power semiconductor devices.

The power semiconductor devices may be capable of blocking voltages DC between 650 volts and 1200 volts (e.g., at least 1200 volts) and may have different stack lengths. In this way, multi-switching device 40 is able to continue to deliver scalable current in the ON (ON) state with low ON (ON) state resistance. The multi-switch device 40 includes power semiconductor devices electrically connected in parallel for scalability with isolation resistance greater than 50 Mohm and minimum package size for different stack lengths. The electrically insulating layer 42 (e.g., a ceramic layer) may have a predetermined thermal stack height and pattern to provide a desired thermal capacity.

The gate terminal 53 of each first power semiconductor device 50 is electrically connected to the first gate signal terminal 56 'via a first gate signal conductor 56', the gate terminal 63 of each second power semiconductor device 60 is electrically connected to the second gate signal terminal 66 'via a second gate signal conductor 66, and the gate terminal 73 of each third power semiconductor device 70 is electrically connected to the third gate signal terminal 76' via a third gate signal conductor 76.

The first, second and third gate signal terminals 56 ', 66 ' and 76 ' are in communication with the switch controller 45 (shown with reference to fig. 1). The multi-switching device 40 may optionally include one or more thermistors (not shown) directly connected to the directly bonded substrate to measure the temperature of the multi-switching device 40.

The multi-switching device 40 has an OFF (OFF) state and an ON (ON) state. Due to its configuration, the multi-switching device 40 is capable of blocking at least 650 to 1200 volts in a single direction during the off state. Due to its configuration, the multi-switching device 40 continues to deliver at least 400 amps of direct current with a voltage drop of less than 1V during the on state. Due to its configuration, multi-switching device 40 may have a mass equal to or less than 400 grams and an on/off time of less than 10 microseconds. Due to its configuration, the multi-switching device 40 has a maximum width of 55 to 65 millimeters, a maximum length of 65 millimeters, and a maximum height of 25 millimeters, thereby minimizing the size of the multi-switching device 40. Due to this configuration, the multi-switching device 40 has an isolation resistance greater than 50 mega-ohms (M Ω). These concepts provide an architecture that includes a layout of power semiconductor devices in such a way that it functionally operates as three power semiconductor devices, but uses only a minimum of four power supply terminals under a single housing, thereby saving package space and cost.

Fig. 4 and 5 illustrate the electrical arrangement and physical layout of another embodiment of multi-switch device 140, including power semiconductor device S1150, power semiconductor device S2160, power semiconductor device S3170, and power semiconductor device S4180, electrically connected in series between first power supply terminal 146 'and second power supply terminal 143'. When arranged as a MOSFET device, the power semiconductor device S1150 includes a drain 151, a source 152, and a gate 153; power semiconductor device S2160 includes drain 161, source 162, and gate 163; the power semiconductor device S3170 includes a drain electrode 171, a source electrode 172, and a gate electrode 173, and the power semiconductor device S4180 includes a drain electrode 181, a source electrode 182, and a gate electrode 183. First power node 147 ' is disposed between power semiconductor device S1150 and power semiconductor device S2160, second power node 148 ' is disposed between power semiconductor device S2160 and power semiconductor device S3170, and third power node 149 ' is disposed between power semiconductor device S3170 and power semiconductor device S4180.

When the multi-switching device 140 is applied to the reconfigurable battery system 100 described with reference to fig. 1 and 4, the power transistor S1150 is arranged to electrically connect the HV + 32 and the anode 12 of the first battery pack 10 at the first power node 147'. Power transistor S4180 is arranged to electrically connect cathode 21 of second battery pack 20 and HV-34 at third power node 149'. Power transistor S2160 and power transistor S3170 are arranged to electrically connect anode 12 of first battery stack 10 and cathode 21 of second battery stack 20. The first power terminal 146 'is electrically connected to HV + 32, and the second power terminal 143' is electrically connected to HV-34.

This arrangement provides bidirectional current blocking via power semiconductor devices S2160 and S3170 during series charging of first and second battery packs 10 and 20.

The multi-switch device 140 is contained in a housing (not shown) that is configured to hold and encapsulate hardware and may be made in whole or in part of an electrically insulating and rigid material, such as a rigid polymeric material.

Referring again to fig. 4 and 5, the multi-switching device 140 includes a substrate 141 having mounting holes on opposite sides thereof. The substrate 141 has a maximum thickness BT of between two and three millimeters to minimize the overall size of the multi-switching device 140. Further, the substrate 141 has a substantially planar shape, and thus has a flat configuration. Further, the substrate 141 may be made in whole or in part of a thermally conductive material, such as a metal or metal matrix composite. For example, the substrate 141 may be made in whole or in part of copper, aluminum, molybdenum, or alloys or metal matrix composites thereof, such as AlSiC or copper foam, and may be mounted to a heat sink. The base plate 141 may optimally have pin fins.

The multi-switching device 140 includes an electrically insulating layer 142 disposed on a substrate 141. In one embodiment, electrically insulating layer 142 is also thermally conductive. Electrically insulating layer 142 may be made in whole or in part of a ceramic material. Suitable ceramic materials for electrically insulating layer 142 include, but are not limited to, aluminum oxide (Al)₂O₃) Aluminum nitride (AlN), aluminum silicon carbide (AlSiC), silicon nitride (Si)₃N₄) Diamond, gallium oxide, and the like.

Multi-switch device 140 may include a solder layer (not shown) disposed between substrate 141 and electrically insulating layer 142 to connect substrate 141 to electrically insulating layer 142. The term "solder" refers to low melting point alloys, especially alloys based on lead and tin or (for higher temperatures) brass or silver, for joining metals that are less fusible. The solder layer is disposed directly on the substrate 141 to facilitate and enhance the connection between the solder layer and the substrate 141. Each of the substrate 141, the electrical insulation layer 142, and the solder layer has a planar shape to minimize the size coupled by the multi-switching device 140.

Multi-switch device 140 also includes a metal sheet (not shown) that is directly coupled to electrically insulating layer 142 to form a directly bonded substrate. The thickness of the directly bonded substrate is between 0.1 mm and 0.8 mm to minimize the size of the multi-switching device 140. The metal sheet may be bonded directly to the electrically insulating and thermally conductive layers to form a directly bonded substrate. The metal sheet may be made entirely or partially of copper and thus form a Directly Bonded Copper (DBC) substrate in conjunction with electrically insulating layer 142. The metal sheet may be made in whole or in part of aluminum to form a Direct Bonded Aluminum (DBA) substrate in conjunction with electrically insulating layer 142. The metal sheet may be directly coupled to (and disposed directly on) the solder layer to enhance the structural integrity of the multi-switch device 140. In this way, the metal sheet is disposed between the solder layer and the electrically insulating layer 142 (e.g., a ceramic layer). In other words, the metal sheet is sandwiched between the solder layer and the electrically insulating layer 142.

Multi-switch device 140 includes a first conductive trace (first power trace) 146, a second conductive trace (second power trace) 147, a third conductive trace (third power trace) 148, a fourth conductive trace (fourth power trace) 149, and a fifth conductive trace (fifth power trace) 143. First power trace 146 includes a first power terminal 146 ', second power trace 147 includes a first power node 147 ', third power trace 148 includes a second power node 148 ', fourth power trace 149 includes a third power node 149 ', and fifth power trace 143 includes a second power terminal 143 '. First power trace 146, second power trace 147, third power trace 148, fourth power trace 149, and fifth power trace 143 are disposed directly on electrically insulating layer 142 to minimize the size occupied by multi-switch device 140.

First power trace 146, second power trace 147, third power trace 148, fourth power trace 149, and fifth power trace 143 are disposed directly on electrically insulating layer 142 and are bonded or otherwise secured directly to electrically insulating layer 142 to enhance the structural integrity of multi-switch device 140. The first power trace 146, the second power trace 147, the third power trace 148, the fourth power trace 149, and the fifth power trace 143 each have a planar shape to minimize the size thereof. The first power trace 146, the second power trace 147, the third power trace 148, the fourth power trace 149, and the fifth power trace 143 are each made, in whole or in part, of a metallic material (e.g., copper or aluminum or alloys thereof).

Multi-switch device 140 further includes a first gate signal conductor 156 and associated first gate signal terminal 156 ', a first source signal conductor 157 and associated first source signal terminal 157'; a second gate signal conductor 166 and associated second gate signal terminal 166 ', a second source signal conductor 167 and associated second source signal terminal 167'; a third gate signal conductor 176 and an associated third gate signal terminal 176 ', and a third source signal conductor 177 and an associated third source signal terminal 177'; and a fourth gate signal conductor 186 and associated fourth gate signal terminal 186 ', a fourth source signal conductor 187 and associated fourth source signal terminal 187', all of which are disposed directly on electrically insulating layer 142, made in whole or in part of a metallic material, such as copper or aluminum, and bonded directly to electrically insulating layer 142 (e.g., a ceramic layer).

The control input delivered through the signal conductor 120 draws near zero power (i.e., less than 0.5 watts) to maintain the multi-switching device 140 in either an ON (ON) state or an OFF (OFF) state.

Multi-switch device 140 includes a plurality of power semiconductor devices including a first group of power semiconductor devices 150, a second group of power semiconductor devices 160, a third group of power semiconductor devices 170, and a fourth group of power semiconductor devices 180. In one embodiment, each power semiconductor device is configured as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and includes a source terminal S, a gate terminal G, and a drain terminal D. This comprises a first group of power semiconductor devices 150, each power semiconductor device 150 having a source terminal S152, a gate terminal G153 and a drain terminal D151. This includes a second group of power semiconductor devices 160, each power semiconductor device 160 having a source terminal S162, a gate terminal G163 and a drain terminal D161. This includes a third group of power semiconductor devices 150, each power semiconductor device 150 having a source terminal S172, a gate terminal G173 and a drain terminal D171. This includes a fourth group of power semiconductor devices 180, each power semiconductor device 180 having a source terminal S182, a gate terminal G183 and a drain terminal D181. In one embodiment, each power semiconductor device has a minimum area of 20 square millimeters to share and deliver 1400A of current.

The first set of power semiconductor devices 150 are disposed directly on the first power trace 146 to facilitate or control current flow between the first power trace 146 and the second power trace 147 via the first electrical junction 155.

A second group of power semiconductor devices 160 is disposed directly on the second power trace 147 to facilitate or control current flow between the second power trace 147 and the third power trace 148 via a second electrical junction 165.

A third set of power semiconductor devices 170 is disposed directly on the third power trace 148 to facilitate or control current flow between the third power trace 148 and the fourth power trace 149 via a third electrical junction 175.

Fourth set of power semiconductor devices 180 is disposed directly on fourth power trace 149 to facilitate or control current flow between fourth power trace 149 and fifth power trace 143 via fourth electrical junction 185.

Each of the first, second, third, and fourth electrical junctions 155, 165, 175, and 185 may be made of high current aluminum or copper tape junctions or foil junctions to minimize parasitic inductance and resistance.

The depicted embodiment shows an amount of eight of the first set of power semiconductor devices 150 arranged in parallel, an amount of eight of the second power semiconductor devices 160 arranged in parallel, an amount of eight of the third set of power semiconductor devices 170 arranged in parallel, and an amount of eight of the fourth set of power semiconductor devices 180 arranged in parallel, the multi-switching devices 140 may each include four to sixteen (each having a voltage rating from 650 volts to 1200 volts) to deliver current, thereby enhancing scalability.

These concepts provide an architecture that includes the layout of the power semiconductor devices in such a way that it functions as three power semiconductor devices, but requires a minimum of four terminals under a single housing, thereby saving package space and cost.

The detailed description and the drawings or figures are support and description for the present teachings, but the scope of the present teachings is limited only by the claims. While some of the best modes and other embodiments for carrying out the present teachings have been described in detail, various alternative designs and embodiments exist for practicing the present teachings as defined in the appended claims.