阅读说明：本技术 正负电极同侧的多结砷化镓太阳电池芯片及其制备方法 (Multi-junction gallium arsenide solar cell chip with positive electrode and negative electrode on same side and preparation method thereof ) 是由 肖祖峰 杜伟 杨文奕 丁杰 黄嘉敬 何键华 于 2020-06-11 设计创作，主要内容包括：本发明公开了一种正负电极同侧的多结砷化镓太阳电池芯片及其制备方法,在P型Ge衬底上用MOCVD方法形成外延多结电池结构后,采用化学腐蚀等方法形成沟槽,并对沟槽进行绝缘填充,进而用电子束蒸镀上金属电极,将电池受光面的负电极引到电池背面,使正、负电极同处于电池的背面。采用本发明制备的太阳电池芯片,可以免于在电池受光面进行电极焊接,降低了在受光面进行焊接的电池损伤及污染风险,提高封装良率；另外,可方便电池直接焊接在带有串并联电路设计的基板上,可降低在电池受光面进行焊接时,与电极焊接在一起的互联片易与电池侧壁接触而短路的风险,提高电池的可靠性。(The invention discloses a multijunction gallium arsenide solar cell chip with positive and negative electrodes on the same side and a preparation method thereof. The solar cell chip prepared by the invention can avoid electrode welding on the light receiving surface of the cell, reduces the damage and pollution risks of the cell welded on the light receiving surface and improves the packaging yield; in addition, the battery can be conveniently and directly welded on the substrate with the series-parallel circuit design, the risk that the interconnection sheet welded together with the electrode is easy to contact with the side wall of the battery to cause short circuit when the light receiving surface of the battery is welded can be reduced, and the reliability of the battery is improved.)

1. Multijunction gallium arsenide solar cell chip of positive negative electrode homonymy, including Ge substrate (2), its characterized in that: the Ge substrate (2) is provided with a groove, the groove is filled in an insulating way, so that a permanent insulating part (7) of a battery is formed in the groove, the Ge substrate (2) is divided into two independent insulating parts, namely a first Ge substrate part and a second Ge substrate part, a first electrode (1) and a second electrode (6) which are independent of each other are prepared on the back surface of the Ge substrate (2) and are used as a positive electrode and a negative electrode, the first electrode (1) and the second electrode (6) correspond to the two independent insulating parts of the Ge substrate (2), namely the first electrode (1) is positioned on the first Ge substrate part, the second electrode (6) is positioned on the second Ge substrate part, a first insulating medium (5) is prepared between the first electrode (1) and the second electrode (6), the first insulating medium (5) is positioned on the bottom of the permanent insulating part (7) of the battery, an epitaxial layer (3) is prepared on the front surface of the first Ge substrate part, a second insulating medium (8) is prepared on the top of the insulating part (7) and the side wall of the epitaxial layer (3) close to the insulating part (7), a third electrode (9) and a metal grid line (10) which are interconnected are prepared on the top of the epitaxial layer (3) and the top of the second insulating medium (8), the third electrode (9) and the metal grid line (10) are in contact with the second Ge substrate part to realize communication with the second electrode (6), namely communication with a negative electrode, the epitaxial layer (3) comprises a window layer and a cap layer which are overlapped, the third electrode (9) and the metal grid line (10) are in contact with the cap layer, and the cap layer except the third electrode (9) and the metal grid line (10) is etched off by adopting a selective etching method to expose the window layer and is formed on the window layer, And preparing an antireflection film layer (4) on the third electrode (9) and the metal grid line (10).

2. The multijunction gallium arsenide solar cell chip with positive and negative electrodes on the same side as claimed in claim 1, wherein: the Ge substrate (2) is a P-type Ge single crystal wafer, and the thickness of the P-type Ge single crystal wafer is 140-200 mu m.

3. The multijunction gallium arsenide solar cell chip with positive and negative electrodes on the same side as claimed in claim 1, wherein: the epitaxial layer (3) comprises an N-type GaInP nucleating layer (31), an N-type GaInAs buffer layer (32), a first tunneling junction (33), a GaInAs middle cell (34), a second tunneling junction (35), a GaInP top cell (36), an N-type AlInP window layer (37) and an N-type GaInAs cap layer (38) which are sequentially stacked according to a layered structure.

4. The multijunction gallium arsenide solar cell chip with positive and negative electrodes on the same side as claimed in claim 1, wherein: the first electrode (1) and the second electrode (6) are made of one or a combination of Au, Pt, Pd, Zn, Cu, Ag, Cr, Ti, Al and TiW alloy.

5. The multijunction gallium arsenide solar cell chip with positive and negative electrodes on the same side as claimed in claim 1, wherein: the insulating part (7) is cured at high temperature using SU8 photoresist.

6. The multijunction gallium arsenide solar cell chip with positive and negative electrodes on the same side as claimed in claim 1, wherein: the third electrode (9) and the metal grid line (10) are made of one or a combination of Au, Pt, Ge, Ni, Ag, Cu, Cr, Ti, Al, AuGe alloy, AuGeNi alloy and TiW alloy.

7. The multijunction gallium arsenide solar cell chip with positive and negative electrodes on the same side as claimed in claim 1, wherein: the first insulating medium (5) and the second insulating medium (8) are SiO₂Or Si₃N₄An insulating medium.

8. The multijunction gallium arsenide solar cell chip with positive and negative electrodes on the same side as claimed in claim 1, wherein: the antireflection film (4) is of a double-layer or three-layer structure and is made of TiO₂、SiO₂、Al₂O₃、Ta₂O₅、Ti₃O₅、ZnS、Si₃N₄Two or three of them are combined, and the thickness of each layer is 10 nm-1000 nm.

9. The method for preparing the multijunction gallium arsenide solar cell chip with the positive and negative electrodes on the same side as in any one of claims 1 to 8, comprising the following steps:

1) providing a Ge substrate (2), and epitaxially growing an N-type GaInP nucleating layer (31), a multi-junction cell, an N-type AlInP window layer (37) and an N-type GaInAs cap layer (38) which are sequentially overlapped layer by layer on the front surface of the Ge substrate by adopting an MOCVD technology to form an epitaxial layer (3);

2) preparing a first electrode (1) and a second electrode (6) on the back of the Ge substrate (2) by adopting a photoresist stripping technology;

3) preparing SiO between a first electrode (1) and a second electrode (6) by adopting a wet etching technology₂Or Si₃N₄An insulating medium which is a first insulating medium (5);

4) etching part of the epitaxial layer to the Ge substrate (2) by adopting a photoetching technology and an ICP (inductively coupled plasma) etching technology, and etching the N-type Ge on the Ge substrate by adopting a wet etching technology;

5) etching through part of the Ge substrate by adopting photoetching, wet etching and photoresist removing technologies to form a groove, wherein the groove is aligned to a first insulating medium (5) on the Ge substrate;

6) filling the groove with SU8 photoresist by using a photoetching technology, and carrying out high-temperature curing to form a permanent insulating part (7) of the battery;

7) preparing SiO on the side wall of the etched epitaxial layer and the top of the permanent insulating part (7) of the cell by adopting PECVD technology, photoetching and wet etching and photoresist removing technology₂Or Si₃N₄An insulating medium which is a second insulating medium (8);

8) preparing a third electrode (9) and a metal grid line (10) which are interconnected on the top of the epitaxial layer (3) and the top of the second insulating medium (8) by adopting a photoresist stripping technology, and directly contacting with the Ge substrate (2), thereby realizing the communication with a negative electrode on the back of the Ge substrate (2);

9) etching off the N-type GaInAs cap layer (38) outside the third electrode (9) and the metal grid line (10) by adopting a selective etching method to expose the N-type AlInP window layer (37);

10) plating an antireflection film (4) on the N-type AlInP window layer (37), the third electrode (9) and the metal grid line (10) by adopting an electron beam evaporation method to obtain a battery product;

11) and cutting the battery product by adopting a mechanical cutting or laser cutting method to form a complete and independent battery chip.

10. The method for preparing the multijunction gallium arsenide solar cell chip with the positive electrode and the negative electrode on the same side as the claim 9, wherein the method comprises the following steps: in the step 2), preparing a photoetching pattern on the back of the Ge substrate (2) by adopting negative photoresist, then evaporating metal, and forming a first electrode (1) and a second electrode (6) by a stripping and photoresist removing process after evaporation;

in the step 3), a layer of SiO is plated on the back of the Ge substrate (2) by PECVD₂Or Si₃N₄Insulating medium, and then forming a first insulating medium (5) between the first electrode (1) and the second electrode (6) by adopting photoetching, wet etching and photoresist removing technologies;

in the step 8), negative photoresist is adopted to prepare electrode and grid line patterns on the top of the epitaxial layer (3) and the second insulating medium (8), electron beam evaporation is adopted to plate metal, and then a stripping and stripping technology is adopted to form a third electrode (9) and a metal grid line (10) which are interconnected;

in the step 9), the third electrode (9) and the metal grid line (10) are used as masks, and an ammonia water and hydrogen peroxide solution are adopted for selective corrosion, so that the N-type GaInAs cap layer (38) outside the third electrode (9) and the metal grid line (10) is corroded away, and the N-type AlInP window layer (37) is exposed;

in the step 10), the antireflection film (4) completely covers the N-type AlInP window layer (37), the third electrode (9) and the metal grid line (10).

Technical Field

The invention relates to the technical field of solar cells, in particular to a multijunction gallium arsenide solar cell chip with positive and negative electrodes on the same side and a preparation method thereof.

Background

In the prior art, a multijunction gallium arsenide solar cell as a third-generation solar cell has the advantages of high conversion efficiency, good temperature characteristic, strong irradiation resistance, light weight and the like, and is widely applied to ground concentrating photovoltaic systems and space power systems at present.

The traditional preparation method of the three-junction gallium arsenide solar cell chip comprises the following steps: sequentially preparing an N-type GaInP nucleating layer, an N-type GaInAs buffer layer, a middle-bottom battery tunneling junction, a GaInAs sub-battery, a middle-top battery tunneling junction, a GaInP top battery, an N-type AlInP window layer and an N-type GaInAs cap layer on a P-type Ge substrate to form a complete structure of an epitaxial layer; and then manufacturing a positive electrode and a negative electrode on the back surface of the Ge substrate and the epitaxial layer respectively, and annealing to form good ohmic contact. Etching off the cap layer of the non-negative electrode area by a selective etching method; and finally, preparing the antireflection film by photoetching and electron beam evaporation methods, and exposing an electrode area for electrical property test and packaging welding. The solar cell with the structure and the preparation method thereof have the following defects:

1. a photoetching process is needed before evaporation of the antireflection film, the temperature is high during evaporation, and the requirement on the heat resistance of the photoresist is high;

2. the negative electrode on one side of the light receiving surface of the battery is not protected by an insulating medium, and in order to improve the reliability of the battery and facilitate welding, a noble metal Au is generally required to be used as the material of the uppermost layer of the electrode;

3. the positive electrode and the negative electrode of the battery are respectively positioned on one side of the back surface of the battery and one side of the light receiving surface of the battery, and when the negative electrode on the side of the light receiving surface of the battery is welded, the battery is easily damaged and polluted, and the performance and the appearance of the battery are influenced;

4. the welded negative electrode metal interconnection sheet has the risk of short circuit caused by contact with the side wall of the battery, and the reliability of the battery is influenced;

5. the positive electrode and the negative electrode of the battery are respectively positioned at two sides of the battery, so that the serial and parallel connection design of a plurality of batteries is not easy.

If a novel multijunction gallium arsenide solar cell structure can be designed, the defects are overcome, the packaging yield and reliability of the cell are undoubtedly improved, the design of a cell series-parallel connection packaging system is facilitated, and the method has important significance for the wide application of gallium arsenide solar cells in various energy demand fields.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a multijunction gallium arsenide solar cell chip with positive and negative electrodes on the same side and a preparation method thereof, wherein a negative electrode of a light receiving surface of a cell is led to the back of the cell, so that the positive electrode and the negative electrode are positioned on the back of the cell, electrode welding on the light receiving surface of the cell can be avoided, the damage and pollution risks of the cell welded on the light receiving surface are reduced, and the packaging yield is improved; in addition, the battery can be conveniently and directly welded on the substrate with the series-parallel circuit design, the risk that the interconnection sheet welded together with the electrode is easy to contact with the side wall of the battery to cause short circuit when the light receiving surface of the battery is welded can be reduced, and the reliability of the battery is improved.

In order to achieve the purpose, the technical scheme provided by the invention is as follows: the multijunction gallium arsenide solar cell chip with the positive electrode and the negative electrode on the same side comprises a Ge substrate, wherein a groove is formed in the Ge substrate, a permanent insulating part of a cell is formed in the groove by insulating and filling the groove, so that the Ge substrate is divided into two independent insulating parts which are a first Ge substrate part and a second Ge substrate part respectively, a first electrode and a second electrode which are independent from each other are prepared on the back surface of the Ge substrate and used as a positive electrode and a negative electrode, the first electrode and the second electrode correspond to the two independent insulating parts of the Ge substrate, namely the first electrode is positioned on the first Ge substrate part, the second electrode is positioned on the second Ge substrate part, a first insulating medium is prepared between the first electrode and the second electrode, the first insulating medium is positioned at the bottom of the permanent insulating part of the cell, and an epitaxial layer is prepared on the front surface of the first Ge substrate part, and a second insulating medium is prepared on the top of the insulating part and the side wall of the epitaxial layer close to the insulating part, a third electrode and a metal grid line which are interconnected are prepared on the top of the epitaxial layer and the second insulating medium, the third electrode and the metal grid line are communicated with the second electrode by contacting with a second Ge substrate part, namely communicated with the negative electrode, the epitaxial layer comprises a window layer and a cap layer which are superposed, the third electrode and the metal grid line are contacted with the cap layer, the cap layer except the third electrode and the metal grid line is corroded by adopting a selective corrosion method to expose the window layer, and an antireflection film layer is prepared on the window layer, the third electrode and the metal grid line.

Furthermore, the Ge substrate is a P-type Ge single crystal wafer, and the thickness of the Ge substrate is 140-200 mu m.

Further, the epitaxial layer comprises an N-type GaInP nucleating layer, an N-type GaInAs buffer layer, a first tunneling junction, a GaInAs middle battery, a second tunneling junction, a GaInP top battery, an N-type AlInP window layer and an N-type GaInAs cap layer which are sequentially stacked according to a layered structure.

Furthermore, the first electrode and the second electrode are made of one or a combination of more of Au, Pt, Pd, Zn, Cu, Ag, Cr, Ti, Al and TiW alloy.

Further, the insulating portion is cured at a high temperature using SU8 photoresist.

Furthermore, the third electrode and the metal grid line are made of one or a combination of more of Au, Pt, Ge, Ni, Ag, Cu, Cr, Ti, Al, AuGe alloy, AuGeNi alloy and TiW alloy.

Further, the first insulating medium and the second insulating medium are SiO₂Or Si₃N₄An insulating medium.

Further, the antireflection filmIs of a double-layer or triple-layer structure made of TiO₂、SiO₂、Al₂O₃、Ta₂O₅、Ti₃O₅、ZnS、Si₃N₄Two or three of them are combined, and the thickness of each layer is 10 nm-1000 nm.

The invention also provides a preparation method of the multijunction gallium arsenide solar cell chip with the positive electrode and the negative electrode on the same side, which comprises the following steps:

1) providing a Ge substrate, and epitaxially growing an N-type GaInP nucleating layer, a multi-junction cell, an N-type AlInP window layer and an N-type GaInAs cap layer which are sequentially overlapped layer by layer, which are mutually connected in series through a tunneling junction on the front surface of the Ge substrate by adopting an MOCVD technology to form an epitaxial layer;

2) preparing a first electrode and a second electrode on the back of the Ge substrate by adopting a photoresist stripping technology;

3) preparing SiO between a first electrode and a second electrode by adopting a wet etching technology₂Or Si₃N₄The insulating medium is a first insulating medium;

4) etching part of the epitaxial layer to the Ge substrate by adopting a photoetching technology and an ICP (inductively coupled plasma) etching technology, and etching the N-type Ge on the Ge substrate by adopting a wet etching technology;

5) etching a part of the Ge substrate through photoetching, wet etching and photoresist removing technologies to form a groove, wherein the groove is aligned to a first insulating medium on the Ge substrate;

6) filling the groove with SU8 photoresist by using a photoetching technology, and carrying out high-temperature curing to form a permanent insulating part of the battery;

7) preparing SiO on the side wall of the etched epitaxial layer and the top of the permanent insulating part of the cell by adopting PECVD technology, photoetching and wet etching and photoresist removing technology₂Or Si₃N₄The insulating medium is a second insulating medium;

8) preparing a third electrode and a metal grid line which are interconnected by adopting a photoresist stripping technology on the top of the epitaxial layer and the top of the second insulating medium, and directly contacting with the Ge substrate so as to realize the communication with the negative electrode on the back of the Ge substrate;

9) etching off the N-type GaInAs cap layer outside the third electrode and the metal grid line by adopting a selective etching method to expose the N-type AlInP window layer;

10) plating an antireflection film on the N-type AlInP window layer, the third electrode and the metal grid line by adopting an electron beam evaporation method to obtain a battery product;

11) and cutting the battery product by adopting a mechanical cutting or laser cutting method to form a complete and independent battery chip.

In the step 2), preparing a photoetching pattern on the back of the Ge substrate by adopting a negative photoresist, then evaporating metal, and forming a first electrode and a second electrode by a stripping and photoresist removing process after evaporation;

in the step 3), a layer of SiO is plated on the back of the Ge substrate by adopting PECVD₂Or Si₃N₄Forming a first insulating medium between the first electrode and the second electrode by adopting photoetching, wet etching and photoresist removing technologies;

in the step 8), negative photoresist is adopted on the top of the epitaxial layer and the second insulating medium to prepare electrode and grid line graphs, electron beam evaporation is adopted to plate metal, and then a stripping and photoresist removing technology is adopted to form a third electrode and a metal grid line which are interconnected;

in step 9), etching off the N-type GaInAs cap layer outside the third electrode and the metal gate line by using the third electrode and the metal gate line as masks and using ammonia water and hydrogen peroxide solution for selective etching to expose the N-type AlInP window layer;

in step 10), the antireflection film covers the N-type AlInP window layer, the third electrode, and the metal gate line.

Compared with the prior art, the invention has the following advantages and beneficial effects:

1. the positive electrode and the negative electrode of the battery chip are positioned on one side of the back surface of the battery, so that electrode welding on the light receiving surface of the battery can be avoided, the damage and pollution risks of the battery welded on the light receiving surface are reduced, and the packaging yield is improved.

2. The positive electrode and the negative electrode of the battery chip are positioned at the same side of the battery, and a plurality of batteries are easy to be designed in series-parallel connection to form a battery assembly and a power supply system.

3. The battery chip reduces the risk of short circuit caused by the contact of the welded negative electrode metal interconnection sheet and the side wall of the battery, and improves the reliability of the battery.

4. The negative electrode on one side of the light receiving surface of the battery can be used without adopting noble metal Au as the uppermost electrode material, so that the use of the noble metal Au is reduced, and the cost can be reduced.

5. The antireflection film disclosed by the invention is plated without adopting a photoetching technology and the requirement on a photoresist with high heat resistance, and is easier to manufacture.

Drawings

Fig. 1 is a schematic structural diagram of a multijunction gallium arsenide solar cell chip with positive and negative electrodes on the same side.

Fig. 2 is a schematic view of the structure of an epitaxial layer formed during fabrication.

Fig. 3 is a top view of the multijunction gaas solar cell chip with the positive and negative electrodes on the same side according to the present invention.

Fig. 4 is a back plan view of the multijunction gaas solar cell chip with the positive and negative electrodes on the same side according to the present invention.

Detailed Description

The present invention will be further described with reference to the following specific examples.

As shown in fig. 1 to 4, the present embodiment provides a multijunction gallium arsenide solar cell chip with positive and negative electrodes on the same side, which includes a Ge substrate 2, where the Ge substrate 2 is a P-type Ge single crystal wafer and has a thickness of 140 μm to 200 μm; the Ge substrate 2 is provided with a groove, the groove is filled with insulation, particularly SU8 photoresist is used for high-temperature curing, so that a permanent insulation part 7 of a battery is formed in the groove, the Ge substrate 2 is divided into two independent insulation parts, namely a first Ge substrate part and a second Ge substrate part, a first electrode 1 and a second electrode 6 which are independent of each other are prepared on the back surface of the Ge substrate 2 and are used as a positive electrode and a negative electrode, the first electrode 1 and the second electrode 6 correspond to the two independent insulation parts of the Ge substrate 2, namely the first electrode 1 is positioned on the first Ge substrate part, the second electrode 6 is positioned on the second Ge substrate part, a first insulation medium 5 is prepared between the first electrode 1 and the second electrode 6, the first insulation medium 5 is positioned at the bottom of the permanent insulation part 7 of the battery, and an epitaxial layer 3 is prepared on the front surface of the first Ge substrate part, a second insulating medium 8 is prepared on the top of the insulating part 7 and the side wall of the epitaxial layer 3 close to the insulating part 7, a third electrode 9 and a metal grid line 10 which are interconnected are prepared on the top of the epitaxial layer 3 and the top of the second insulating medium 8, and the third electrode 9 and the metal grid line 10 are in contact with the second Ge substrate part to realize communication with the second electrode 6, namely communication with a negative electrode; the epitaxial layer 3 comprises an N-type GaInP nucleating layer 31, an N-type GaInAs buffer layer 32, a first tunneling junction 33, a GaInAs middle cell 34, a second tunneling junction 35, a GaInP top cell 36, an N-type AlInP window layer 37 and an N-type GaInAs cap layer 38 which are sequentially stacked according to a layered structure, the third electrode 9 and the metal grid line 10 are in contact with the N-type GaInAs cap layer 38, the N-type GaInAs cap layer 38 outside the third electrode 9 and the metal grid line 10 is etched away by adopting a selective etching method to expose the N-type GaInP window layer 37, and the antireflection film layer 4 is prepared on the N-type GaInP window layer 37, the third electrode 9 and the metal grid line 10.

The first electrode 1 and the second electrode 6 are made of one or a combination of Au, Pt, Pd, Zn, Cu, Ag, Cr, Ti, Al and TiW alloy.

The third electrode 9 and the metal grid line 10 are made of one or a combination of more of Au, Pt, Ge, Ni, Ag, Cu, Cr, Ti, Al, AuGe alloy, AuGeNi alloy and TiW alloy.

The first insulating medium 5 and the second insulating medium 8 are SiO₂Or Si₃N₄An insulating medium.

The antireflection film 4 is of a double-layer or three-layer structure and is made of TiO₂、SiO₂、Al₂O₃、Ta₂O₅、Ti₃O₅、ZnS、Si₃N₄Two or three of them are combined, and the thickness of each layer is 10 nm-1000 nm.

The embodiment also provides a preparation method of the multijunction gallium arsenide solar cell chip with the positive electrode and the negative electrode on the same side, which comprises the following steps:

step 1: providing a Ge substrate 2 which is a P-type Ge single crystal wafer, and epitaxially growing an N-type GaInP nucleating layer 31, an N-type GaInAs buffer layer 32, a first tunneling junction 33, a GaInAs middle cell 34, a second tunneling junction 35, a GaInP top cell 36, an N-type AlInP window layer 37 and an N-type GaInAs cap layer 38 which are sequentially overlapped layer by layer on the front surface of the Ge substrate 2 by adopting an MOCVD technology to form an epitaxial layer 3.

Step 2: and preparing a photoetching pattern on the back of the Ge substrate by adopting negative photoresist, then sequentially evaporating and plating metal Ti and Au, and forming a first electrode 1 and a second electrode 6 by a stripping and photoresist removing process after evaporation.

And step 3: plating a layer of SiO on the back of the Ge substrate 2 by adopting PECVD₂Then, photoetching, wet etching and photoresist removing technologies are adopted to form SiO between the first electrode 1 and the second electrode 6₂The insulating medium is a first insulating medium 5.

And 4, step 4: etching part of the epitaxial layer to the Ge substrate 2 by adopting a photoetching technology and an ICP (inductively coupled plasma) etching technology, and leaving an epitaxial layer 3 shown in figure 2; and adopting a wet etching process to continuously etch off the N-type Ge part on the Ge substrate 2 and then removing the photoresist.

And 5: and etching a part of the Ge substrate by adopting photoetching, wet etching and photoresist removing technologies to form a groove, wherein the groove is aligned to the first insulating medium 5 on the Ge substrate.

Step 6: the trenches were filled with SU8 photoresist using photolithography and cured at a high temperature of 200 c to form the permanent insulating portion 7 of the cell.

And 7: preparing SiO on the side wall of the etched epitaxial layer and the top of the permanent insulating part 7 of the cell by adopting PECVD technology, photoetching and wet etching and photoresist removing technology₂And the insulating medium is a second insulating medium 8.

And 8: and preparing electrode and grid line patterns on the top of the epitaxial layer 3 and the second insulating medium 8 by adopting negative photoresist, evaporating AuGeNi, Ag and TiW in sequence by adopting electron beam evaporation, and then forming a third electrode 9 and a metal grid line 10 which are interconnected by a stripping and photoresist removing technology.

And step 9: and etching off the N-type GaInAs cap layer 38 outside the third electrode 9 and the metal grid line 10 by using ammonia water and hydrogen peroxide solution for selective etching by using the third electrode 9 and the metal grid line 10 as masks to expose the N-type AlInP window layer 37.

Step 10: TiO is plated on the N-type AlInP window layer 37, the third electrode 9 and the metal grid line 10 by adopting an electron beam evaporation method₂And SiO₂And forming the antireflection film 4 to obtain a battery product.

Step 11: and cutting the battery product by adopting a mechanical cutting or laser cutting method to form a complete and independent battery chip.

The above-mentioned embodiments are merely preferred embodiments of the present invention, and the scope of the present invention is not limited thereto, so that the changes in the shape and principle of the present invention should be covered within the protection scope of the present invention.