阅读说明：本技术 一种模拟故障相位控制装置 (Phase control device for simulating fault ) 是由 林永清 于 2019-03-22 设计创作，主要内容包括：本发明涉及电力动态模拟系统技术领域,且公开了一种模拟故障相位控制装置,包括装置机体和固定设置在装置机体内部的处理器,处理器的内部固定设有主板,主板的上端固定设有捕获模块、定时计数器、内核、IO模块、AD采集模块、控制器、SPI模块及UART模块,捕获模块、定时计数器、内核、IO模块、AD采集模块、控制器、SPI模块及UART模块均通过导线与主板电性连接,处理器的外部设有信号整形模块。该模拟故障相位控制装置,装置模拟故障时,既可以模拟单次故障,也可以模拟周期性故障,并且在模拟周期性故障时,故障相位可以固定不变,也可以按设定参数,使合闸角度有规律的递增或递减,形成周期性故障,便于人们使用。(The invention relates to the technical field of electric power dynamic simulation systems, and discloses a simulated fault phase control device which comprises a device body and a processor fixedly arranged in the device body, wherein a mainboard is fixedly arranged in the processor, a capture module, a timing counter, an inner core, an IO module, an AD acquisition module, a controller, an SPI module and a UART module are fixedly arranged at the upper end of the mainboard, the capture module, the timing counter, the inner core, the IO module, the AD acquisition module, the controller, the SPI module and the UART module are electrically connected with the mainboard through wires, and a signal shaping module is arranged outside the processor. The phase control device for simulating the fault can simulate single fault and periodic fault when simulating the fault, and the fault phase can be fixed and unchanged when simulating the periodic fault, and the closing angle can be regularly increased or decreased according to set parameters to form the periodic fault, so that the phase control device is convenient for people to use.)

1. A phase control device for simulating a fault, comprising a device body (1) and a processor fixedly arranged inside the device body (1), characterized in that: the processor is characterized in that a mainboard is fixedly arranged inside the processor, a capturing module, a timing counter, an inner core, an IO module, an AD acquisition module, a controller, an SPI module and a UART module are fixedly arranged at the upper end of the mainboard, the capturing module, the timing counter, the inner core, the IO module, the AD acquisition module, the controller, the SPI module and the UART module are all electrically connected with the mainboard through wires, a signal shaping module is arranged outside the processor, the output end of the signal shaping module is electrically connected with the input end of the capturing module through a wire, the input end of the signal shaping module is electrically connected with a signal conditioning module through a wire, the input end of the signal conditioning module is electrically connected with a low-pass filter through a wire, the output end of the signal conditioning module is also electrically connected with the AD acquisition module through a wire, a first photoelectric isolating switch and a second photoelectric isolating switch are also arranged outside the processor, the output of first photoelectric isolator passes through the input electric connection of wire and IO module, the input of first photoelectric isolator has external trigger switch through wire electric connection, the input of second photoelectric isolator passes through the output electric connection of wire and IO module, photoelectric isolator's output has electronic switch through wire electric connection, electronic switch's output passes through wire electric connection trouble analog switch, the outside of treater still is equipped with serial Flash module and external communication interface, serial Flash module passes through wire and SPI module electric connection, external interface module passes through wire and UART module electric connection.

2. A simulated fault phase control apparatus as claimed in claim 1, wherein: the input end of the low-pass filter is electrically connected with two paths of switching-on reference voltages, a first input panel (2) and a second input panel (3) are fixedly arranged on the surface of the device body (1), and the first input panel (2) and the second input panel (3) are respectively electrically connected with the two paths of switching-on reference voltages.

3. A simulated fault phase control apparatus as claimed in claim 1, wherein: the surface of the device body (1) is fixedly provided with a display terminal (4), and the input end of the display terminal (4) is electrically connected with the output end of the UART module through a wire.

4. A simulated fault phase control apparatus as claimed in claim 1, wherein: the surface fixing of device organism (1) is equipped with start button (5) and stop button (6), start button (5) and stop button (6) all with low pass filter's input electric connection.

5. A simulated fault phase control apparatus as claimed in claim 1, wherein: the device body (1) is fixedly provided with an RS485 communication interface (7) and an Ethernet communication interface (8) on the side wall, and the RS485 communication interface (7) and the Ethernet communication interface (8) both support Modbus, 101 or 104 protocols.

6. A simulated fault phase control apparatus as claimed in claim 1, wherein: the range of the simulation action phase theta of the device body (1) is 0-360 degrees, and the set range of the outlet pulse width tm of the device body (1) is 5-5000 ms.

7. A simulated fault phase control apparatus as claimed in claim 1, wherein: a plurality of switch outlets are fixedly arranged outside the device body (1), wherein 1-4 switch outlets are high-power electric linkage contactless output interfaces (9).

Technical Field

The invention relates to the technical field of electric power dynamic simulation systems, in particular to a simulated fault phase control device.

Background

With the daily promotion and the comprehensive development of the construction of the electricity utilization information acquisition system, the types and the number of the field acquisition terminals and the meters are continuously increased, and the problems and the faults of a large number of different phenomena can be quickly and accurately solved in the process of construction and operation maintenance.

The current line has faults under different phases, the faults of the current line comprise a three-phase current reverse phase sequence, a three-phase current reverse A, B, C phase, a three-phase current short circuit, an A-phase current short circuit, a B-phase current short circuit, a C-phase current short circuit, an A-phase current open circuit, a B-phase current open circuit and a C-phase current open circuit.

Disclosure of Invention

Technical problem to be solved

Aiming at the defects of the prior art, the invention provides a fault simulation phase control device which has the advantages of simulating single fault and various simulation obstacles such as periodic faults and the like, and solves the problems that the simulation mode of the fault simulation phase control device on the market is single and the requirements of practitioners cannot be met.

(II) technical scheme

In order to achieve the purpose of simulating single fault and periodic fault, the invention provides the following technical scheme: a phase control device for simulating faults comprises a device body and a processor fixedly arranged in the device body, wherein a mainboard is fixedly arranged in the processor, a capturing module, a timing counter, an inner core, an IO module, an AD acquisition module, a controller, an SPI module and a UART module are fixedly arranged at the upper end of the mainboard, the capturing module, the timing counter, the inner core, the IO module, the AD acquisition module, the controller, the SPI module and the UART module are all electrically connected with the mainboard through wires, a signal shaping module is arranged outside the processor, the output end of the signal shaping module is electrically connected with the input end of the capturing module through a wire, the input end of the signal shaping module is electrically connected with a signal conditioning module through a wire, the input end of the signal conditioning module is electrically connected with a low-pass filter through a wire, and the output end of the signal conditioning module is also electrically connected with the AD acquisition module through a wire, the processor is characterized in that a first photoelectric isolating switch and a second photoelectric isolating switch are further arranged outside the processor, the output end of the first photoelectric isolating switch is electrically connected with the input end of the IO module through a wire, the input end of the first photoelectric isolating switch is electrically connected with an external trigger switch through a wire, the input end of the second photoelectric isolating switch is electrically connected with the output end of the IO module through a wire, the output end of the photoelectric isolating switch is electrically connected with an electronic switch through a wire, the output end of the electronic switch is electrically connected with a fault analog switch through a wire, a serial Flash module and an external communication interface are further arranged outside the processor, the serial Flash module is electrically connected with the SPI module through a wire, and the external interface module is electrically connected with the UART module through a wire.

Preferably, the input end of the low-pass filter is electrically connected with two switching-on reference voltages, a first input panel and a second input panel are fixedly arranged on the surface of the device body, and the first input panel and the second input panel are respectively electrically connected with the two switching-on reference voltages.

Preferably, the surface of the device body is fixedly provided with a display terminal, and the input end of the display terminal is electrically connected with the output end of the UART module through a wire.

Preferably, the surface of the device body is fixedly provided with a start button and a stop button, and the start button and the stop button are both electrically connected with the input end of the low-pass filter.

Preferably, the lateral wall of device organism is fixed and is equipped with RS communication interface and ethernet communication interface, RS485 communication interface and ethernet communication interface all support Modbus, 101 or 104 conventions.

Preferably, the range of the simulation action phase theta of the device body is 0-360 degrees, and the set range of the outlet pulse width tm of the device body is 5-5000 ms.

Preferably, a plurality of switch outlets are fixedly arranged outside the device body, wherein 1-4 switch outlets are high-power electric linkage contactless output interfaces.

(III) advantageous effects

Compared with the prior art, the invention provides a phase control device for simulating fault, which comprises the following components

Has the advantages that:

1. the analog fault phase control device extracts voltage as reference analog quantity through two infinite power supplies arranged, after the voltage is processed by a low-pass filter, the signal is amplified and impedance matched to form periodic square waves, the periodic square waves are transmitted to a capture module for frequency measurement and zero-crossing detection, a CPU starts a high-precision timer for triggering AD conversion at regular time, an AD conversion mark is associated with a DMA module to realize AD automatic timing acquisition, AD acquired data is used for calculating voltage amplitude and calculating a zero-crossing point and a signal period through software for comparing with hardware frequency measurement, the inherent error of hardware frequency measurement and zero-crossing detection is eliminated, the CPU acquires the signal period and frequency in real time, after an external starting signal is detected, phase timing is started at the signal zero-crossing moment, and after the set phase is reached, starting a plurality of fault simulation switches according to the set exit logic and time delay, and completing a fault simulation experiment.

Drawings

Fig. 1 is a schematic structural diagram of a phase control device for simulating a fault according to the present invention;

FIG. 2 is a schematic diagram of electrical connections of processors in a phase control apparatus for simulating a fault according to the present invention;

fig. 3 is a flowchart of a simulated fault phase control apparatus according to the present invention.

In the figure: the device comprises a device body 1, a first input panel 2, a second input panel 3, a display terminal 4, a start button 5, a stop button 6, an RS485 communication interface 7, an Ethernet communication interface 8 and a high-power electronic linkage contactless output interface 9.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1-3, a phase control device for simulating fault comprises a device body 1 and a processor fixedly disposed inside the device body 1, wherein a main board is fixedly disposed inside the processor, a capture module, a timing counter, an inner core, an IO module, an AD acquisition module, a controller, an SPI module and a UART module are fixedly disposed at an upper end of the main board, the capture module, the timing counter, the inner core, the IO module, the AD acquisition module, the controller, the SPI module and the UART module are electrically connected to the main board through wires, a signal shaping module is disposed outside the processor, an output end of the signal shaping module is electrically connected to an input end of the capture module through a wire, an input end of the signal shaping module is electrically connected to a signal conditioning module through a wire, an input end of the signal conditioning module is electrically connected to a low pass filter through a wire, and an output end of the signal conditioning module is also electrically connected, the outside of treater still is equipped with first photoelectric isolator and second photoelectric isolator, the input electric connection of wire and IO module is passed through to first photoelectric isolator's output, first photoelectric isolator's input has external trigger switch through wire electric connection, the output electric connection of wire and IO module is passed through to second photoelectric isolator's input, photoelectric isolator's output has electronic switch through wire electric connection, electronic switch's output passes through wire electric connection fault analog switch, the outside of treater still is equipped with serial Flash module and external communication interface, serial Flash module passes through wire and SPI module electric connection, external interface module passes through wire and UART module electric connection.

The input end of the low-pass filter is electrically connected with two paths of switching-on reference voltages, one path of the switching-on reference voltages can be selected as a reference source through parameter configuration according to actual field requirements, a first input panel 2 and a second input panel 3 are fixedly arranged on the surface of the device body 1, the first input panel 2 and the second input panel 3 are respectively electrically connected with the two paths of switching-on reference voltages, and the device can be operated through the first input panel 2 and the second input panel 3, so that starting and stopping fault simulation can be carried out.

The fixed surface of device organism 1 is equipped with display terminal 4, and display terminal 4's input passes through the wire and the output electric connection of UART module, can show real-time parameter and operating condition, and the user can dispose working method and experimental parameters through the display interface.

A start button 5 and a stop button 6 are fixedly arranged on the surface of the device body 1, the start button 5 and the stop button 6 are both electrically connected with the input end of the low-pass filter, and after the start button is pressed, the device starts to work according to a set single-step mode or a set circulation mode. If the stop button is pressed, the device receives the stop command, and immediately performs resetting, and the logic judgment is finished.

The lateral wall of device organism 1 is fixed to be equipped with RS485 communication interface 7 and ethernet communication interface 8, and RS485 communication interface 7 and ethernet communication interface 8 all support Modbus, 101 or 104 conventions, can realize that remote control device starts and stops.

The range of the simulated motion phase theta of the device body 1 is 0-360 degrees, the simulated motion phase theta can be set according to experimental requirements, the range of the outlet pulse width tm of the device body 1 is 5-5000 ms, and the closing time of each outlet can be set.

A plurality of switch outlets are fixedly arranged outside the device body 1, wherein the switch outlets 1-4 are high-power electric power linkage contactless output interfaces 9, and the instantaneity of the switch outlets is guaranteed.

In summary, when the phase control device for simulating fault is used, voltage is extracted by two infinite power supplies as reference analog quantity, after passing through a low-pass filter, the signal is amplified and impedance-matched, and other conditioning measures are taken, the signal is respectively connected to a frequency measurement loop and an AD acquisition loop, the signal of the frequency measurement loop needs to be subjected to saturation amplification and signal shaping to form periodic square waves, the periodic square waves are sent to a capture module for frequency measurement and zero-crossing detection, a CPU starts and a high-precision timer to trigger AD conversion at regular time, an AD conversion mark is associated with a DMA module to realize AD automatic timing acquisition, the AD acquired data is compared with the hardware frequency measurement, the zero-crossing point and the signal period are calculated by software, the inherent error of the hardware frequency measurement and zero-crossing detection is eliminated, the CPU acquires the signal period and frequency in real time, after an external start signal is detected, and starting phase timing at the signal zero-crossing moment, and starting a plurality of fault simulation switches according to set exit logic and time delay after a set phase is reached to finish a fault simulation experiment.

It is to be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.