阅读说明：本技术 一种消除非线性的低噪声放大器 (Low-noise amplifier for eliminating nonlinearity ) 是由 李振荣 张新雨 王泽渊 杨艳梅 庄奕琪 刘帅 于 2020-07-10 设计创作，主要内容包括：本发明公开了一种消除非线性的低噪声放大器,包括输入匹配电路、放大电路、非线性消除电路、噪声消除电路和输出匹配电路,非线性消除电路通过流复用电感Lc、第一耦合电容C2连接放大电路,实现了三阶非线性项的抵消；噪声消除电路的第二耦合电容C3连接到放大电路的一端,消除第一NMOS管M1的噪声,并增强了电路的跨导；输入匹配电路采用LC谐振结构调谐工作频率,提高射频信号输入匹配度。本发明在获得较好的增益和输入匹配度的同时,有效地改善了低噪声放大器的线性度和噪声系数,可用于射频收发芯片中。(The invention discloses a low-noise amplifier for eliminating nonlinearity, which comprises an input matching circuit, an amplifying circuit, a nonlinear eliminating circuit, a noise eliminating circuit and an output matching circuit, wherein the nonlinear eliminating circuit is connected with the amplifying circuit through a flow multiplexing inductor Lc and a first coupling capacitor C2, so that the cancellation of three-order nonlinear terms is realized; the second coupling capacitor C3 of the noise elimination circuit is connected to one end of the amplifying circuit, so that the noise of the first NMOS tube M1 is eliminated, and the transconductance of the circuit is enhanced; the input matching circuit adopts an LC resonance structure to tune the working frequency, and the input matching degree of the radio frequency signal is improved. The invention can obtain better gain and input matching degree, effectively improve the linearity and noise coefficient of the low noise amplifier, and can be used in a radio frequency transceiver chip.)

1. A low noise amplifier for eliminating nonlinearity comprises an input matching network and an output matching network connected between an input terminal Vin and an amplifying circuit, wherein: the device also comprises an amplifying circuit, a nonlinear eliminating circuit and a noise eliminating circuit; the input matching network adopts an LC resonance structure; the nonlinear cancellation circuit comprises a current multiplexing inductor Lc, a first coupling capacitor C2 and a second NMOS tube M2, wherein one end of the current multiplexing inductor Lc is connected with the drain end of the first NMOS tube M1, the other end of the current multiplexing inductor Lc is connected with the source end of the second NMOS tube M2, and two ends of the first coupling capacitor C2 are respectively connected with the drain electrode of the first NMOS tube M1 and the grid electrode of the second NMOS tube M2; the amplifying circuit comprises a first NMOS transistor M1 and a first bias resistor R1, wherein two ends of the first bias resistor R1 are respectively connected with a first bias voltage Vbias1 and a grid end of the first NMOS transistor M1; the noise elimination circuit comprises a third NMOS tube M3, a second bias resistor R2 and a second coupling capacitor C3, wherein the source electrode of the third NMOS tube M3 is connected with the common ground, the drain electrode of the third NMOS tube M3 is directly connected to the output end Vout, and two ends of the second bias resistor R2 are respectively connected to the gate electrode of the third NMOS tube M3 and a second bias voltage Vbias 2.

2. A low noise amplifier for canceling nonlinearity according to claim 1, wherein: the LC resonance structure comprises an input capacitor C1, a first inductor L1 and a second coupling capacitor C3, wherein the input capacitor C1 and the first inductor L1 are both connected with the source end of a first NMOS tube M1, the other end of the first inductor L1 is connected with the common ground, and the other end of the input capacitor C1 is connected with an input end Vin; two ends of the second coupling capacitor C3 are respectively connected to the source end of the first NMOS transistor M1 and the gate end of the third NMOS transistor M3.

3. A low noise amplifier for canceling nonlinearity according to claim 1, wherein: the gate terminal of the second NMOS transistor M2 in the non-linear cancellation circuit is connected to the power supply voltage VDD, and the drain terminal thereof is connected to the power supply VDD through the second inductor L2.

4. A low noise amplifier for canceling nonlinearity according to claim 1, wherein: the transconductance range of the first NMOS transistor M1 in the amplifying circuit is [20M, 100M ]]Siemens, whose value is in accordance with g_m＝1/R_inIs determined in which g_mRepresents the transconductance, R, of the first NMOS transistor M1_inRepresenting the input impedance of the low noise amplifier; the value of the first bias resistor R1 is determined to be in kiloohm magnitude according to the chip area constraint, and the value range of Vbias1 is [600m, 800m ]]Volts.

5. A low noise amplifier for canceling nonlinearity according to claim 1, wherein: the third NMOS transistor M3 in the noise elimination circuit works in a saturation region, the value of the second bias resistor R2 is the same as that of the first bias resistor R1, and V is_BIAS2Has a value range of [600m, 800m ]]Volts.

6. A low noise amplifier for canceling nonlinearity according to claim 1, wherein: the first inductor L1 is adjusted around 1nH, and the input capacitor C1 and the second coupling capacitor C3 are adjusted around 1 pH.

7. A low noise amplifier for canceling nonlinearity according to claim 1, wherein: the second inductor L2 is adjusted around 6nH, the power supply voltage VDD is 1.2V, and the second NMOS tube M2 works in a saturation region.

Technical Field

The invention belongs to the technical field of microelectronics, and further relates to a low-noise amplifier for eliminating nonlinearity in the technical field of radio frequency integrated circuits. The invention can be used for a radio frequency receiver of a wireless communication system and amplifies the amplitude of a received 6GHz radio frequency signal.

Background

The first active amplification circuit is used as the front end of the radio frequency receiver, the higher the gain of the low noise amplifier is, the larger the amplitude of the output radio frequency signal is, and the stronger the inhibition capability on the noise of a post-stage circuit is; meanwhile, the noise of the low noise amplifier needs to be continuously reduced, and the signal to noise ratio is improved, so that the sensitivity of the whole receiver is enhanced; in addition, in order to prevent the influence of the intermodulation of signals with different frequencies on the circuit performance, the linearity of the low noise amplifier must be improved to avoid the distortion of the signals, and the improvement of the linearity can cause the deterioration of the gain to a certain extent; meanwhile, the input matching characteristic of the low noise amplifier also affects the noise performance of the low noise amplifier. Therefore, when designing a receiver circuit, it is required to balance performance parameters of the low noise amplifier in all aspects, and improve linearity and noise performance while satisfying requirements of gain and input matching degree.

A low noise amplifier circuit with low power consumption is disclosed in patent document "low noise amplifier" (application No. 201710026217.3, publication No. CN108306623A, published even 2018.07.20) of shanghai weiji 29583. The low noise amplifier circuit includes an amplifier basic circuit and a bypass circuit connected in parallel with the amplifier basic circuit, the amplifier basic circuit including an input-end circuit and an output-end circuit. The low noise amplifier is additionally provided with the bypass circuit, and in the specific application process of the low noise amplifier, if an input signal is large enough, the input signal can be identified and switched to a bypass mode without amplifying a receiving end so as to save power consumption and achieve the effect of reducing power consumption. However, the low noise amplifier still has the disadvantages that the basic circuit of the low noise amplifier adopts a simple cascode structure, the linearity of the cascode structure is poor, and when the bypass circuit of the low noise amplifier operates in a small-signal high frequency band, due to the influence of circuit parasitic effect, the input matching performance is deteriorated and the signal is attenuated, so that the functions required by the radio frequency receiving chip are difficult to meet.

The patent document "a low noise amplifier with high linearity" (application No. 201910526423X, publication No. CN110149096A, published as 2019.08.20) applied by the hangzhou zhongke microelectronics ltd discloses a low noise amplifier with high linearity. The high-linearity low-noise amplifier comprises a main amplifier circuit, an auxiliary amplifier circuit and a cascode circuit, wherein the cascode circuit is connected with the main amplifier circuit and the auxiliary amplifier circuit through leads, and the main amplifier circuit is connected with the auxiliary amplifier circuit through leads. The main amplifier circuit provides a transconductance with a positive derivative to the circuit through the NMOS transistor in a low bias state, the auxiliary amplifier circuit provides a transconductance with a negative derivative through the PMOS transistor, and the transconductance with the positive derivative of the main amplifier circuit is compensated to a constant value within a threshold value, so that the linearity is improved under the condition of low power. However, the low noise amplifier with high linearity has the disadvantages that an additional inductor is used when the main amplifier circuit and the auxiliary amplifier of the low noise amplifier are connected, and the cascode circuit needs a bias resistor to assist in realizing the circuit function, so that more devices limit the size of the whole circuit, and the noise performance of the circuit is also deteriorated, which brings more parasitic effects.

Disclosure of Invention

The invention aims to provide a low noise amplifier based on a CMOS process and different from the existing cascode structure for eliminating nonlinearity, which can meet the requirements of matching degree and gain and solve the problem of poor linearity and noise performance of the existing low noise amplifier.

The idea for realizing the purpose of the invention is as follows: an amplification circuit, a nonlinear cancellation circuit, and a noise cancellation circuit are used. A common source structure in the nonlinear elimination circuit is utilized to provide a negative third-order nonlinear term, and the negative third-order nonlinear term is connected with a common gate structure with a positive third-order nonlinear term in the amplification circuit, so that the third-order nonlinear term is eliminated and the linearity is improved; the current multiplexing structure in the nonlinear cancellation circuit is utilized to realize the self-bias of the common source structure, and the area and the power consumption of the circuit are reduced; the noise of the first NMOS tube M1 in the amplifying circuit is eliminated by using the noise elimination circuit, and meanwhile, the circuit transconductance is enhanced.

In order to achieve the above object, the present invention provides a nonlinear low noise amplifier, which comprises an input matching network, an output matching network, an amplifying circuit, a nonlinear canceling circuit and a noise canceling circuit, wherein the input matching network, the output matching network, the amplifying circuit, the nonlinear canceling circuit and the noise canceling circuit are connected to an input terminal Vin and the amplifying circuit; the input matching network adopts an LC resonance structure; the nonlinear cancellation circuit comprises a current multiplexing inductor Lc, a first coupling capacitor C2 and a second NMOS tube M2, wherein one end of the current multiplexing inductor Lc is connected with the drain end of the first NMOS tube M1, the other end of the current multiplexing inductor Lc is connected with the source end of the second NMOS tube M2, and two ends of the first coupling capacitor C2 are respectively connected with the drain electrode of the first NMOS tube M1 and the grid electrode of the second NMOS tube M2; the amplifying circuit comprises a first NMOS transistor M1 and a first bias resistor R1, wherein two ends of the first bias resistor R1 are respectively connected with a first bias voltage Vbias1 and a grid end of the first NMOS transistor M1; the noise elimination circuit comprises a third NMOS tube M3, a second bias resistor R2 and a second coupling capacitor C3, wherein the source electrode of the third NMOS tube M3 is connected with the common ground, the drain electrode of the third NMOS tube M3 is directly connected to the output end Vout, and two ends of the second bias resistor R2 are respectively connected to the gate electrode of the third NMOS tube M3 and a second bias voltage Vbias 2.

Compared with the prior art, the invention has the following advantages:

firstly, the input matching network of the invention adopts an LC resonance structure, a first inductor L1, an input coupling capacitor C1 and a second coupling capacitor C3 in the LC resonance structure are all connected with the source end of a first NMOS transistor M1 to generate resonance, and the working frequency of the low noise amplifier can be tuned to 6GHz by adjusting the value of the first inductor L1, so that out-of-band interference is inhibited, the problem of poor input matching degree in the prior art is solved, the invention has higher input matching characteristic, the maximum power transmission of the circuit is realized, and the noise coefficient of the amplifier is reduced.

Secondly, a nonlinear elimination circuit is added on the basis of the amplification circuit, one end of a current multiplexing inductor Lc in the nonlinear elimination circuit is connected with the drain end of a first NMOS tube M1 of the amplification circuit, the other end of the current multiplexing inductor Lc is connected with the source end of a second NMOS tube, and two ends of a first coupling capacitor C2 are respectively connected with the source end of the first NMOS tube M1 and the gate end of the second NMOS tube M2; the second NMOS tube M2 generates a negative third-order nonlinear term, the first NMOS tube M1 of the amplifying circuit generates a positive third-order nonlinear term, and the negative third-order nonlinear term and the positive third-order nonlinear term are respectively connected to two ends of the current multiplexing inductor Lc to form a cancellation effect, so that the problem of poor linearity caused by a cascode structure in the prior art is solved, and the linearity at the working frequency is improved.

Thirdly, the amplifier circuit of the invention is additionally provided with a noise elimination circuit, the noise elimination circuit comprises a second bias resistor R2 and a third NMOS tube M3, two ends of the second bias resistor R2 are respectively connected with the grid of the third NMOS tube M3 and a second bias voltage Vbias2, the source end of the third NMOS tube M3 is connected with the common ground, the grid end of the third NMOS tube M3 is connected with the source end of the first NMOS tube M1 through a second coupling capacitor C3, the noise of the first NMOS tube M1 is eliminated, the problem of circuit noise performance deterioration caused by a plurality of devices in the prior art is solved, the noise coefficient of the amplifier is reduced, and meanwhile, the gain of the amplifier is improved through transconductance enhancement, so that the signal-to-noise ratio at the working frequency is improved.

Drawings

FIG. 1 is an electrical schematic of the present invention;

FIG. 2 is a graph of simulation results of input return loss of the present invention;

FIG. 3 is a graph of simulation results for the noise figure of the present invention;

FIG. 4 is a graph of simulation results of the third order intermodulation characteristics of the present invention;

the specific implementation mode is as follows:

the invention is further described below with reference to the accompanying drawings.

The overall circuit architecture topology of the present invention is further described with reference to fig. 1.

The invention comprises an input matching circuit, an output matching network, an amplifying circuit, a nonlinear eliminating circuit and a noise eliminating circuit which are connected with an input end Vin and the amplifying circuit.

The input impedance matching network adopts an LC resonance structure, the LC resonance structure comprises an input capacitor C1, a first inductor L1 and a second coupling capacitor C3, the input capacitor C1 and the first inductor L1 are both connected with the source end of a first NMOS transistor M1, the other end of the first inductor L1 is connected with the common ground, and the other end of the input capacitor C1 is connected with an input end Vin; two ends of the second coupling capacitor C3 are respectively connected to the source end of the first NMOS transistor M1 and the gate end of the third NMOS transistor M3. By adjusting the inductance of the first inductor L1, the input capacitance of the circuit is cancelled out, thereby improving the input matching degree. The first inductor L1 is adjusted around 1nH, and the input capacitor C1 and the second coupling capacitor C3 are both adjusted around 1 pH.

The nonlinear cancellation circuit comprises a current multiplexing inductor Lc, a first coupling capacitor C2 and a second NMOS tube M2, wherein one end of the current multiplexing inductor Lc is connected with the drain end of the first NMOS tube M1, the other end of the current multiplexing inductor Lc is connected with the source end of the second NMOS tube M2, and two ends of the first coupling capacitor C2 are respectively connected with the drain electrode of the first NMOS tube M1 and the grid electrode of the second NMOS tube M2; the gate terminal of the second NMOS transistor M2 in the non-linear cancellation circuit is connected to the power supply voltage VDD, and the drain terminal thereof is connected to the power supply VDD through the second inductor L2. The second inductor L2 is adjusted around 6nH, the power supply voltage VDD is 1.2V, and the second NMOS transistor M2 works in a saturation region.

The amplifying circuit comprises a first NMOS transistor M1 and a first bias resistor R1, wherein two ends of the first bias resistor R1 are respectively connected with a first bias voltage Vbias2 and a grid end of the first NMOS transistor M1; the transconductance range of the first NMOS transistor M1 in the amplifying circuit is [20M, 100M ]]Siemens, whose value is in accordance with g_M1＝1/R_inDetermining that the value of the first bias resistor R1 is determined to be in kiloohm magnitude according to the chip area, and taking [600m, 800m ] for Vbias1]Volts.

The noise elimination circuit comprises a third NMOS transistor M3, a second bias resistor R2 and a second coupling capacitor C3, wherein the source electrode of the third NMOS transistor M3 is connected with the common ground, the drain electrode is directly connected with the output end Vout, and the second biasTwo ends of the resistor R2 are respectively connected to the gate of the third NMOS transistor M3 and the second bias voltage Vbias 2. The third NMOS transistor M3 in the noise elimination circuit works in a saturation region, the second bias resistor R2 is the same as the first bias resistor R1, and V is_BIAS2Take [600m, 800m ]]Volts. The signal of the source electrode of the first NMOS transistor M1 enters the gate electrode of the third NMOS transistor M3 through the second coupling capacitor C3 for amplification, and by setting the appropriate size of the third NMOS transistor M3, the noise of the first NMOS transistor M1 can be partially or completely cancelled, the noise coefficient of the high-linearity low-noise amplifier is reduced, and meanwhile, the third NMOS transistor M3 can realize transconductance enhancement to improve the gain.

The working principle of the invention is as follows:

the input end Vin inputs a radio frequency signal with the frequency of 6GHz, bias voltages Vbias1 and Vbias2 are provided for the low noise amplifier of the invention through current mirror bias or direct voltage bias, the width-length ratio of the first NMOS tube M1, the second NMOS tube M2 and the third NMOS tube M3 is changed at the same time, the working current of the amplifying circuit and the noise eliminating circuit is adjusted, and signal amplification is realized.

The first NMOS tube in the amplifying circuit converts input voltage into current, and if the channel length modulation effect and the body effect of the NMOS tube are neglected, the real part of the input impedance of the NMOS tube is as follows:

where Rin represents the input resistance of the low noise amplifier, g_M1The transconductance of the first NMOS tube is represented; g_M1Is expressed as

Wherein, mu and C_ox、

And I_DRespectively representing the carrier mobility, the gate oxide layer capacitance, the width-length ratio and the leakage current of the first NMOS; therefore, the width-to-length ratio of the NMOS tube can be adjustedAnd leakage current I_DTo change g_M1So as to meet the requirement of matching the input electrical impedance of the low-noise amplifier.

In the low noise amplifier of the invention, at the source end of the first NMOS transistor M1 and the drain end of the second NMOS transistor M2, the polarities of radio frequency signals are opposite, and the polarities of noises generated by the first NMOS transistor M1 are the same. The third NMOS transistor M3 reversely transmits the noise at the source terminal of the first NMOS transistor M1, and adds the noise at the drain terminal of the second NMOS transistor M2, so as to cancel the noise voltage at the output terminal. Compared with the noise analysis process, the radio frequency signal voltage with the opposite polarity is subjected to the action of the noise elimination circuit to generate the signal voltage in the same direction, and the signal voltage is enhanced in output.

The input-output characteristic of the first NMOS transistor M1 in the amplifying circuit of the present invention can be expressed as a polynomial:

wherein i_d1Represents the leakage current, v, of the first NMOS transistor M1_gs1Representing the gate-source voltage of the first NMOS transistor M1,

indicating a small signal gain of the first NMOS transistor M1,representing the second order intermodulation term gain of the first NMOS transistor M1,

represents the third-order intermodulation gain of the first NMOS transistor M1;

the input-output characteristic of the second NMOS transistor M2 in the non-linear cancellation circuit can be expressed as a polynomial:

wherein i_d2Represents the leakage current, v, of the second NMOS transistor M2_gs2Represents the gate-source voltage of the second NMOS transistor M2,

indicating a small signal gain of the two NMOS transistors M2,

the gain of the second-order intermodulation term is shown,

showing the third-order intermodulation gain of the second NMOS transistor M2, the nonlinearity of the low noise amplifier is mainly derived from the third-order intermodulation gain α₃And β₃。

Neglecting the influence of the channel length modulation effect and the body effect of the first NMOS transistor M1 and the second NMOS transistor M2, the calculation result is obtainedWherein g is_M1、g_M2Respectively representing the transconductance of M1 and the transconductance of a second NMOS transistor M2, R_SRepresenting the signal source impedance, Z_SThe source impedance of the second NMOS transistor M2 is shown; parameters in the moleculeWherein, mu_nRepresenting the carrier mobility of the first NMOS tube and the second NMOS tube, C_oxThe gate oxide capacitances of the first NMOS transistor M1 and the second NMOS transistor M2 are represented,α can be seen by the width-to-length ratio of the first NMOS transistor M1 and the width-to-length ratio of the second NMOS transistor M2₃＞0，β₃The < 0 forms a cancellation effect in a calculation formula of an input third-order cut-off point, and the linearity of the low-noise amplifier is improved.

The effect of the present invention will be further described with reference to simulation experiments.

1. Simulation experiment conditions are as follows:

the hardware platform of the simulation experiment of the invention is as follows: the processor is Intel (R) Pentium (R) CPU, the main frequency is 3GHz, and the memory is 4 GB.

The software platform of the simulation experiment of the invention is as follows: a Linux operating system and an IC 617.

The simulation of the invention is to use a Spectre RF simulation tool to simulate the circuit of the invention, and adopt an SMIC55nm CMOS process, the given power supply voltage VDD is 1.2V, the working temperature is 26 ℃, the values of bias voltages Vbias1 and Vbias2 are 600mV, the working frequency is 6GHz, the scanning range of the frequency of the input radio frequency signal is [4G, 9G ] Hz, and the scanning range of the power of the input radio frequency signal is [ -40, 10] dBm.

2. Simulation content and result analysis thereof:

the simulation experiment of the invention adopts the Spectre RF simulation technology of the invention and the prior art, and three simulation experiments are carried out: simulation experiment 1, simulation of input return loss of a low noise amplifier, simulation experiment 2, simulation of noise coefficient of the low noise amplifier, and simulation experiment 3, simulation of linearity of the low noise amplifier.

The spectrum RF simulation technology refers to the simulation technology for radio frequency integrated circuits proposed by Cadence company in "Cadence announces the new technology of spectrum RF simulation [ J ]. electronic design technology, 1996(10): 59.".

The following describes the simulation experiment 1 of the present invention with reference to fig. 2.

An input port and an output port are respectively added to an input end Vin and an output end Vout of the low-noise amplifier circuit, the scanning range of the frequency of an input radio-frequency signal is set to [4G, 9G ] Hz, the step is 100MHz, and the input port of the low-noise amplifier is subjected to return loss simulation to obtain a simulation result diagram of the input return loss of the low-noise amplifier of the invention shown in FIG. 2. The abscissa in fig. 2 represents the input radio frequency signal frequency in GHz and the ordinate represents the input return loss of the low noise amplifier in dB. The curve in fig. 2 is the input return loss S11 of the low noise amplifier obtained by performing the return loss simulation on the input port of the low noise amplifier. As can be seen from FIG. 2, the input return loss of the low noise amplifier in simulation experiment 1 can be as low as-30 dB or less, and is less than-10 dB from 5.8GHz to 6.8GHz, so that the input matching requirement is met.

The following describes the simulation experiment 2 of the present invention with reference to fig. 3.

An input port and an output port are respectively added to an input end Vin and an output end Vout of the circuit, the scanning range of the frequency of an input radio frequency signal is set to [4G, 9G ] Hz, the step is 100MHz, and the noise coefficient simulation is carried out on the input port of the low noise amplifier to obtain a noise coefficient simulation result diagram of the invention shown in FIG. 3. The abscissa in fig. 3 represents the frequency of the input low noise amplifier signal in GHz, and the ordinate represents the noise figure value of the low noise amplifier in dB; the noise figure of the low noise amplifier obtained by performing noise figure simulation on the input port of the low noise amplifier is represented by a curve in fig. 3. As can be seen from fig. 3, the noise figure of the low noise amplifier in simulation experiment 2 is only 1.4dB at the operating frequency of 6GHz, and the noise figures in the frequency bands from 5.2GHz to 7.6GHz are all less than 2dB, so that the noise performance is greatly improved.

The following describes the simulation experiment 3 of the present invention with reference to fig. 4.

Setting the test frequency to be 6GHz, the scanning range of the radio frequency input signal power to be [ -40, 0] dBm, the stepping to be 0.05dBm, selecting a first order and a third order for the simulation order, measuring the power of the output signal at the output port, respectively obtaining the output power of a first order item and the output power of a third order intermodulation item, and obtaining a linearity simulation result chart of the invention shown in FIG. 4. The abscissa in fig. 4 represents the rf input signal power, the ordinate represents the output signal power, and the units of the abscissa and the ordinate are dBm; the power of the output signal is measured at the output port, the output power of the resulting first order term, indicated by the dashed line in fig. 4, the output power of the resulting third order intermodulation term, indicated by the solid line in fig. 4, and the corresponding abscissa value at the intersection of the two lines represents the input third order intercept point. As can be seen from fig. 4, the input third-order intercept point of the low noise amplifier in simulation experiment 3 is 7.8dBm, which indicates that the invention has higher linearity.

The theoretical analysis and simulation results show that the nonlinear cancellation low-noise amplifier can obtain higher linearity and lower noise coefficient while meeting the input matching degree.

The above-described example is only one implementation of the present invention, and it is to be understood that changes in form and detail may be made by those skilled in the art without inventive faculty, based on the basic principles, construction and details of the invention. Therefore, modifications and changes that may be suggested by those skilled in the art are intended to be included within the scope of the appended claims.