阅读说明：本技术 太阳能电池的制造方法 (Method for manufacturing solar cell ) 是由 中野邦裕 三岛良太 口山崇 于 2019-02-19 设计创作，主要内容包括：一种太阳能电池的制造方法,包含：在晶体基板(11)的一个主面(11S)上形成p型半导体层(13p)的工序、在p型半导体层(13p)上层叠以氧化物为主成分的剥离层(LF)的工序、选择性地除去p型半导体层(13p)和剥离层(LF)的工序,在选择性地除去p型半导体层(13p)和剥离层(LF)的工序中,进行使用2种以上的不同蚀刻液的湿式蚀刻,以使从晶体基板(11)的表面垂直方向的一个主面侧观察,p型半导体层(13p)的蚀刻面积小于或等于剥离层(LF)的蚀刻面积。(A method of fabricating a solar cell, comprising: in a step of forming a p-type semiconductor layer (13p) on one main surface (11S) of a crystal substrate (11), a step of laminating a peeling Layer (LF) containing an oxide as a main component on the p-type semiconductor layer (13p), and a step of selectively removing the p-type semiconductor layer (13p) and the peeling Layer (LF), wet etching using 2 or more different etching solutions is performed in the step of selectively removing the p-type semiconductor layer (13p) and the peeling Layer (LF) so that the etching area of the p-type semiconductor layer (13p) is smaller than or equal to the etching area of the peeling Layer (LF) when viewed from one main surface side in a direction perpendicular to the surface of the crystal substrate (11).)

1. A method for manufacturing a solar cell includes the steps of:

a step of forming a 1 st semiconductor layer of a 1 st conductivity type on one main surface of 2 main surfaces opposed to each other in a semiconductor substrate,

a step of laminating a peeling layer containing an oxide as a main component on the 1 st semiconductor layer,

a step of selectively removing the 1 st semiconductor layer and the peeling layer by etching,

a step of forming a 2 nd semiconductor layer of a 2 nd conductivity type on the one main surface including the 1 st semiconductor layer and the peeling layer,

removing the peeling layer to remove the 2 nd semiconductor layer covering the peeling layer;

in the step of selectively removing the 1 st semiconductor layer and the peeling layer, the 1 st semiconductor layer and the peeling layer are removed by wet etching using 2 or more different etching solutions so that an etching area of the 1 st semiconductor layer is equal to or smaller than an etching area of the peeling layer as viewed from the one principal surface side in a direction perpendicular to a surface of the semiconductor substrate.

2. The method for manufacturing a solar cell according to claim 1, wherein the step of selectively removing the 1 st semiconductor layer and the peeling layer includes a peeling layer removing step of removing the peeling layer and a 1 st semiconductor layer removing step of removing the 1 st semiconductor layer,

the type of the etching solution used in the peeling layer removing step is different from the type of the etching solution used in the first semiconductor layer removing step 1.

3. The method for manufacturing a solar cell according to claim 2, wherein when the etching solution used in the peeling layer removing step is defined as a 1 st etching solution and the etching solution used in the 1 st semiconductor layer removing step is defined as a 2 nd etching solution,

the 1 st etching solution satisfies the following relational expression (1):

the etching rate of the 1 st semiconductor layer is < the etching rate of the peeling layer,

the 2 nd etching solution satisfies the following relation (2):

the etching rate of the 1 st semiconductor layer is less than or equal to that of the peeling layer.

4. The method for manufacturing a solar cell according to any one of claims 1 to 3, wherein the peeling layer contains an oxide of an element selected from the group consisting of indium, zinc, tin, aluminum, and silicon as a main component.

5. The method for manufacturing a solar cell according to any one of claims 1 to 4, wherein the peeling layer is formed to have a film thickness of 20nm to 500nm in the step of laminating the peeling layers.

6. The method for manufacturing a solar cell according to any one of claims 1 to 5, wherein the semiconductor substrate has a 1 st texture structure on each of the 2 main surfaces,

the 1 st semiconductor layer and the 2 nd semiconductor layer formed on the one main surface of the semiconductor substrate include a 2 nd texture structure reflecting the 1 st texture structure.

7. The method for manufacturing a solar cell according to any one of claims 1 to 6, wherein in the step of selectively removing the 1 st semiconductor layer and the peeling layer, in order to form a part of the 2 nd semiconductor layer on the 1 st semiconductor layer in the step of removing the 2 nd semiconductor layer, etching is performed so as to form an edge portion of the peeling layer receding from an edge portion of the 1 st semiconductor layer.

Technical Field

The technology disclosed herein belongs to the technical field of a method for manufacturing a solar cell.

Background

A general solar cell is a double-sided electrode type in which electrodes are arranged on both surfaces (a light receiving surface and a back surface) of a semiconductor substrate, and recently, as a solar cell having no shielding loss due to the electrodes, a back contact (back electrode) type solar cell in which only electrodes are arranged on the back surface as described in patent document 1 has been developed.

The back contact solar cell requires a semiconductor layer pattern such as a p-type semiconductor layer and an n-type semiconductor layer to be formed on the back surface with high accuracy, and the manufacturing method is more complicated than that of the double-sided electrode type solar cell. As a technique for simplifying the manufacturing method, as described in patent document 1, there is a technique for forming a semiconductor layer pattern by a lift-off method. That is, a patterning technique for forming a semiconductor layer pattern is developed by removing the peeling layer and removing the semiconductor layer formed over the peeling layer.

Disclosure of Invention

However, in the method described in patent document 1, when the solubility of the peeling layer and the semiconductor layer is similar, the layer which is not desired to be removed may be removed, and there is a possibility that the patterning accuracy or the productivity is not high.

The technology disclosed herein has been made in view of the above-described circumstances, and an object thereof is to efficiently manufacture a high-performance back contact type solar cell.

In order to solve the above problem, a technique disclosed herein includes the steps of: a step of forming a 1 st semiconductor layer of a 1 st conductivity type on one principal surface of 2 principal surfaces opposed to each other in a semiconductor substrate, a step of laminating a peeling layer containing an oxide as a main component on the 1 st semiconductor layer, a step of selectively removing the 1 st semiconductor layer and the peeling layer by etching, a step of forming a 2 nd semiconductor layer of a 2 nd conductivity type on the one principal surface including the 1 st semiconductor layer and the peeling layer, and a step of removing the 2 nd semiconductor layer covering the peeling layer by removing the peeling layer, wherein in the step of selectively removing the 1 st semiconductor layer and the peeling layer, the 1 st semiconductor layer and the peeling layer are removed by wet etching using 2 or more different kinds of etching liquids as viewed from the one principal surface side in a direction perpendicular to a surface of the semiconductor substrate, so that the etching area of the 1 st semiconductor layer is smaller than or equal to the etching area of the peeling layer.

According to the technology disclosed herein, a high-performance back contact type solar cell can be efficiently manufactured.

Drawings

Fig. 1 is a schematic cross-sectional view partially showing a solar cell of an exemplary embodiment.

Fig. 2 is a plan view showing a back principal surface of a crystal substrate constituting a solar cell.

Fig. 3 is a schematic partial cross-sectional view showing one step of a method for manufacturing a solar cell.

Fig. 4 is a schematic partial cross-sectional view showing one step of a method for manufacturing a solar cell.

Fig. 5 is a schematic partial cross-sectional view showing one step of a method for manufacturing a solar cell.

Fig. 6 is a schematic partial cross-sectional view showing one step of a method for manufacturing a solar cell.

Fig. 7 is a schematic partial cross-sectional view showing a step of a method for manufacturing a solar cell.

Fig. 8 is a schematic partial cross-sectional view showing a step of a method for manufacturing a solar cell.

Fig. 9 is a schematic partial cross-sectional view showing a step of a method for manufacturing a solar cell.

Fig. 10 is a schematic partial cross-sectional view showing a step of a method for manufacturing a solar cell.

Fig. 11 is a plan view of the state of fig. 7 at the end of the process, as viewed from the back principal surface side in the direction perpendicular to the surface of the crystal substrate.

Fig. 12 is a view corresponding to fig. 8 showing a modification of the present embodiment.

Fig. 13 is a view corresponding to fig. 9 showing a modification of the present embodiment.

Detailed Description

The illustrated embodiments are described with reference to the accompanying drawings.

Fig. 1 shows a partial sectional view of a solar cell (battery cell) according to the present embodiment. As shown in fig. 1, a crystalline substrate 11 made of silicon (Si) is used for the solar cell 10 of the present embodiment. The crystal substrate 11 has 2 main surfaces 11S (11SU, 11SB) facing each other. Here, the main surface on which light is incident is referred to as a front main surface 11SU, and the main surface on the opposite side is referred to as a back main surface 11 SB. For convenience, the front main surface 11SU is configured to receive light more positively than the back main surface 11SB, and to receive no light positively.

The solar cell 10 of the present embodiment is a so-called hetero-junction silicon solar cell, and is a back-contact type (back-electrode type) solar cell in which an electrode layer is disposed on the back-side main surface 11 SB.

The solar cell 10 includes a crystal substrate 11, an intrinsic semiconductor layer 12, a conductive semiconductor layer 13 (p-type semiconductor layer 13p, n-type semiconductor layer 13n), a low reflection layer 14, and an electrode layer 15 (transparent electrode layer 17, metal electrode layer 18).

Hereinafter, for convenience, a part corresponding to each of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n independently may be denoted by "p" or "n" at the end of the reference numeral. Further, since the conductivity types are different between p-type and n-type, one conductivity type may be referred to as "1 st conductivity type", and the other conductivity type may be referred to as "2 nd conductivity type".

The crystal substrate 11 may be a semiconductor substrate made of single crystal silicon or a semiconductor substrate made of polycrystalline silicon. Hereinafter, a single crystal silicon substrate will be described as an example.

The conductivity type of the crystal substrate 11 may be an n-type single crystal silicon substrate into which an impurity for introducing electrons into silicon atoms (for example, phosphorus (P) atoms) is introduced, or a P-type single crystal silicon substrate into which an impurity for introducing holes into silicon atoms (for example, boron (B)) is introduced. Hereinafter, an n-type single crystal substrate having a long carrier lifetime will be described as an example.

In addition, from the viewpoint of blocking received light in advance, the crystal substrate 11 may have a texture TX (1 st texture) composed of peaks (projections) and valleys (recesses) on the surfaces of the 2 main surfaces 11S. The texture TX (uneven surface) can be formed by, for example, anisotropic etching using the difference between the etching rate of the crystal substrate 11 in which the crystal plane is oriented as a (100) crystal plane and the etching rate of the crystal plane oriented as a (111) crystal plane.

The thickness of the crystal substrate 11 may be 250 μm or less. The measurement direction in the thickness measurement is a direction perpendicular to the average plane of the crystal substrate 11 (the average plane is a plane independent of the texture TX as a whole substrate). Hereinafter, the vertical direction, that is, the direction in which the thickness is measured is referred to as the surface vertical direction.

The size of the bump in the texture TX may be defined by the number of vertices, for example. In the present embodiment, the number of vertexes is preferably 50000/mm from the viewpoint of light harvesting performance and productivity²100000 pieces/mm²Particularly preferably 70000 pieces/mm²85000 pieces/mm²。

If the thickness of the crystal substrate 11 is 250 μm or less, the amount of silicon used can be reduced, and therefore, the silicon substrate can be easily secured, and cost reduction can be achieved. In addition, a back contact structure in which holes and electrons generated by photoexcitation in the silicon substrate are collected only on the back surface side is also preferable from the viewpoint of the free path of each exciton.

On the other hand, if the thickness of the crystal substrate 11 is too small, the mechanical strength is reduced, or external light (sunlight) cannot be sufficiently absorbed, resulting in a reduction in short-circuit current density. Therefore, the thickness of the crystal substrate 11 is preferably 50 μm or more, and more preferably 70 μm or more. When the texture structure TX is formed on the main surface of the crystal substrate 11, the thickness of the crystal substrate 11 is represented by the distance between straight lines connecting the apexes of the protrusions in the concave-convex structures on the light receiving side and the back side.

The intrinsic semiconductor layers 12(12U, 12p, 12n) cover both main surfaces 11S (11SU, 11SB) of the crystal substrate 11, thereby suppressing diffusion of impurities into the crystal substrate 11 and performing surface passivation. Note that "intrinsic (i-type)" is not limited to completely intrinsic containing no conductive impurity, and includes a layer which is substantially intrinsic, such as a "weak n-type" or a "weak p-type" containing a small amount of an n-type impurity or a p-type impurity in a range where the silicon-based layer can function as an intrinsic layer.

The intrinsic semiconductor layer 12(12U, 12p, 12n) is not essential, and may be formed as appropriate as needed.

The material of the intrinsic semiconductor layer 12 is not particularly limited, and may be an amorphous silicon-based thin film or a hydrogenated amorphous silicon-based thin film (a-Si: H thin film) containing silicon and hydrogen. Here, amorphous means a structure having no long-range order. I.e. not only completely disordered structures, but also short-range ordered structures.

The thickness of the intrinsic semiconductor layer 12 is not particularly limited, and may be 2nm to 20 nm. This is because if the thickness is 2nm or more, the effect as a passivation layer is improved, and if the thickness is 20nm or less, the reduction of the switching characteristics due to the increase in resistance is suppressed.

The method for forming the intrinsic semiconductor layer 12 is not particularly limited, and a Plasma CVD (Plasma enhanced Chemical Vapor Deposition) method can be used. According to this method, the surface of the substrate can be effectively passivated while suppressing diffusion of impurities into the single crystal silicon. In addition, in the case of the plasma CVD method, by changing the hydrogen concentration in the layer of the intrinsic semiconductor layer 12 in the thickness direction thereof, it is also possible to form an energy gap profile (energy gap profile) effective for recovery of carriers.

As the film forming conditions of the thin film by the plasma CVD method, for example, the substrate temperature may be 100 to 300 ℃, the pressure may be 20 to 2600Pa, and the high frequency power density may be 0.003W/cm²～0.5W/cm²。

In addition, as a source gas for forming a thin film, monosilane (SiH) may be used in the case of the intrinsic semiconductor layer 12₄) And disilane (Si)₂H₆) Silicon-containing gas, or a mixture of such gas and hydrogen (H)₂) The mixed gas.

Further, methane (CH) may be added to the gas₄) Ammonia (NH)₃) Or germylane (GeH)₄) And gases containing different kinds of elements are mixed to form silicon carbide (SiC) and silicon nitride (SiN)_X) Or a silicon compound such as silicon germanium (SIGe) to appropriately change the energy gap of the thin film.

Examples of the conductive semiconductor layer 13 include a p-type semiconductor layer 13p and an n-type semiconductor layer 13 n. As shown in fig. 1, the p-type semiconductor layer 13p is formed on a part of the back-side main surface 11SB of the crystal substrate 11 with the intrinsic semiconductor layer 12p interposed therebetween. The n-type semiconductor layer 13n is formed on the other part of the back main surface of the crystal substrate 11 with the intrinsic semiconductor layer 12n interposed therebetween. That is, the intrinsic semiconductor layer 12 is interposed between the p-type semiconductor layer 13p and the crystal substrate 11 and between the n-type semiconductor layer 13n and the crystal substrate 11, respectively, as an intermediate layer that functions as a passivation.

The thickness of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n is not particularly limited, and may be 2nm to 20 nm. This is because if the thickness is 2nm or more, the effect as a passivation layer is improved, and if the thickness is 20nm or less, the reduction of the switching characteristics due to the increase in resistance is suppressed.

The p-type semiconductor layer 13p and the n-type semiconductor layer 13n are disposed on the back side of the crystal substrate 11 so that the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are electrically separated from each other through the intrinsic semiconductor layer 12. The width of the conductive semiconductor layer 13 may be 50 μm to 3000 μm, or 80 μm to 500 μm. The widths of the semiconductor layers 12 and 13 and the widths of the electrode layers 17 and 18 are, unless otherwise specified, lengths of a part of each patterned layer, that is, lengths in a direction perpendicular to an extending direction of a part of each patterned layer, that is, a part of each patterned layer in a linear shape, for example.

In the solar cell 10 of the present embodiment, a part of the intrinsic semiconductor layer 12n and a part of the n-type semiconductor layer 13n are formed on the p-type semiconductor layer 13 p. The intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed on the p-type semiconductor layer 13p such that the edges in the width direction are substantially on one surface.

When excitons (carriers) generated in the crystal substrate 11 are extracted through the conductive semiconductor layer 13, the effective mass of holes is larger than that of electrons. Therefore, the width of the p-type semiconductor layer 13p may be narrower than that of the n-type semiconductor layer 13n from the viewpoint of reducing the transmission loss. For example, the width of the p-type semiconductor layer 13p may be 0.5 to 0.9 times, or 0.6 to 0.8 times the width of the n-type semiconductor layer 13 n.

The p-type semiconductor layer 13p is a silicon layer to which a p-type dopant (such as boron) is added, and may be formed of amorphous silicon in view of suppressing diffusion of impurities or suppressing series resistance. On the other hand, the n-type semiconductor layer 13n is a silicon layer to which an n-type dopant (phosphorus or the like) is added, and may be formed of an amorphous silicon layer as in the case of the p-type semiconductor layer 13 p.

As a source gas of the conductive semiconductor layer 13, monosilane (SiH) can be used₄) Or disilane (Si)₂H₆) Silicon-containing gas or silicon-based gas and hydrogen (H)₂) The mixed gas of (1). Diborane (B) is used as a dopant gas for forming the p-type semiconductor layer 13p₂H₆) Etc., in the formation of the n-type semiconductor layer using Phosphine (PH)₃) And the like. Further, since the amount of impurities such as boron (B) and phosphorus (P) may be small, a mixed gas obtained by diluting a dopant gas with a source gas may be used.

In addition, methane (CH) may be added to adjust the energy gap of the p-type semiconductor layer 13p or the n-type semiconductor layer 13n₄) Carbon dioxide (CO)₂) Ammonia (NH)₃) Or germylane (GeH)₄) And the gas containing different kinds of elements is alloyed with the p-type semiconductor layer 13p or the n-type semiconductor layer 13 n.

The low reflection layer 14 is a layer that suppresses reflection of light received by the solar cell 10. The material of the low reflection layer 14 is not particularly limited as long as it is a light-transmitting material that transmits light, and examples thereof include silicon oxide (SiO)_X) Silicon nitride (SiN)_X) Zinc oxide (ZnO) or titanium oxide (TiO)_X). In addition, as a method for forming the low reflection layer 14, for example, a resin material in which nanoparticles of an oxide such as zinc oxide or titanium oxide are dispersed may be used for coating.

The electrode layer 15 is formed so as to cover the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, and is electrically connected to each of the conductive semiconductor layers 13. Thus, the electrode layer 15 functions as a carrier transport layer that conducts carriers generated in the p-type semiconductor layer 13p or the n-type semiconductor layer 13 n. The electrode layers 15p and 15n corresponding to the semiconductor layers 13p and 13n are arranged separately from each other, thereby preventing a short circuit between the p-type semiconductor layer 13p and the n-type semiconductor layer 13 n.

The electrode layer 15 may be formed only of a metal having high conductivity. In addition, from the viewpoint of electrical bonding with each of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n, or from the viewpoint of suppressing diffusion of atoms into the two semiconductor layers 13p and 13n of metal as an electrode material, electrode layers 15 made of a transparent conductive oxide may be provided between the metal electrode layer and the p-type semiconductor layer 13p and between the metal electrode layer and the n-type semiconductor layer 13n, respectively.

In this embodiment, the electrode layer 15 made of a transparent conductive oxide is referred to as a transparent electrode layer 17, and the electrode layer 15 made of a metal is referred to as a metal electrode layer 18. As shown in the plan view of the back-side main surface 11SB of the crystal substrate 11 shown in fig. 2, in the p-type semiconductor layer 13p and the n-type semiconductor layer 13n each having a comb-tooth shape, the electrode layer formed on the back of the comb is sometimes referred to as a main grid (bus bar) portion, and the electrode layer formed on the comb-tooth portion is sometimes referred to as a fine grid (finger) portion.

Transparent electrodeThe material of the layer 17 is not particularly limited, and examples thereof include zinc oxide (ZnO) and indium oxide (InO)_X) Or indium oxide to which various metal oxides such as titanium oxide (TiO) are added in an amount of 1 to 10 wt%_X) Tin oxide (SnO)_X) Tungsten oxide (WO)_X) Or molybdenum oxide (MoO)_X) And the like.

The thickness of the transparent electrode layer 17 may be 20nm to 200 nm. Examples of a method suitable for forming the transparent electrode layer having such a thickness include a Physical Vapor Deposition (PVD) method such as a sputtering method, and a Metal-Organic chemical Vapor Deposition (MOCVD) method using a reaction of an organometallic compound with oxygen or water.

The material of the metal electrode layer 18 is not particularly limited, and examples thereof include silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), and the like.

The thickness of the metal electrode layer 18 may be 1 μm to 80 μm. A method of forming the metal electrode layer 18 having a suitable thickness includes printing by ink-jet printing or screen printing of a material paste, or plating. However, the present invention is not limited thereto, and when a vacuum process is used, vapor deposition or sputtering may be used.

The width of the comb-teeth in the p-type semiconductor layer 13p and the n-type semiconductor layer 13n may be the same as the width of the metal electrode layer 18 formed on the comb-teeth. The width of the metal electrode layer 18 may be narrower than the width of the comb teeth. In addition, as long as the metal electrode layers 18 are configured to prevent leakage current between them, the width of the metal electrode layers 18 may be larger than the width of the comb teeth.

In the present embodiment, a predetermined annealing treatment is performed in a state where the intrinsic semiconductor layer 12, the conductive semiconductor layer 13, the low reflection layer 14, and the electrode layer 15 are stacked on the back-side main surface 11SB of the crystal substrate 11 in order to passivate each bonding surface, suppress the occurrence of defect levels in the conductive semiconductor layer 13 and its interface, and crystallize the transparent conductive oxide in the transparent electrode layer 17.

The annealing treatment of the present embodiment includes, for example, an annealing treatment in which the crystal substrate 11 on which the above layers are formed is put in an oven heated to 150 to 200 ℃. In this case, the atmosphere in the oven may be the atmosphere, and further, if hydrogen or nitrogen is used, more effective annealing treatment can be performed. In addition, the annealing treatment may be RTA (Rapid thermal annealing) treatment in which the crystal substrate 11 on which each layer is formed is irradiated with infrared rays by an infrared heater.

[ method for producing solar cell ]

A method for manufacturing the solar cell 10 of the present embodiment will be described below with reference to fig. 3 to 9.

First, as shown in fig. 3, a crystal substrate 11 having a texture structure TX on each of the front main surface 11SU and the back main surface 11SB is prepared.

Next, as shown in fig. 4, an intrinsic semiconductor layer 12U, for example, is formed on the front main surface 11SU of the crystal substrate 11. Next, the low reflection layer 14 is formed on the formed intrinsic semiconductor layer 12U. From the viewpoint of blocking light, silicon nitride (SiN) having an appropriate light absorption coefficient and refractive index is used for the low reflection layer 14_X) Or silicon oxide (SiO)_X)。

Next, as shown in fig. 5, an intrinsic semiconductor layer 12p using, for example, i-type amorphous silicon is formed on the back-side main surface 11SB of the crystal substrate 11. Next, a p-type semiconductor layer 13p is formed on the formed intrinsic semiconductor layer 12 p. Thereby, the p-type semiconductor layer 13p is formed on the back-side main surface 11SB which is one main surface of the crystal substrate 11. As described above, in this embodiment, the step of forming the p-type semiconductor layer (1 st semiconductor layer) 13p includes a step of forming the intrinsic semiconductor layer (1 st intrinsic semiconductor layer) 12p on the one main surface (back side main surface) 11S of the crystal substrate (semiconductor substrate) 11 before forming the p-type semiconductor layer 13 p.

Thereafter, a peeling layer LF is formed on the formed p-type semiconductor layer 13 p. In the present embodiment, the peeling layer LF is composed mainly of an oxide. Specifically, the peeling layer LF is composed mainly of an oxide of 1 or more elements selected from indium (In), zinc (Zn), tin (SnO), aluminum (Al), and silicon (Si). The peeling layer LF does not have to be one of the above elementsOxide of 1 composition (e.g., indium oxide (InO)_X) For example, a 3-membered type such as indium-tin composite oxide, indium-aluminum composite oxide, indium-silicon composite oxide, zinc-tin composite oxide, zinc-aluminum composite oxide, aluminum-silicon composite oxide, or a 4-membered type such as indium-zinc-tin composite oxide, zinc-tin-silicon composite oxide, can be selected.

The peeling layer LF can be formed by a vacuum process, particularly a CVD method or a sputtering method. In these methods, the film quality can be controlled by the flow ratio of the raw material gas, the pressure, the voltage at the time of plasma discharge, and the like without largely changing the composition. Further, the etching characteristics in the film thickness direction may be adjusted by changing the deposition conditions in the film thickness direction. The structure of the oxide formed by the vacuum process is not particularly limited, and examples thereof include a structure in which a physical or chemical void (defect) is contained in the layer. If the peeling layer LF is formed by a vacuum process, the grown crystal grains grow so as to be stacked almost perpendicular to the film formation surface. In this case, many grains are formed from the grown crystal grains, and voids may be formed between the grains. In the case of the release layer LF having such a void, the etching solution easily enters the inside of the layer, and thus the etching rate may be increased. Therefore, the time for peeling described later can be shortened.

Next, as shown in fig. 6 and 7, the peeling layer LF and the p-type semiconductor layer 13p are patterned in the back-side main surface 11SB of the crystal substrate 11. This generates a non-formation region NA where the p-type semiconductor layer 13p is not formed. On the other hand, the peeling layer LF and the p-type semiconductor layer 13p remain in the unetched region on the back-side main surface 11SB of the crystal substrate 11.

In the steps of fig. 6 and 7, the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the peeling layer LF are removed by wet etching using 2 or more different etching solutions so that the areas of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p dissolved by etching (hereinafter referred to as etching areas) are equal to or smaller than the etching area of the peeling layer LF when viewed from the back-side main surface 11SB side in the direction perpendicular to the surface of the crystal substrate 11. More specifically, the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the peeling layer LF are removed so that the widths of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are equal to or larger than the width of the peeling layer LF when viewed from the back-side main surface 11SB side in the direction perpendicular to the surface of the crystal substrate 11.

In an actual process, as shown in fig. 6, the peeling layer is selectively removed by wet etching using a 1 st etching solution, and then, as shown in fig. 7, the intrinsic semiconductor layer 12 and the p-type semiconductor layer are selectively removed by wet etching using a 2 nd etching solution.

Such a patterning step can be realized by forming a resist film (not shown) having a predetermined pattern on the peeling layer LF by photolithography, for example, and etching a region masked by the formed resist film. As shown in fig. 6 and 7, patterning each of the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the peeling layer LF generates a non-formation region NA, that is, an exposed region of the back-side main surface 11SB in a partial region of the back-side main surface 11SB of the crystal substrate 11. The details of the non-formation region NA will be described later.

As the 1 st etching solution used in the step shown in fig. 6, for example, a strong acid etching solution such as hydrochloric acid or nitric acid can be used. On the other hand, as the 2 nd etching solution used in the step shown in fig. 7, for example, a solution in which ozone is dissolved in hydrofluoric acid (hereinafter, an ozone/hydrofluoric acid solution) can be used.

Note that the ozone/hydrofluoric acid solution as the 2 nd etching solution etches not only the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p but also the separation layer LF. Therefore, in the state after the step shown in fig. 7, the edge portion of the release layer LF in the width direction is retreated compared to the state after the step shown in fig. 6. This causes the edge of the peeling layer LF to recede from the edge of the p-type semiconductor layer 13 p. As a result, as shown in fig. 11, the widths of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are larger than or equal to the width of the peeling layer LF when viewed from the back-side main surface 11SB side in the direction perpendicular to the surface of the crystal substrate 11.

Next, as shown in fig. 8, the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are sequentially formed on the back-side main surface 11SB of the crystal substrate 11 in addition to the peeling layer LF, the type semiconductor layer 13p, and the intrinsic semiconductor layer 12 p. In this way, in this embodiment, the step of forming the n-type semiconductor layer (2 nd semiconductor layer) 13n includes a step of forming the intrinsic semiconductor layer (2 nd intrinsic semiconductor layer) 12n on the peeling layer LF including the crystal substrate (semiconductor substrate) 11 and the one main surface (back side main surface) 11S of the p-type semiconductor layer before forming the n-type semiconductor layer 13 n. Thus, the laminated film of the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n is formed so as to cover the surface and side surfaces (end surfaces) of the peeling layer LF and the side surfaces (end surfaces) of the peeling layer LF, the p-type semiconductor layer 13p, and the intrinsic semiconductor layer 12p in the non-formation region NA. Here, since the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed in a state where the end edge portion of the peeling layer LF is receded from the end edge portion of the p-type semiconductor layer 13p, as shown in fig. 8, a part of the intrinsic semiconductor layer 12n and a part of the n-type semiconductor layer 13n are formed so as to directly straddle the p-type semiconductor layer 13 p.

Next, as shown in fig. 9, the stacked peeling layer LF is removed using an etchant, whereby the n-type semiconductor layer 13n and the intrinsic semiconductor layer 12n covering the peeling layer LF are removed (peeled) from the crystal substrate 11. Here, the 2 nd intrinsic semiconductor layer and the 2 nd conductive semiconductor layer covering the peeling layer LF are peeled from the crystal substrate without dissolving them, and the peeling layer is removed. The etchant used for the patterning preferably uses a solvent that dissolves the peeling layer LF and does not dissolve the intrinsic semiconductor layer 12 and the conductive semiconductor layer 13. For example, the lift-off layer LF is formed of indium oxide (InO)_X) Or metal oxide such as zinc oxide (ZnO), the release layer LF may be formed of silicon oxide (SiO) using an acidic solution such as hydrochloric acid_X) Hydrofluoric acid may be used as the main component.

Next, as shown in fig. 10, for example, a transparent electrode layer 17(17p, 17n) is formed on the back-side main surface 11SB of the crystal substrate 11, that is, on the p-type semiconductor layer 13p and the n-type semiconductor layer 13n, respectively, by a sputtering method using a mask. Note that, instead of the sputtering method, the transparent electrode layer 17(17p, 17n) may be formed as follows. For example, a transparent conductive oxide film may be formed on the entire back-side main surface 11SB without using a mask, and then the remaining transparent conductive oxide film may be etched on the p-type semiconductor layer 13p and the n-type semiconductor layer 13n by photolithography.

Then, for example, a linear metal electrode layer 18(18p, 18n) is formed on the transparent electrode layer 17 using a mesh (not shown) having openings.

The back-bonding solar cell 10 is formed through the above steps.

(summarization and Effect)

The following can be concluded from the above-described method for manufacturing the solar cell 10.

First, in the step shown in fig. 9, if the separation layer LF is removed by an etching solution, the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n deposited on the separation layer LF are also removed from the crystal substrate 11 at the same time (so-called "separation"). In this step, as compared with the case where the photolithography method is used in the step shown in fig. 6, for example, a resist coating step and a developing step used in the photolithography method are not required. Therefore, the n-type semiconductor layer 13n can be easily patterned.

In the step of patterning the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the peeling layer LF, the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the peeling layer LF are removed by wet etching using 2 or more different etching solutions so that the etching areas of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are equal to or smaller than the etching area of the peeling layer LF when viewed from the back side of the surface of the crystal substrate 11 in the vertical direction. In this way, by performing etching so that the etching areas of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are smaller than or equal to the etching area of the peeling layer LF, the crystal substrate 11 is prevented from being exposed at the stage of forming the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13 n.

That is, if the etched area of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p is larger than the etched area of the peeling layer LF when viewed from the back side in the direction perpendicular to the surface of the crystal substrate 11, the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are in a state of receding from the peeling layer LF (a state of sidewall cutting). In this state, if the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed, the peeling layer LF functions as a mask, and a gap is generated between the side surface of the intrinsic semiconductor layer 12n and the side surfaces of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p on the non-formation region NA. Then, if the peeling layer LF, the intrinsic semiconductor layer 12p, and the p-type semiconductor layer 13p are formed, the back-side main surface 11SB of the crystal substrate 11 is exposed between the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p and the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13 n. If the back-side main surface 11SB of the crystal substrate 11 is exposed, the effective area in which holes and electrons can be collected is reduced by the exposed area, and therefore the performance of the solar cell is deteriorated.

On the other hand, if the separation layer LF is formed mainly of an oxide as in the present embodiment, the etching characteristics of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are greatly different from those of the separation layer LF. Further, by making the etching solution for etching the peeling layer LF different from the etching solution for etching the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p, the control of the etching area of each layer, particularly the accuracy of patterning in the width direction of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p, is improved. Thus, the etching areas of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are made smaller than or equal to the etching area of the peeling layer LF. As a result, the side surfaces of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p and the side surface of the peeling layer LF are flush with each other, or the peeling layer LF recedes from the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13 p. In this state, if the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed, the intrinsic semiconductor layer 12n is formed in contact with at least the side surfaces of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p, and thus exposure of the crystal substrate 11 is suppressed. Therefore, deterioration of the performance of the solar cell can be suppressed, and a high-performance solar cell can be manufactured.

Thus, according to the present embodiment, a high-performance back contact type solar cell can be efficiently manufactured.

As described above, in order to control the etching area of each layer, it is preferable that the etching rate of the 1 st etching solution used in the step shown in fig. 6 satisfies the following relational expression (1) and the etching rate of the 2 nd etching solution used in the step shown in fig. 7 satisfies the following relational expression (2),

the etching rate of the intrinsic semiconductor layer 12p is not more than that of the p-type semiconductor layer 13p < the etching rate of the lift-off layer LF (1).)

The etching rate of the intrinsic semiconductor layer 12p is not less than that of the p-type semiconductor layer 13p is not less than that of the peeling layer LF (2).

If the 1 st etching solution satisfies the above relational expression (1), the separation layer LF can be dissolved selectively and quickly in the step shown in fig. 6. When the second etching solution 2 satisfies the above relational expression (2), the separation layer LF is dissolved together with the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p in the step shown in fig. 7. Therefore, the etching area of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p is not larger than that of the peeling layer LF, and sidewall chipping of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p is less likely to occur.

The above-described relational expressions (1) and (2) can be satisfied by the kind of the etching solution or the concentration of the etching solution.

The thickness of the release layer LF is preferably 20nm to 500nm, particularly preferably 50nm to 250 nm. That is, if the film thickness of the peeling layer LF is too thick, insufficient etching or a reduction in productivity may occur in the step of fig. 6. In addition, if the film thickness of the peeling layer LF is too thick, undercut of an inverted wedge shape may occur in the peeling layer LF due to side etching. If undercut of the inverted wedge shape is generated in the peeling layer LF, the width of the peeling layer LF becomes narrower than the surface of the peeling layer LF as approaching the p-type semiconductor layer 13 p. Therefore, in the state after etching of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p, the edge portions of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are set back from the edge portion of the peeling layer LF on the side farthest from the p-type semiconductor layer 13 p. In this state, if the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed, the peeling layer LF functions as a mask as described above, and a gap is generated between the side surface of the intrinsic semiconductor layer 12n and the side surfaces of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p on the non-formation region NA, eventually exposing the crystal substrate 11. Therefore, the release layer LF needs to have a film thickness to prevent the undercut of the inverted wedge shape. On the other hand, if the film thickness is too thin, the peeling layer LF may be completely removed (peeled) when the peeling layer LF is patterned in the step shown in fig. 6, and thus a certain film thickness is required. Therefore, the thickness of the release layer LF is particularly preferably 20nm to 500 nm.

Further, the crystal substrate 11 has the texture TX, and each of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n formed on the back-side main surface 11SB of the crystal substrate 11 preferably includes a texture (texture 2) reflecting the texture TX.

If the conductive semiconductor layer 13 has the textured structure TX on the surface, the etching solution is likely to penetrate into the semiconductor layer 13 due to the irregularities of the textured structure TX. Therefore, the conductive type semiconductor layer 13 is easily removed, i.e., easily patterned.

In the present embodiment, the texture TX (1 st texture) is provided on both main surfaces 11S of the crystal substrate 11, that is, the front main surface 11SU and the back main surface 11SB, but may be provided on either main surface. That is, when the texture TX is provided on the front main surface 11SU, the light-capturing effect and the blocking effect of the received light are improved. On the other hand, when the texture structure TX is provided on the back-side main surface 11SB, the light extraction effect is improved and the conductive semiconductor layer 13 is easily patterned. Therefore, the texture structure TX of the crystal substrate 11 may be provided on at least one main surface 11S. In the present embodiment, the textures TX on both main surfaces 11S are formed in the same pattern, but the pattern is not limited to this, and the sizes of the irregularities of the textures TX may be changed on the front main surface 11SU and the back main surface 11 SB.

The technology disclosed herein is not limited to the above-described embodiments, and may be modified without departing from the scope of the claims.

For example, in the above-described embodiment, in the step shown in fig. 7, the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are patterned so that the widths of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are larger than the width of the peeling layer LF when viewed from the back side in the direction perpendicular to the surface of the crystal substrate 11, but the present invention is not limited thereto, and the patterning (etching) may be performed so that the widths of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are substantially the same as the width of the peeling layer LF (actually, the width of the peeling layer LF is slightly smaller). That is, when the widths of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are substantially the same as the width of the separation layer LF, the edge of the separation layer LF and the edge of the p-type semiconductor layer 13p are located at substantially the same position. In this state, if the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed, the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are not formed to directly straddle the p-type semiconductor layer 13p as shown in fig. 12. Thus, if the n-type semiconductor layer 13n and the intrinsic semiconductor layer 12n deposited on the peeling layer LF are removed from the crystal substrate 11 by removing the peeling layer LF, the n-type semiconductor layer 13n is not formed on the p-type semiconductor layer 13p, but is separated from the p-type semiconductor layer 13p in the width direction through the intrinsic semiconductor layer 12n, as shown in fig. 13. In this way, when the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are formed, it is preferable to form a separation groove at the boundary portion between the p-type semiconductor layer 13p and the n-type semiconductor layer 13n from the viewpoint of suppressing the generation of a leakage current.

In the above-described embodiment, the semiconductor layer used in the step shown in fig. 5 is the p-type semiconductor layer 13p, but the present invention is not limited thereto, and may be the n-type semiconductor layer 13 n. The conductivity type of the crystal substrate 11 is not particularly limited, and may be p-type or n-type.

The above embodiments are merely examples, and are not intended to limit the technical scope of the present disclosure. The technical scope of the present disclosure is defined by the claims, and modifications and variations that fall within the scope of equivalents of the claims are also within the technical scope of the present disclosure.