阅读说明：本技术 一种电磁阀控制装置及智能干选机 (Solenoid valve control device and intelligent dry separator ) 是由 梁兴国 王家祥 刘云峰 于 2020-06-22 设计创作，主要内容包括：本发明实施例公开了一种电磁阀控制装置及智能干选机。电磁阀控制装置包括通信模块、FPGA、多个电磁阀驱动模块及多个数字信号输出模块；FPGA通过通信模块与上位机连接,用于接收上位机发送的电磁阀控制信号；FPGA包括多路输出端口,输出端口与电磁阀驱动模块的输入端连接,电磁阀驱动模块的输出端与数字信号输出模块的输入端连接,数字信号输出模块的输出端与电磁阀连接；电磁阀驱动模块用于在FPGA的控制下驱动电磁阀开启或关闭；电磁阀驱动模块包括并联设置的至少两个MOS芯片。本发明实施例的技术方案,可以快速控制电磁阀的开启或关闭动作,达到精确控制电磁阀行为的目的。(The embodiment of the invention discloses a solenoid valve control device and an intelligent dry separator. The electromagnetic valve control device comprises a communication module, an FPGA, a plurality of electromagnetic valve driving modules and a plurality of digital signal output modules; the FPGA is connected with the upper computer through a communication module and is used for receiving the electromagnetic valve control signal sent by the upper computer; the FPGA comprises a plurality of output ports, the output ports are connected with the input end of the electromagnetic valve driving module, the output end of the electromagnetic valve driving module is connected with the input end of the digital signal output module, and the output end of the digital signal output module is connected with the electromagnetic valve; the electromagnetic valve driving module is used for driving the electromagnetic valve to open or close under the control of the FPGA; the electromagnetic valve driving module comprises at least two MOS chips which are arranged in parallel. According to the technical scheme of the embodiment of the invention, the opening or closing action of the electromagnetic valve can be rapidly controlled, and the aim of accurately controlling the action of the electromagnetic valve is achieved.)

1. The electromagnetic valve control device is characterized by being used for controlling a plurality of electromagnetic valves and comprising a communication module, a Field Programmable Gate Array (FPGA), a plurality of electromagnetic valve driving modules and a plurality of digital signal output modules;

the FPGA is connected with an upper computer through the communication module and is used for receiving the electromagnetic valve control signal sent by the upper computer;

the FPGA comprises a plurality of output ports, the output ports are connected with the input ends of the electromagnetic valve driving modules in a one-to-one correspondence manner, the output ends of the electromagnetic valve driving modules are connected with the input ends of the digital signal output modules in a one-to-one correspondence manner, and the output ends of the digital signal output modules are connected with the electromagnetic valves in a one-to-one correspondence manner;

the electromagnetic valve driving module is used for generating an electromagnetic valve driving signal according to the electromagnetic valve control signal under the control of the FPGA, and transmitting the electromagnetic valve driving signal to a corresponding electromagnetic valve through the digital signal output module so as to drive the electromagnetic valve to be opened or closed;

the electromagnetic valve driving module comprises at least two Metal Oxide Semiconductor (MOS) chips which are arranged in parallel.

2. The electromagnetic valve control device according to claim 1, further comprising a plurality of optical coupling isolation chips, wherein input ends of the optical coupling isolation chips are connected with output ports of the FPGA in a one-to-one correspondence manner, and output ends of the optical coupling isolation chips are connected with input ends of the electromagnetic valve driving modules in a one-to-one correspondence manner.

3. The solenoid valve control device according to claim 1, further comprising a plurality of analog-to-digital conversion modules;

the FPGA also comprises a plurality of output feedback detection ports, the input ends of the analog-to-digital conversion modules are correspondingly connected with the output ends of the electromagnetic valve driving modules one by one, and the output ends of the analog-to-digital conversion modules are correspondingly connected with the output feedback detection ports one by one;

the FPGA is also used for monitoring whether the output signal of the electromagnetic valve driving module is abnormal or not according to the signal received by the output feedback detection port.

4. The solenoid valve control device according to claim 1, further comprising a watchdog circuit and a clock reset circuit;

the first end of the watchdog circuit is connected with the FPGA, and the second end of the watchdog circuit is connected with the first end of the clock reset circuit;

the second end of the clock reset circuit is connected with the FPGA;

the watchdog circuit is used for receiving the dog feeding signal sent by the FPGA and sending a reset signal to the clock reset circuit when the dog feeding signal is not received;

the clock reset circuit is used for controlling the FPGA to reset when receiving the reset signal.

5. The solenoid valve control device according to claim 1, wherein n-stage solenoid valve control devices are provided in cascade;

the communication module comprises an uplink interface and a downlink interface, the uplink interface of the first-level solenoid valve control device is connected with an upper computer, and the uplink interface of the nth-level solenoid valve control device is connected with the downlink interface of the (n-1) th-level solenoid valve control device;

wherein n is not less than 2 and n is an integer.

6. The solenoid valve control device of claim 1, wherein the communication module comprises an ethernet communication module; the ethernet communication module includes an RJ45 interface and a port physical layer PHY chip.

7. The solenoid valve control of claim 1, wherein said communication module comprises any one of an RS-585 bus, an RS-232 bus, a PCI-E bus, or a RapidIO bus.

8. The electromagnetic valve control device according to claim 1, characterized in that the MOS chip is an ISP772T chip;

the electromagnetic valve driving module comprises a first MOS chip, a second MOS chip, a first resistor and a first capacitor;

the power supply end of the first MOS chip and the power supply end of the second MOS chip are connected with the first voltage end, the input end of the first MOS chip and the power supply end of the second MOS chip are connected with the output port of the FPGA, the output end of the first MOS chip and the first end of the first capacitor are connected, the second end of the first resistor is connected with the first grounding end, and the second end of the first capacitor is connected with the second grounding end.

9. The electromagnetic valve control device according to claim 2, wherein the optocoupler isolation chip is a TLP183 chip, and the TLP183 chip comprises a light emitting diode and a phototriode;

the positive electrode of the light emitting diode is connected with the output port of the FPGA, the negative electrode of the light emitting diode is connected with a third grounding end, the collector of the photosensitive triode is connected with the second voltage end, and the emitter of the photosensitive triode is connected with the input end of the electromagnetic valve driving module.

10. An intelligent dry separator, characterized by comprising the solenoid valve control device of any one of claims 1 to 9.

Technical Field

The embodiment of the invention relates to a solenoid valve control technology, in particular to a solenoid valve control device and an intelligent dry separator.

Background

The intelligent Dry Separator (TDS) utilizes ray and image recognition technology to identify coal and gangue, realizes accurate identification and separation of lump coal, and has the advantages of no water, simple process, less investment and low production cost.

The core of the TDS execution system comprises an electromagnetic valve injection system, wherein the electromagnetic valve injection system controls a plurality of air nozzles through a plurality of electromagnetic valves, and the movement of coal briquettes or gangue is controlled by utilizing the air outlet of the air nozzles. Tens to hundreds of electromagnetic valves need to be controlled to be opened or closed simultaneously in the TDS, the execution precision requirement of the action of the electromagnetic valves is within 1ms, meanwhile, the types of the electromagnetic valves used in the TDS are also a plurality, the driving power required by the electromagnetic valves of different types is different, and the prior art mainly adopts a Programmable Logic Controller (PLC) to drive and control the electromagnetic valves. Because PLC response time is slower, can't satisfy the control requirement, lead to the break-make of solenoid valve to have the condition of delay or advancing, influence the sorting precision of TDS.

Disclosure of Invention

The embodiment of the invention provides an electromagnetic valve control device and an intelligent dry separator, wherein the electromagnetic valve control device is based on a hardware platform of an FPGA (field programmable gate array), realizes quick communication with an upper computer through a communication module, can achieve the state updating speed of 100 microseconds, simultaneously can achieve the microsecond level of the response speed of an MOS (metal oxide semiconductor) chip, controls the opening or closing action of an electromagnetic valve, and achieves the purpose of accurately controlling the behavior of the electromagnetic valve.

In a first aspect, an embodiment of the present invention provides an electromagnetic valve control apparatus, configured to control a plurality of electromagnetic valves, where the electromagnetic valve control apparatus includes a communication module, a field programmable gate array FPGA, a plurality of electromagnetic valve driving modules, and a plurality of digital signal output modules;

the FPGA is connected with an upper computer through the communication module and is used for receiving the electromagnetic valve control signal sent by the upper computer;

the FPGA comprises a plurality of output ports, the output ports are connected with the input ends of the electromagnetic valve driving modules in a one-to-one correspondence manner, the output ends of the electromagnetic valve driving modules are connected with the input ends of the digital signal output modules in a one-to-one correspondence manner, and the output ends of the digital signal output modules are connected with the electromagnetic valves in a one-to-one correspondence manner;

the electromagnetic valve driving module is used for generating an electromagnetic valve driving signal according to the electromagnetic valve control signal under the control of the FPGA, and transmitting the electromagnetic valve driving signal to a corresponding electromagnetic valve through the digital signal output module so as to drive the electromagnetic valve to be opened or closed;

the electromagnetic valve driving module comprises at least two Metal Oxide Semiconductor (MOS) chips which are arranged in parallel.

Optionally, the system further comprises a plurality of optical coupling isolation chips, wherein the input ends of the optical coupling isolation chips are connected with the output ports of the FPGA in a one-to-one correspondence manner, and the output ends of the optical coupling isolation chips are connected with the input ends of the electromagnetic valve driving modules in a one-to-one correspondence manner.

Optionally, the system further comprises a plurality of analog-to-digital conversion modules;

the FPGA also comprises a plurality of output feedback detection ports, the input ends of the analog-to-digital conversion modules are correspondingly connected with the output ends of the electromagnetic valve driving modules one by one, and the output ends of the analog-to-digital conversion modules are correspondingly connected with the output feedback detection ports one by one;

the FPGA is also used for monitoring whether the output signal of the electromagnetic valve driving module is abnormal or not according to the signal received by the output feedback detection port.

Optionally, the clock circuit further comprises a watchdog circuit and a clock reset circuit;

the first end of the watchdog circuit is connected with the FPGA, and the second end of the watchdog circuit is connected with the first end of the clock reset circuit;

the second end of the clock reset circuit is connected with the FPGA;

the watchdog circuit is used for receiving the dog feeding signal sent by the FPGA and sending a reset signal to the clock reset circuit when the dog feeding signal is not received;

the clock reset circuit is used for controlling the FPGA to reset when receiving the reset signal.

Optionally, the n-level solenoid valve control devices are arranged in a cascade manner;

the communication module comprises an uplink interface and a downlink interface, the uplink interface of the first-level solenoid valve control device is connected with an upper computer, and the uplink interface of the nth-level solenoid valve control device is connected with the downlink interface of the (n-1) th-level solenoid valve control device;

wherein n is not less than 2 and n is an integer.

Optionally, the communication module includes an ethernet communication module; the ethernet communication module includes an RJ45 interface and a port physical layer PHY chip.

Optionally, the communication module includes any one of an RS-585 bus, an RS-232 bus, a PCI-E bus, or a RapidIO bus.

Optionally, the MOS chip is an ISP772T chip;

the electromagnetic valve driving module comprises a first MOS chip, a second MOS chip, a first resistor and a first capacitor;

the power supply end of the first MOS chip and the power supply end of the second MOS chip are connected with the first voltage end, the input end of the first MOS chip and the power supply end of the second MOS chip are connected with the output port of the FPGA, the output end of the first MOS chip and the first end of the first capacitor are connected, the second end of the first resistor is connected with the first grounding end, and the second end of the first capacitor is connected with the second grounding end.

Optionally, the optocoupler isolation chip is a TLP183 chip, and the TLP183 chip includes a light emitting diode and a light sensing triode;

the positive electrode of the light emitting diode is connected with the output port of the FPGA, the negative electrode of the light emitting diode is connected with a third grounding end, the collector of the photosensitive triode is connected with the second voltage end, and the emitter of the photosensitive triode is connected with the input end of the electromagnetic valve driving module.

In a second aspect, an embodiment of the present invention further provides an intelligent dry separator, including any one of the above electromagnetic valve control devices.

The electromagnetic valve control device provided by the embodiment of the invention comprises a communication module, an FPGA, a plurality of electromagnetic valve driving modules and a plurality of digital signal output modules; the FPGA is connected with the upper computer through a communication module to realize the rapid communication between the FPGA and the upper computer, and the FPGA is used for receiving the electromagnetic valve control signal sent by the upper computer; the FPGA comprises a plurality of output ports, the output ports are connected with the input ends of the electromagnetic valve driving modules in a one-to-one correspondence manner, the output ends of the electromagnetic valve driving modules are connected with the input ends of the digital signal output modules in a one-to-one correspondence manner, and the output ends of the digital signal output modules are connected with the electromagnetic valves in a one-to-one correspondence manner; the electromagnetic valve driving module is used for generating an electromagnetic valve driving signal according to the electromagnetic valve control signal under the control of the FPGA, and transmitting the electromagnetic valve driving signal to the corresponding electromagnetic valve through the digital signal output module so as to drive the electromagnetic valve to be opened or closed; the electromagnetic valve driving module comprises at least two Metal Oxide Semiconductor (MOS) chips which are arranged in parallel. By arranging the FPGA-based hardware platform, the FPGA and the upper computer can realize rapid communication at a 100 mu s level updating speed through the communication module, the electromagnetic valve driving module generates an electromagnetic valve driving signal according to the electromagnetic valve control signal, and the electromagnetic valve driving signal is output through the digital signal output module to control the opening or closing of the electromagnetic valve; the electromagnetic valve driving module comprises at least two MOS chips which are connected in parallel, the MOS chips have microsecond-level response speed, the power of the electromagnetic valve driving module can meet the driving requirement of the electromagnetic valve in a mode that the MOS chips are connected in parallel, and the purpose of quickly and accurately controlling the behavior of the electromagnetic valve is achieved.

Drawings

Fig. 1 is a schematic structural diagram of a solenoid valve control device according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of another solenoid valve control device provided in the embodiment of the present invention;

FIG. 3 is a schematic structural diagram of another solenoid valve control device provided in the embodiment of the present invention;

FIG. 4 is a schematic structural diagram of another solenoid valve control device provided in the embodiment of the present invention;

FIG. 5 is a schematic structural diagram of another solenoid valve control device provided in the embodiment of the present invention;

FIG. 6 is a schematic diagram of a cascade structure of a multi-solenoid valve control device according to an embodiment of the present invention;

fig. 7 is a schematic circuit structure diagram of a solenoid valve driving module according to an embodiment of the present invention;

fig. 8 is a schematic circuit structure diagram of an optical coupler isolation chip according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. It should be noted that the terms "upper", "lower", "left", "right", and the like used in the description of the embodiments of the present invention are used in the angle shown in the drawings, and should not be construed as limiting the embodiments of the present invention. In addition, in this context, it is also to be understood that when an element is referred to as being "on" or "under" another element, it can be directly formed on "or" under "the other element or be indirectly formed on" or "under" the other element through an intermediate element. The terms "first," "second," and the like, are used for descriptive purposes only and not for purposes of limitation, and do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

Fig. 1 is a schematic structural diagram of a solenoid valve control device according to an embodiment of the present invention. Referring to fig. 1, the solenoid valve control apparatus provided in the present embodiment is used for controlling a plurality of solenoid valves 100, and includes a communication module 10, a field programmable gate array FPGA20, a plurality of solenoid valve driving modules 30, and a plurality of digital signal output modules (DO) 40; the FPGA20 is connected with the upper computer 200 through the communication module 30, and the FPGA20 is used for receiving the electromagnetic valve control signal sent by the upper computer 200; the FPGA20 comprises a plurality of output ports 21, the output ports 21 are correspondingly connected with the input ends of the electromagnetic valve driving modules 30, the output ends of the electromagnetic valve driving modules 30 are correspondingly connected with the input ends of the digital signal output modules 40, and the output ends of the digital signal output modules 40 are correspondingly connected with the electromagnetic valves 100; the electromagnetic valve driving module 30 is used for generating an electromagnetic valve driving signal according to the electromagnetic valve control signal under the control of the FPGA20, and transmitting the electromagnetic valve driving signal to the corresponding electromagnetic valve 100 through the digital signal output module 40 to drive the electromagnetic valve 100 to open or close; the solenoid valve driving module 40 includes at least two metal oxide semiconductor MOS chips 31 arranged in parallel.

It is understood that the 4 solenoid valves 100 shown in fig. 1 are schematic, and in other embodiments, the number of the solenoid valves 100 may be designed according to actual requirements, for example, 8, 16, etc., and further more solenoid valves may be controlled in a cascade manner. The solenoid valve driving module 40 includes two MOS chips 31 arranged in parallel, which is only illustrative, and the number of the MOS chips 31 may be set according to the driving power of the actual solenoid valve in specific implementation, and optionally, the MOS chips 31 may be ISP772T chips. The ISP772T chip has the characteristics of quick response (microsecond magnitude) and large power (the current is greater than or equal to 1.5A), and the total output current can reach 3A by adopting a double-chip parallel connection mode, so that the driving capability of the electromagnetic valve is more than 99 percent.

According to the technical scheme of the embodiment, a hardware platform based on the FPGA is arranged, the FPGA and an upper computer can realize rapid communication at a 100 mu s-level updating speed through a communication module, an electromagnetic valve driving signal is generated by an electromagnetic valve driving module according to an electromagnetic valve control signal, and the electromagnetic valve driving signal is output through a digital signal output module to control the opening or closing of an electromagnetic valve; the electromagnetic valve driving module comprises at least two MOS chips which are connected in parallel, the MOS chips have microsecond-level response speed, the power of the electromagnetic valve driving module can meet the driving requirement of the electromagnetic valve in a mode that the MOS chips are connected in parallel, and the purpose of quickly and accurately controlling the behavior of the electromagnetic valve is achieved. All modules of the solenoid valve control device provided by the embodiment can be integrated on the same circuit board, the whole size is 100mm multiplied by 100mm, the solenoid valve control device is installed in a card type, a very large space cannot be occupied, and the solenoid valve control device is very suitable for application scenes in which dozens or even hundreds of solenoid valves are required to perform centralized control.

On the basis of the above technical solution, fig. 2 is a schematic structural diagram of another solenoid valve control device according to an embodiment of the present invention. Referring to fig. 2, optionally, the electromagnetic valve control device provided in this embodiment further includes a plurality of optical coupling isolation chips (OC) 50, an input end of each optical coupling isolation chip 50 is connected to the output port 21 of the FPGA20 in a one-to-one correspondence, and an output end of each optical coupling isolation chip is connected to an input end of the electromagnetic valve driving module 30 in a one-to-one correspondence.

It can be understood that the optical coupling isolation chip 50 is arranged between the FPGA20 and the solenoid valve driving module 30, so that the FPGA20 can be prevented from being directly electrically connected with the solenoid valve driving module 30, a reverse current which may be generated when the solenoid valve driving module 30 drives a solenoid valve can be prevented from flowing into the FPGA20, and the safety performance of the solenoid valve control device can be improved. Optionally, the optical coupling isolation chip 50 may be a TLP183 chip, and may be selected according to actual requirements in specific implementation.

Fig. 3 is a schematic structural diagram of another solenoid valve control device according to an embodiment of the present invention. Referring to fig. 3, optionally, the solenoid valve control device provided in this embodiment further includes a plurality of analog-to-digital conversion modules (ADCs) 60; the FPGA20 further includes a plurality of output feedback detection ports 22, the input end of the analog-to-digital conversion module 60 is connected with the output end of the solenoid valve driving module 30 in a one-to-one correspondence, and the output end is connected with the output feedback detection ports 22 in a one-to-one correspondence; the FPGA20 is also used to monitor whether the output signal of the solenoid driver module 30 is abnormal according to the signal received by the output feedback detection port 22.

It can be understood that, by setting the analog-to-digital conversion module 60, the output end of each solenoid valve driving module 30 has a state acquisition signal, and the actual working state of the solenoid valve can be judged by acquiring the current state of the channel and comparing with the normal value of the type of solenoid valve preset in the factory, and the judgment results of the states of the solenoid valve such as disconnection, short circuit, blockage and the like are provided, so that the maintenance of the solenoid valve is facilitated.

Fig. 4 is a schematic structural diagram of another solenoid valve control device according to an embodiment of the present invention. Referring to fig. 4, optionally, the solenoid valve control apparatus provided in this embodiment further includes a watchdog circuit 70 and a clock reset circuit 80; the first end of the watchdog circuit 70 is connected with the FPGA20, and the second end is connected with the first end of the clock reset circuit 80; the second end of the clock reset circuit 80 is connected with the FPGA 20; the watchdog circuit 70 is configured to receive a dog feeding signal sent by the FPGA20, and send a reset signal to the clock reset circuit 80 when the dog feeding signal is not received; clock reset circuit 80 is used to control FPGA20 to reset upon receipt of a reset signal.

By arranging the watchdog circuit 70 and the clock reset circuit 80, the FPGA20 can be reset when the FPGA20 fails (for example, dead cycle), so that the working stability of the solenoid valve control device is improved.

It should be noted that, in specific implementation, the optional modules in the foregoing embodiments may be combined with each other to meet the requirements of different application scenarios. Fig. 5 is a schematic structural diagram of another solenoid valve control device according to an embodiment of the present invention. Referring to fig. 5, the solenoid valve control device provided in this embodiment includes a communication module 10, an FPGA20, a solenoid valve driving module 30, a digital signal output module (DO) 40, an optical coupling isolation chip (OC) 50, an analog-to-digital conversion module (ADC) 60, a watchdog circuit 70, and a clock reset circuit 80, and optionally, the communication module 10 includes an ethernet communication module; the ethernet communication module includes an RJ45 interface 11 and a port physical layer PHY chip 12. The upper computer 200 is connected with an RJ45 interface 11, and the RJ45 interface 11 is connected with the FPGA20 through the PHY chip 12, so that microsecond-level rapid communication can be realized. In specific implementation, the RJ45 interface can be HR911205C, and the PHY chip can be LAN8720AI-CP-TR chip.

In other embodiments, optionally, the communication module may include any one of an RS-585 bus, an RS-232 bus, a PCI-E bus, or a RapidIO bus, and the specific implementation may be selected according to actual requirements, which is not limited in this embodiment of the present invention.

In the practical application process, due to the number of ports, the bearing power of a single device and the like, the number of the electromagnetic valves which can be controlled by one electromagnetic valve control device may not meet the practical application requirements, and if a plurality of electromagnetic valve control devices are connected with an upper computer, the upper computer is required to comprise a plurality of communication interfaces, so that the cost is not reduced. The electromagnetic valve control device provided by the embodiment can also adopt a multi-device cascade mode. For example, fig. 6 is a schematic diagram illustrating a cascade structure of a multi-electromagnetic valve control device according to an embodiment of the present invention. Referring to fig. 6, alternatively, n-stage solenoid valve control devices 300 are arranged in cascade; the communication module comprises an uplink interface 301 and a downlink interface 302, the uplink interface 301-1 of the first-level electromagnetic valve control device 300-1 is connected with the upper computer 200, and the uplink interface 301-n of the nth-level electromagnetic valve control device 300-n is connected with the downlink interface 302-n-1 of the nth-1-level electromagnetic valve control device 300-n-1; wherein n is not less than 2 and n is an integer.

When a single electromagnetic valve control device controls 16 electromagnetic valves, and the cascade number is 64, the control requirement of a single system of 1024 electromagnetic valves can be met. In a specific implementation, both the uplink interface 101 and the downlink interface 102 may adopt an RJ45 interface, and in other embodiments, other communication interfaces may also be selected, which is not limited in the embodiment of the present invention.

On the basis of the foregoing embodiments, for example, fig. 7 is a schematic circuit structure diagram of a solenoid valve driving module according to an embodiment of the present invention. Referring to fig. 7, the MOS chip is an ISP772T chip, and the solenoid valve driving module includes a first MOS chip U1, a second MOS chip U2, a first resistor R1, and a first capacitor C1; the power supply ends of the first MOS chip U1 and the second MOS chip U2 are both connected to the first voltage terminal VCC1, the input end D1IN is connected to the output port of the FPGA, the output end OUT is connected to the first end of the first resistor R1 and the first end of the first capacitor C1, the second end of the first resistor R2 is connected to the first ground terminal GND1, and the second end of the first capacitor C2 is connected to the second ground terminal GND 2.

The ISP772T chip comprises four power supply terminals Vbb 1-Bbb 4 which are all connected with a first voltage terminal VCC1, the voltage of the first voltage terminal VCC1 can be 24V, the input ends and the output ends of a first MOS chip U1 and a second MOS chip U2 are respectively connected in parallel, a first grounding terminal GND1 is an analog grounding terminal, a first resistor R1 is used for AD isolation, and a second grounding terminal GND2 is a shielding grounding terminal and used for shielding signal interference.

Exemplarily, fig. 8 is a schematic diagram of a circuit structure of an optical coupler isolation chip according to an embodiment of the present invention. Referring to fig. 8, the optocoupler isolation chip is a TLP183 chip, and the TLP183 chip includes a light emitting diode D and a photo transistor T; the positive pole of the light emitting diode D is connected with the output port of the FPGA, the negative pole of the light emitting diode D is connected with a third grounding end GND3, the collector of the phototransistor T is connected with a second voltage end VCC2, and the emitter of the phototransistor T is connected with the input end D1IN of the electromagnetic valve driving module.

Two optical coupling isolation chips are shown in fig. 8, a second resistor R2 is further arranged between the optical coupling isolation chips and the output end of the FPGA, and no two optical coupling reasonable chips share one 8P4R patch exclusion RN, so that circuit structure packaging is facilitated.

The embodiment of the invention also provides an intelligent dry separator which comprises any one of the electromagnetic valve control devices provided by the embodiment.

It can be understood that the intelligent dry separator provided by the embodiment can be used for intelligently separating coal and gangue, an intelligent identification method is adopted, an analysis model suitable for different coal quality characteristics is established according to the different coal quality characteristics, the coal and gangue are digitally identified through big data analysis, and finally the gangue is discharged through an intelligent execution system; the system comprises four main systems of a feeding system, a distributing device, a recognition device and an execution mechanism, and three auxiliary systems of an air supply system, a dust removal system and an electric control system; the feeding system is positioned at the feeding end of the distributing system, and raw materials are uniformly fed onto the distributing device by the feeding system; the identification device is an X-ray source positioned above the material distribution device and an X-ray detector positioned below the material distribution device; the actuating mechanism is an array air nozzle with an outlet facing to the motion track of the clean coal and the gangue, each air nozzle controls air injection through an electromagnetic valve, and the opening and the closing of the electromagnetic valve are controlled and executed by adopting any electromagnetic valve control device provided by the embodiment. The electromagnetic valve control device has the characteristic of quickly and accurately controlling the behavior of the electromagnetic valve, can be integrated on the same circuit board, has the overall size of 100mm multiplied by 100mm, is installed in a card type, does not occupy very large space, and is very suitable for application scenes that dozens or even hundreds of electromagnetic valves are needed to carry out centralized control in an intelligent dry separation machine.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.