Voltage matched multijunction solar modules made of 2D materials

文档序号：1146315 发布日期：2020-09-11 浏览：12次中文

阅读说明：本技术 2d材料制成的电压匹配的多结太阳能模块 (Voltage matched multijunction solar modules made of 2D materials ) 是由莫西·埃那夫于 2019-01-23 设计创作，主要内容包括：一种电压匹配的太阳能模块,用于将入射的太阳辐射转换为电能,太阳能模块由多个晶圆尺寸的多结太阳能设备和与模块尺寸的底部基板相邻的布线电路组成。每个太阳能设备具有至少两个由电绝缘的透明层隔开的光伏(PV)电池。PV电池被对齐以重叠并且通过导电通孔电连接到布线电路。布线电路包括并联电连接并具有基本相同电压的多个串行串。公开了一种生产太阳能模块的方法,其利用ALD/LPCVD工具对2D材料进行范德华外延。(A voltage matched solar module for converting incident solar radiation to electrical energy is comprised of a plurality of wafer-sized multijunction solar devices and a wiring circuit adjacent to a module-sized base substrate. Each solar device has at least two Photovoltaic (PV) cells separated by an electrically insulating transparent layer. The PV cells are aligned to overlap and are electrically connected to the wiring circuit by conductive vias. The wiring circuit includes a plurality of serial strings electrically connected in parallel and having substantially the same voltage. A method of producing a solar module is disclosed that utilizes an ALD/LPCVD tool to perform van der waals epitaxy on 2D materials.)

1. A voltage matched solar module for converting incident solar radiation into electrical energy, characterized by: sequentially comprises the following steps:

a plurality of wafer-sized multijunction solar devices, each solar device comprising:

a first Photovoltaic (PV) cell that first receives the incident solar radiation;

an electrically insulating transparent layer;

a second PV cell that receives the incident solar radiation after the first PV cell; and

a packaging layer; and

a wiring circuit, a bottom substrate adjacent to the module size,

wherein:

the first PV cell and the second PV cell each comprise two transparent electrodes and a p-n junction;

the first and second PV cells are aligned to overlap and are electrically connected to the wiring circuit by conductive vias; and

the wiring circuit includes a plurality of serial strings electrically connected in parallel and having substantially the same voltage.

2. The solar module of claim 1, wherein: the wiring circuit includes at least two serial strings electrically connected to the first PV cell.

3. The solar module of claim 1, wherein: the voltage is equal to a number of devices in the plurality of solar devices multiplied by an open circuit voltage of the second PV cell.

4. The solar module of claim 1, wherein: each solar device includes a monolithic stack of a plurality of pellicles comprising a two-dimensional (2D) material.

5. The solar module of claim 4, wherein: the plurality of thin films are held together by van der waals forces, and the 2D material includes at least one of a semiconductor, a conductor, and an insulator.

6. The solar module of claim 4, wherein: the 2D material includes at least one of inorganic, organic, and metal-organic materials having an amorphous, polycrystalline, or single crystal structure.

7. The solar module of claim 4, wherein: the 2D material is a crystalline film, either lamellar or non-lamellar.

8. The solar module of claim 1, wherein: the first and second PV cells absorb short and long wavelength solar radiation, respectively, and the bandgap of the p-n junction of the first PV cell is wider than the bandgap of the p-n junction of the second PV cell.

9. The solar module of claim 1, wherein: the p-n junction comprises a 2D semiconductor material having a direct bandgap transition.

10. The solar module of claim 1, wherein: the p-n junction includes an n-region and a p-region that together form a type II band alignment.

11. The solar module of claim 1, wherein: the p-n junction comprises a material selected from the group consisting ofA semiconductor material of the group comprising: chemical groups V and VI, chemical groups I-II-IV-VI, I-III-VI, I-IV-VI, IV-VI, I-VI, II-VI, III-IV, III-V, IV-III-V, IV-VI, V-VI, FeS₂And perovskite compounds.

12. The solar module of claim 1, wherein: the electrode comprises a two-dimensional layered conductor selected from the group consisting of graphene, metal halides, metal chalcogenides, metal oxides and metal nitrides.

13. The solar module of claim 1, wherein: the conductor adjacent the n-type semiconductor comprises n-type material and the conductor adjacent the p-type semiconductor comprises p-type material.

14. The solar module of claim 1, wherein: each conductive via is enclosed within an insulative sleeve and terminated on the encapsulation layer with a pad.

15. The solar module of claim 14, wherein: the conductive via and the pad comprise a material selected from the group consisting of a metal, a metal alloy, graphene, a metal halide, a metal chalcogenide, a metal oxide, and a metal nitride.

16. The solar module of claim 14, wherein: the electrically insulating transparent layer and the insulating sleeve comprise at least one 2D material, the at least one 2D material being selected from hexagonal boron nitride; metalloids and metals with halides, oxides, nitrides and metal oxynitrides.

17. The module of claim 1, wherein: the base substrate is a module-sized flexible or solid sheet that shields the solar module from its surroundings and comprises plastic, glass, composite material, or stainless steel coated with a dielectric film.

18. The module of claim 1, wherein: the base substrate includes a metal film for reflecting solar radiation not absorbed by the first and second PV cells for re-absorption and forming the wiring circuit.

19. The solar module of claim 18, wherein: the metal film includes a metal or a metal alloy, and is minimally processed to form the wiring circuit so that most of the metal film can function as a reflector.

20. The module of claim 1, wherein: also included is a module-sized top laminate that shields the solar module from its surroundings and includes transparent plastic or glass, anti-reflective coatings, and micro-scale pyramids.

21. The module of claim 1, wherein: the p-n junction of the second PV cell is replaced by an n-p junction.

22. The module of claim 1, wherein: the p-n junction of the first PV cell is replaced by an n-p junction.

23. A method of manufacturing a voltage matched solar module, characterized by: the method comprises the following steps:

(a) providing a module-sized base substrate;

(b) depositing a wiring circuit on the base substrate;

(c) providing a vapor deposition system comprising an Atomic Layer Deposition (ALD) mode and a Low Pressure Chemical Vapor Deposition (LPCVD) mode;

(d) providing a crystallographic template to process the wafer;

(e) fabricating a wafer-sized multi-junction solar device, including metallization;

(f) connecting the multijunction solar device to the bottom substrate and removing the handle wafer;

(g) repeating steps (d), (e) and (f) to produce a plurality of solar devices; and

(h) a top laminate is fabricated and attached over a plurality of solar devices.

24. The method of claim 23, wherein: step (e) further comprises the sequential steps of:

(i) performing ALD/LPCVD to form a first PV cell, further comprising:

(a) ALD of the first transparent electrode;

(b) placing a baffle having a first shape over a small portion of the first transparent electrode;

(d) LPCVD of p-n junctions;

(e) ALD of the second transparent electrode;

(f) placing another baffle having a first shape over a small portion of the second transparent electrode; and

(g) ALD of an electrically isolating layer;

(ii) (ii) repeating step (i) to form additional PV cells;

(iii) replacing a plurality of baffles having a first shape with a plurality of baffles having a second shape, the second shape being smaller than the first shape;

(iv) ALD of an encapsulation layer comprising a sleeve for a through-hole;

(v) removing all the baffles;

(vi) removing the processed wafer and the grown layer from the vapor deposition system;

(vii) physically masking to determine the positions of the electrical pads corresponding to the positions of the through holes; and

(viii) physical Vapor Deposition (PVD) is used to metalize the vias and pads.

25. The method of claim 23, wherein: the step of depositing wiring circuitry on the base substrate is: by a technique selected from the group consisting of photolithography and etching, physical mask deposition and printing.

26. The method of claim 23, wherein: the vapor deposition system includes a cluster tool or integrated tool having an ALD mode and an LPCVD mode capable of growth in a controlled atmosphere.

27. The method of claim 26, wherein: the vapor deposition system also includes a plurality of fittings: for rotating the handle wafer, for heating the growing film by radiant heat, and for exciting gas atoms or molecules by remote plasma, UV lamps or lasers.

28. The method of claim 23, wherein: the crystallography template processing wafer comprises a single crystal or an epitaxial and full-grown single crystal, and the material of the single crystal is selected from graphite, mica and CaF₂、Si、Ge、Ni、Pt、Ir、Ru、GaAs、GaP、MgO、Al₂O₃SiC, and carbides of Ta, Ti, Zr, Hf, and Nb.

29. The method of claim 28, wherein: passivating a surface of the single crystal by a chemical method selected from the group consisting of hydrogenation, fluorination, oxidation, sulfidation, nitridation, electroplating, and graphitization to form a van der Waals surface.

30. The method of claim 24, wherein: the step of connecting the multijunction solar device to the base substrate comprises: electrical contact is made between the metallized pads and the wiring circuit.

31. The method of claim 24, wherein: the ALD step of the first transparent electrode is preceded by ALD of a protective 2D crystalline insulating layer.

32. The method of claim 24, wherein: the plurality of baffles comprise a coin-shaped magnetic material encapsulated in a ceramic material.

33. The method of claim 24, wherein: a thin semiconductor seed layer is epitaxially grown on the van der waals surface of the transparent electrode until a continuous film is obtained.

34. The method of claim 24, wherein: the plurality of baffles are operated by electromagnets attached to the bellows shaft.

Technical Field

The present invention relates to photovoltaic modules and their manufacture, and more particularly to voltage matched multijunction solar modules.

Background of the invention

The voltage-matched multijunction solar module is composed of a plurality of voltage-matched multijunction solar cells (VMMJSC) connected in series. Each VMMJSC is a vertical stack of two or more photovoltaic cells (hereinafter "PV cells") separated by a dielectric layer, each photovoltaic cell absorbing a different wavelength or color of the incident solar radiation spectrum. Typically, the uppermost PV cell absorbs the short solar wavelengths corresponding to the blue and green color bands, i.e., the photovoltaic cell that receives solar radiation first, while the longer solar wavelengths corresponding to the red and infrared bands are absorbed by the PV cells deeper in the vertical stack or stacks. In this document, reference is made to directions such as highest, deepest, top, bottom and variants thereof. These directional references are exemplary, and show the disclosed subject matter in an exemplary orientation, and are in no way limiting.

Various wiring configurations for voltage-matched multijunction solar cells have been proposed in the prior art, hereinafter referred to as "solar modules". For example, U.S. patent No. 9,287,431 to Mascarenhas and Alberi, 3/15/2016, hereinafter referred to as MA'431, discloses a thin film voltage matched multijunction solar cell and method of producing a cell with an upper p-n junction layer of CdTe formed on a transparent substrate that is operably disposed in a super configuration in the completed device. As another example, U.S. patent publication No. 2015/0340528a1 to Alberi and Mascarenhas, dated 26/11/2015, discloses a thin film voltage matched multijunction solar cell and method of manufacturing a cell producing a first p-n junction (p-njunction) having a first band gap energy, a second p-n junction having a second band gap energy, and an insulating layer between the first and second p-n junctions.

In the prior art, the p-n junctions of different PV cells do not completely overlap. As a result, the manufacture of each PV cell requires its own dedicated mask for the trench, metallization, and encapsulation. This increases the complexity and cost of the manufacturing process.

There is a great need for a solar module in which all PV cells are completely overlapped, as this can be a streamlined manufacturing process. Disclosed are a solar cell module having PV cells that are completely overlapped and do not cause a decrease in efficiency due to shading of electrodes, and a manufacturing method using Van der Waals (vdW) epitaxy, which is performed by Atomic Layer Deposition (ALD) and Low Pressure Chemical Vapor Deposition (LPCVD).

Disclosure of Invention

The present invention is a voltage matched solar module for converting incident solar radiation into electrical energy and a method of fabricating a solar module using ALD/LPCVD tools for van der Waals epitaxy (van der Waals epi) of 2D materials.

The solar module is comprised of a plurality of wafer-sized multijunction solar devices and a wiring circuit adjacent to a module-sized base substrate. Each solar device has at least two Photovoltaic (PV) cells separated by an electrically insulating transparent layer. The PV cells are aligned to overlap and are electrically connected to the wiring circuit by conductive vias. The wiring circuit includes a plurality of serial strings electrically connected in parallel and having substantially the same voltage.

The method for producing a solar module consists of the following sequence of steps:

(a) providing a module-sized base substrate;

(b) depositing a wiring circuit on the base substrate;

(c) providing a vapor deposition system comprising an Atomic Layer Deposition (ALD) mode and a Low Pressure Chemical Vapor Deposition (LPCVD) mode;

(d) providing a crystallographic template processing wafer (crystallographic template handle wafer);

(e) fabricating a wafer-sized (wafer-sized) multi-junction solar device, including metallization;

(f) connecting the multijunction solar device to the bottom substrate and removing a handle wafer (handlewafer);

(g) repeating steps (d), (e) and (f) to produce a plurality of solar devices; and

(h) a top laminate is fabricated and attached over a plurality of solar devices.

Brief description of the drawings

The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein:

fig. 1(a) and 1(b) are diagrams illustrating solar modules with non-overlapping PV cells according to the prior art.

Fig. 2(a) and 2(b) are diagrams illustrating an exemplary solar module with overlapping PV cells according to the principles of the present invention for comparison with the prior art of fig. 1(a) and 1 (b).

Fig. 3(a) to 3(d) are schematic views illustrating a first exemplary embodiment of a solar module having a four-wafer-size multi-junction solar device.

Fig. 4(a) to 4(d) are schematic views illustrating a second exemplary embodiment of a solar module having a multi-junction solar device of twenty-four wafer size.

Fig. 5 is a block diagram illustrating steps of an exemplary manufacturing method for manufacturing a solar module according to the present invention.

Fig. 6(a) to 6(x) are a series of schematic diagrams illustrating steps of the exemplary manufacturing method of fig. 5.

Detailed description of the preferred embodiments

Fig. 1(a) and 1(b) are diagrams of a solar module according to the prior art, as disclosed in fig. 1 and 2 of MA'431, for example. In fig. 1(a) and 1(b), solar radiation photons of energy h ν are incident on the solar module 1, wherein "h" is the planck constant and "ν" is the photon frequency inversely proportional to the photon wavelength. The first and second p-n junctions 2 and 4, respectively, are separated by an electrically insulating transparent layer 5. The band gap energy of the p-n junction 2 is greater than the band gap energy of the p-n junction 4. Thus, photons of short solar wavelengths are absorbed in the p-n junction 102, and photons of long solar wavelengths pass through the p-n junction 2 and the transparent layer 5 and are absorbed by the p-n junction 4. The upper layer 8 consists of three p-n junctions 2 and the lower layer 10 consists of five p-n junctions 4.

Fig. 1(b) shows a wiring diagram of a solar module 1 according to the prior art. Three diodes (denoted by 2') corresponding to the p-n junction 2 are electrically connected in series to form an upper string. Similarly, five diodes corresponding to p-n junctions 4, denoted by 4', are connected in series to form a lower string. Finally, the two strings are connected in parallel to form two terminal devices, as shown in fig. 1 (b).

Voltage matching is achieved by selecting the materials of the p-n junctions 2 and 4 so that the combined output voltage of the upper string is approximately equal to the output voltage of the lower string. Note, however, that the area of p-n junction 4 is approximately 3/5 times the area of p-n junction 2; thus, the p-n junction of the upper layer 8 does not completely overlap the p-n junction of the lower layer 10. As a result, the manufacturing process is complex, requiring many different photolithographic masks and processing steps.

Fig. 2(a) and 2(b) are diagrams of an exemplary solar module with overlapping PV cells according to the principles of the present invention as compared to the prior art. Incident solar radiation photons of energy hv are incident on a solar module 50, said solar module 50 consisting in sequence of an upper layer of four p-n junctions 52, an electrically insulating transparent layer 55 and a lower layer of four p-n junctions 58. As previously mentioned, photons at short solar wavelengths are preferentially absorbed at the upper layer, and photons at long solar wavelengths are preferentially absorbed at the lower layer.

Fig. 2(b) shows a wiring diagram of the solar module 50. The four diodes 52 'corresponding to the four p-n junctions 52 are divided into two upper strings 52A, each upper string 52A consisting of two diodes 52' connected in series. The two upper strings 52A are connected in parallel at point P. Four diodes 58' corresponding to the four p-n junctions 58 are connected in series to form a single lower string. Finally, a single lower string is connected in parallel with the two upper strings 52A at point Q to form two terminal devices. The total output current is the sum of the individual output currents of the lower string and the two upper strings and varies with daily and seasonal fluctuations in solar intensity.

The voltage matching in fig. 2(b) is achieved by selecting the materials of the p-n junctions 52 and 58 so that the output voltage of each upper string 52A is approximately equal to the voltage of the lower string. For example, assume that each diode 52 'outputs 2 volts and each diode 58' outputs 1 volt. The combined voltage of the lower string is equal to 4x 1-4 volts; the combined voltage of each upper string 52A is equal to 2x 2-4 volts, which is the same as the output voltage of the lower string.

Fig. 2(a) and 2(b) differ from the prior art in that:

(a) the p-n junction of the upper layer is completely overlapped with the p-n junction of the lower layer;

(b) the number of p-n junctions of the two layers is the same; and

(c) voltage matching is achieved by dividing the upper layer diodes into more than one parallel string (two in this case).

The meaning of the above-mentioned differences between the present invention and the prior art is profound. First, the solar module 50 can be assembled by fabricating four individual multijunction solar devices 51, each consisting of two p-n junctions, separated by an electrically insulating transparent layer. Because the p-n junctions are completely overlapped, the solar device 51 can be fabricated onto the entire surface of the wafer in one continuous process. Second, because solar device 51 is flat, without grooves, an uninterrupted process consists of stacking successive layers of conductive, semiconductive, and insulative materials in a single continuous pass without the need for etching or photolithography. Third, solar device 51 is a monolithic crystal in which all of the p-n junctions, conductors, and insulators are crystalline, using epitaxial growth processes such as Atomic Layer Deposition (ALD) and van der waals (vdW) epitaxy, as opposed to prior art solar devices in which only one semiconductor layer in the stack is crystalline and the other semiconductor layers are polycrystalline or amorphous. This is particularly important in view of the fact that crystalline PV cells are known to have approximately twice the energy conversion efficiency as polycrystalline or amorphous PV cells. Fourth, the continuous process for manufacturing the solar device 51 includes conductive vias and pads that lead to the back (bottom) of the device. The solar module 50 is then assembled by bringing the solar devices 51 into electrical contact with the wiring circuit mounted on the protective module-sized base substrate. In this way, there is no metal grid to front shade the device, which is an advantage over the prior art where shading is a significant cause of reduced solar energy conversion efficiency.

The principles of the present invention are illustrated in more detail in fig. 3(a) to 3 (d). A schematic diagram of a first exemplary embodiment of a multi-junction solar energy device 110 having four wafer sizes is shown in accordance with the present invention.

Fig. 3(a) is a cross-sectional view of a solar module 100 receiving solar radiation photons of energy hv from above. The photons pass through the module-sized transparent top laminate 101 and into a plurality of four wafer-sized multijunction solar devices 110 in electrical contact with wiring circuits 111 that are in physical contact with a module-sized bottom substrate 112. Each solar device 110 is comprised of two PV cells 102 and 108, separated by an electrically insulating transparent layer 105.

Fig. 3(b) is a top view of the solar module 100, wherein four solar devices 110 are arranged in a 2x 2 array. The lateral dimension LD of the solar device 110 corresponds to the size of a semiconductor wafer, which is typically 2, 4, 6, 8, or 12 inches wide. The lateral dimension LM of the solar module 100 is about twice the dimension LD.

Fig. 3(c) shows a diagram of the wiring circuit 111 of the solar module 100. The wiring circuit is composed of two serial strings 102A and a single serial string 108A connected in parallel with each other. Each serial string 102A is a series connection of two diodes 102' corresponding to two PV cells 102. The single serial string 108A is a series connection of four diodes 108' corresponding to the four PV cells 108. The serial string 102A and the serial string 108A have substantially the same voltage and are electrically connected in parallel.

As a numerical example, assume that each diode 102 'outputs two volts and each diode 108' outputs one volt. The combined voltage of serial string 108A is equal to 4x 1-4 volts. The combined voltage of each serial string 102A is 2 × 2 ═ 4 volts, which is the same as the output voltage of serial string 108A.

Fig. 3(d) is a vertical cross section showing the respective layers and the through-hole of the solar module 100. Starting from top to bottom, the solar device 110 consists of two PV cells 102 and 108, which are separated by an insulating transparent layer 105. The PV cell 102 consists of two conductive electrodes 102c and a p-n junction aligned by a staggered (type II) heterostructure or formed of n-doped and p-doped semiconductor layers 102n and 102p, respectively. Similarly, the PV cell 108 is composed of two conductive electrodes 108c and a p-n junction formed by type II alignment or n-doped and p-doped semiconductor layers 108n and 108p, respectively. The key difference between the two PV cells is that the bandgap width of the p-n junction of the PV cell 102 is wider than the bandgap width of the PV cell 108.

In alternative embodiments of the solar power plant 110, the location of the n-type semiconductor may be interchanged with the location of the p-type semiconductor in the PV cell 102 or the PV cell 108.

The conductive electrodes 102c and 108c are electrically connected to the wiring circuit 111 by means of conductive vias 102v and 108v, which terminate in conductive pads (connecting pads) under the insulating encapsulation layer 105E.

Fig. 4(a) to (d) show schematic views of a multijunction solar device 210 having a twenty-four wafer size according to a second exemplary embodiment of the present invention.

Fig. 4(a) is a cross-sectional view of a solar module 200 receiving solar radiation photons of energy hv from above. The photons pass through the module-sized transparent top laminate 101 and into a plurality of twenty-four wafer-sized multi-junction solar devices 210, which are in electrical contact with wiring circuits 211, which are in physical contact with the module-sized bottom substrate 112. Each solar device 210 comprises four PV cells 202, 204, 206 and 208, which are isolated from each other by an insulating transparent layer 105.

Fig. 4(b) is a top view of a solar module 200 in which twenty-four solar devices 210 are arranged in a 2x12 array. As shown in fig. 3(b), the lateral dimension LD of the solar device 210 corresponds to the dimension of a semiconductor wafer, which is typically 2, 4, 6, 8, or 12 inches wide. The lateral dimensions LM1 and LM2 of solar module 200 are approximately twice and twelve times the dimension LD, respectively.

Fig. 4(c) shows a schematic diagram of the wiring circuit 211 of the solar module 200. The wiring circuit is composed of the following components:

(a) four series strings 202A in parallel, each series string being a series connection of 6 diodes 202', corresponding to 6 PV cells 202;

(b) three parallel series strings 204A, each series string being a series connection of 8 diodes 204', corresponding to 8 PV cells 204;

(c) two parallel series strings 206A, each series string being a series connection of 12 diodes 206', corresponding to 12 PV cells 206; and

(d) one serial string 208A, which is a series connection of 24 diodes 208', corresponds to 24 PV cells 208.

The serial strings 202A, 204A, 206A, and 208A have substantially the same voltage and are electrically connected in parallel.

As a numerical example, assume that each diode 202' outputs 1.6 volts; each diode 204' outputs 1.2 volts; each diode 206' outputs 0.8 volts; each diode 208' outputs 0.4 volts. The output voltage of serial string 202A is 6x1.6 ═ 9.6V; the output voltage of serial string 204A is 8x1.2 ═ 9.6V; the output voltage of serial string 206A is 12x 0.8-9.6V; the output voltage of serial string 208A is 24 × 0.4 — 9.6V. Thus, all of the serial strings have substantially the same output voltage.

Fig. 4(d) is a vertical cross-section showing the respective layers and through-holes of the solar module 200. Starting from top down, the solar power device 210 includes four PV cells 202, 204, 206, and 208, separated by an electrically insulating transparent layer 105. Each PV cell consists of a pair of conductive electrodes (202c, 204c, a pair (pair) of 206c and 208 c) and a p-n junction formed by an n-type semiconductor layer (202n, 204n, 206n and 208n) and a p-type semiconductor layer (202p, 204p, 206p and 208 p). The n-type and p-type pair can be realized by a staggered (type II) alignment of the two semiconductor materials, also by a slight transfer of composition or by n-doping or p-doping the semiconductor.

Typically, the p-n junctions of the PV cells 202, 204, 206, and 208 have monotonically decreasing band gap widths and provide preferential absorption of solar radiation photons in the blue, green, red, and infrared spectral bands, respectively.

In an alternative embodiment of the solar power device 210, the position of the n-doped semiconductor may be interchanged with the position of the p-doped semiconductor in any of the PV cells 102, 104, 106, and 108.

It is evident that the use of wiring circuits with series strings connected in parallel can be extended from solar modules with 2x12 solar devices to solar modules with 6x12 solar devices. In the latter case, using the diode output voltage as in the numerical example above, the output voltage of the various serial strings will be equal to 72x 0.4-28.8V.

The diode output values used in the above numerical example can be generalized to solar devices having any number of PV cells and solar modules having any number of solar devices by using the following algorithm.

(i) The number of photovoltaic cells (N) in each solar device is selected. For example, for the first exemplary embodiment, N ═ 2, and for the second exemplary embodiment, N ═ 4.

(ii) The open circuit voltage of the bottom photovoltaic cell (i.e., the photovoltaic cell with the smallest bandgap width) is set to approximately Voc 1-1.8/N volts. This is also the voltage increment between two adjacent PV cells.

(iii) The required solar module output voltage (Vm) is set. The number of solar devices (M) in a solar module is estimated by an integer close to Vm/Voc1, which can be divided equally by the numbers 1 to N.

(iv) The value of Voc1 is reset to be equal to Vm/M. Voc1 and Vm are iterated (iterative) to obtain the optimal values.

(v) Open circuit voltages of other PV cells are determined.

(vi) The band gap is estimated and the semiconductor material is selected for all PV cells.

As a numerical example, please consider the case where N is 3 (step (i)). Next, Voc1 is set to 1.8/3 to 0.6 volts (step (ii)). Next, Vm is set to 24 volts, and M is estimated to (24/0.6) to 40. To divide M equally by 1,2 and 3, M is selected to be 42 (step (iii)), the value of Voc1 is reset to 24/42 to 0.57 volts (step (iv)), the open circuit voltage of the second PV cell is set to 2x0.57 to 1.14 volts, the open circuit voltage of the third PV cell is set to 3x0.57 to 1.71 volts (step (v)), the band gap is estimated to be Eg1 to 0.57+0.4 to 0.97eV, Eg2 to 1.14+0.4 to 1.54eV and Eg3 to 1.71+0.4 to 2.11 eV. to make p-n junctions with these band gaps.

The conductive electrodes 202c, 204c, 206c, and 208c are electrically connected to the wiring circuit 211 through the conductive vias 202v, 204v, 206v, and 208v, respectively. The conductive vias terminate at conductive pads under the insulating encapsulation layer 105E.

In an exemplary embodiment, the size and material of the wiring circuits 111 and 211 are preferably selected so as to reflect solar photons that are not absorbed in the first pass through the solar devices 110 and 210, respectively. Upon reflection, these photons gain a second chance of being absorbed, thereby increasing the overall conversion efficiency of the solar module.

The module-sized base substrate 112 is preferably made of plastic, glass, composite or stainless steel with an additional dielectric layer to prevent electrical contact with the wiring circuit.

Materials:

as shown in detail in fig. 3(d) and 4(d), the layers of the solar devices 110 and 210 include three materials, namely, an insulator, a conductor, and a semiconductor. Preferably, these layers should be monolithically stacked in a superposition (Superstrate) mode, should be crystalline and transparent under the appropriate solar spectrum, and should be thin films with a minimum thickness so that they can function with maximum efficiency. Growing a crystalline upper layer (super-layer) of a different material is called heteroepitaxy (heteroepitaxy), which is limited to a small lattice mismatch. Materials with large mismatch can be grown epitaxially using vdW. When a layered material is grown on the cleavage plane of another layered material or on a three-dimensional material substrate (e.g., Si or GaAs), a vdW interface may be formed if the dangling bonds (dangling bonds) on its surface are capped with appropriate atoms to render it inert.

Van der Waals (vdW) epitaxy was invented by Atsushi Koma et al and is in the journal of Microelectronic Engineering (Microelectronic Engineering) (Vol.2, 1984, p.129). Growth of a planar three-dimensional (3D) material film on two-dimensional (2D) material on mica has been demonstrated as described in the journal of nano-scale (Nanoscale), 2016, stage 8, page 11375. In order to expand the range of materials and phases that can be used to build heterostructures, it is highly desirable to have an approval for Koma's method and use vdW epitaxy. In this way, two chemically non-reactive crystal surfaces can be matched to form a monolithic structure with little regard to the lattice constant of their composition. Such non-reactive crystal surfaces can be found naturally in 2D layered materials, but also artificially in saturated surfaces of 3D materials.

The 2D layered material consists of crystalline flat plates stacked vertically like the pages in a book. The slab (slab) may comprise a single layer, e.g. hexagonal boron nitride (h-BN), or a single crystal of a binary, ternary or quaternary compound, e.g. Bi₂Sb₃A thickness of 3 to about

Between adjacent plates is about 3.5 angstromsSpaced apart by the internal space of vdW. The plates are held together firmly by covalent or ionic chemical bonds and are about 100 times stronger than the vdW force between adjacent plates. To be chemically inert, the surface of the 2D plate must be smooth and free of dangling bonds extending therefrom. The attractive force vdW between adjacent plates is generated by slightly overlapping electron orbits.

Saturated or "terminated" 3D material surfaces are very common, for example, silicon surfaces may be terminated with hydrogen, fluorides, sulfides, selenides, nitrides, and other materials. The GaAs surface may be end-capped with selenide, H-Ga, and other materials. Experimental evidence suggests that 3D materials such as GaN, GaAs, CdTe, GeAsSe, PbSnSe tend to grow in the form of 2D layered materials or so-called "planar 3D layered materials" or "2D non-layered materials" when grown on 2D layered materials. Koma calls it "Quasi-vdW epitaxy (Quasi vdW epitax)". It appears that almost any 2D or 3D material can be grown as a layered material if grown on a passivated and smooth 2D material surface.

The electrically insulating transparent layer 105 separating adjacent PV cells may comprise a wide bandgap 2D material, such as halides, oxides, nitrides of groups IA, IIA, IIIA, IVA, IIIB, IVB, e.g. MgBr₂，SrIF，BaIF，ScBr₃，YI₃，CdI₂(ii) a 2D oxide: graphene oxide, P₄O₁₀；Ti_0.87O₂，LaNb₂O₇，(Ca，Sr)₂Nb₃O₁₀，CaLaNb₂TiO₁₀，La₂Ti₂NbO₁₀ZnO, ZnS and nitrides, such as hexagonal boron nitride (h-BN). h-BN is preferred for its electrical insulating properties, exceptional optoelectronic properties as well as mechanical strength, thermal stability and chemical inertness. The dielectric constant of h-BN is 1.8, the dielectric strength of h-BN is 700KV/mm, as with Teflon, and 173KV/mm compared with Teflon.

The conductive electrode of the solar module of the present invention may include a halide of vanadium, AlCl₂，YGaI，Ag₂ReCl₆，CuS，FeLiP，FeS，FeTe，SbSiNi，ZnIn₂S₄，Zn₂In₂S₅(ii) a Transition Metal Dihalides (TMDC) of Y, Ti, V, Nb, Ta, Cr, Co, Rh, Ir, Ni, preferably graphene (Gn) nanoplatelets. Gn is 10 on a boron nitride substrate⁵cm²Semi-metal (semi-metal) with electron mobility μ of/V-s is 60 times higher than silicon and 1400 times higher than Indium Tin Oxide (ITO). Gn has a resistivity of 10^-8Omega-m, about 60% of silver. The original Gn is a p-type conductor with work functionIt was 4.7 eV. In order to convert it to an n-type material (as in the cathode), Gn is doped with nitrogen. Optimal doping can be achieved by incorporating N atoms into the graphene honeycomb network. Gn is transparent to solar radiation spectrum and has transparency of 97.7% of the total weight of the composition. The thickness of graphene is only 0.34 nanometers (nm). Experiments show that Gn can stabilize the 2D form of traditional 3D binary compounds. When the Gn electrode surrounds a p-n junction, Gn also has the advantage of acting as an "epitaxial catalyst" as shown in fig. 3(d) and 4 (d).

The photoactive absorbing material comprising a p-n junction is a single crystal direct bandgap 2D semiconductor or a 2D non-layered material with low exciton binding energy. The advantage of a single crystal structure is that it has fewer defects, such as grain boundaries and dislocations, which tend to reduce the fill factor (fill factor) by recombination and extinction of free carriers (annihilation). Typically, a single crystal absorber is twice as efficient as a mock polycrystalline material.

The direct bandgap transition ensures a high absorption coefficient and thus translates into a thin thickness. In order to be used as an absorber for photovoltaic cells, the semiconductor should maintain its direct transition at a significant thickness. Just like TMDC (e.g. MoS)₂) That is, a direct transition in a monolayer alone is not sufficient to provide sufficient absorption. Thus, the absorber should be a direct semiconductor with a thickness in the range of a few hundred nanometers. The low binding energy of the excitons ensures a high open circuit voltage (Voc) and rapid diffusion of the photo-carriers to the electrodes. In general, 3D and thicker 2D layered materials have lower binding energies. To ensure absorption of a large solar spectrum, the semiconductor bandgap (Eg) should be between about 2.4eV to about 0.5 eV.

The field of 2D layered and non-layered (3D) planar materials is expanding rapidly. To date, it contains about 700 different materials, a large portion of which are semiconductors. Most semiconductors in the chemical family provide alloying, thereby facilitating bandgap engineering. For example, in groups III-VI, GaSe (Eg ═ 1.9eV) can be alloyed with GaSe (Eg ═ 1.65eV) to produce GaSe with an intermediate Eg of 1.70eV_0.4Te_0.6。

Table 1 below is a list of exemplary 2D and 3D semiconductor materials that may be used for the p-n junction in the PV cells of the present invention. The band gap of these materials has a direct transition and has an energy in the range of 0.5-2.5 eV.

Table 1:

table 1 (continuation):

in the case of 2D layered materials, the formation of p-n junctions is different from typical 3D semiconductors (e.g., silicon or III-V group materials). In the 3D case, junctions (junctions) are formed by doping bulk or thin film single crystals with donor and acceptor elements. A larger intermediate region is created in the transition region from the n-type conductivity region to the p-type conductivity region due to the doping technique (implantation, diffusion, etc.) and/or epitaxial transition from one compound to another, requiring a crystallographically-matched transition region. On the other hand, a p-n junction with 2D material is formed by simply stacking heterogeneous materials to form an abrupt heterojunction. A pair of semiconductors with narrow type II staggered heterojunctions facilitates charge separation, which is necessary for high efficiency PV cells. In the staggered arrangement, the two bandgaps are in offset positions, with the n-type having a lower energy and the p-type having a higher energy. For 2D layered materials, it is relatively easy to find p-n pairs because the band offset of the junction of the stacked layers follows the anderson's electron affinity rule as described in Yuzheng Guo and John Robertson, applied physics Letters, 2016, volume 108, 233104. For example, the same metal component in a compound, but with a heavier chalcogenide element, will shift it to a p-type position as compared to an n-type. For example, InSe is n-type and intee is p-type. Even a very small substitution of Se for Se in InSe shifts the band, resulting in InSe/InSe_0.9Te_0.1Pairs can reach n-p junctions.

Another PV cell alternative is graphene/2D absorbing Schottky junctions (Schottky junctions). Highly p-doped Gn and n-doped Gn surround a multi-plate semiconductor. Can convert electrons intoAn intermediate layer of barrier h-BN is interposed between the p-Gn and the absorber to create an effective Schottky junction. The absorber is typically n-type (i.e., InSe) and the "schottky metal" is a graphene layer in which some of the carbon atoms in the mesh are replaced by boron atoms. In addition, nitric acid (HNO) may be used₃) Other doping methods are performed.

Exemplary material layers:

in fig. 4(d), the solar device 210 has a stack of four PV cells, each having two electrodes and a p-n junction. The electrically insulating transparent layer 105 and the encapsulation layer 105E separating adjacent PV cells are preferably made of h-BN. The electrodes of the PV cell are preferably made of Gn.

The four PV cells 202, 204, 206, and 208 preferentially absorb solar radiation photons in the blue, green, red, and infrared bands, respectively.

The PV cell 202 that first receives solar radiation preferably includes an n-p junction with a band gap width of about 2.0eV, which is designed to provide an open circuit voltage (Voc) of about 1.6V. In this case, the absorptive n-layer 202n may include In₂S₃(Eg. 2.1eV), the absorptive p-layer 202p may include In₂(Se_xS_1-x)₃。

The PV cell 204 preferably includes an n-p junction having a bandgap width of about 1.6eV, which is designed to provide a Voc of about 1.2V. In this case, the absorptive n-layer 204n may include Sb₂S₃(Eg ═ 1.63eV), the absorbing p-layer 204p may include Sb₂(Se_xS_1-x)₃。

The PV cell 206 preferably includes an n-p junction having a bandgap width of about 1.2eV, which is designed to provide a Voc of about 0.8V. In this case, the absorptive n-layer 206n may include Bi₂S₃(Eg ═ 1.3eV), the absorbing p-layer 206p may include Sb₂Se_xS_3-x。

The PV cell 208 preferably includes an n-p junction having a bandgap width of about 0.8eV, which is designed to provide a Voc of about 0.4V. In this case, the absorptive n-layer 206n may be made of Pb_xSn_1-xSe (Eg ═ 0.85eV), and the absorbing layer 206p may include Pb_ySn_1-ySe, wherein y is greater than x.

The conductive vias 202v, 204v, 206v and 208v are preferably made of copper, which draws the diode output voltage to pads on the underside of the encapsulation layer 105E.

The preparation method comprises the following steps:

fig. 5 is a block diagram illustrating steps of an exemplary manufacturing method for manufacturing a solar module according to the present invention.

Step 400A is to provide a module sized base substrate 112. Step 400B is to deposit wiring circuit 111 onto base substrate 112.

Step 400C provides a vapor deposition system capable of Atomic Layer Deposition (ALD) and Low Pressure Chemical Vapor Deposition (LPCVD). The system generally includes a cluster tool having a load lock apparatus, an ALD chamber and an LPCVD chamber all connected in a vacuum system to control the atmosphere. Alternatively, an integrated ALD/LPCVD tool in which ALD and LPCVD functions are performed in one chamber.

To achieve LPCVD, the ALD/LPCVD chamber should have an additional heating source to achieve the high temperatures required for reaction and annealing. For example, a "ceiling" radiant quartz illumination heater may be used. Moreover, such heaters can extend the "window" of the ALD process by rapidly changing the temperature between individual reactions. The ALD/LPCVD chamber may include a light source such as an LED or laser; remote plasma module (remote plasma module). The light source may cause a photochemical reaction and activation of gaseous species. The remote plasma can provide reactive species (radicals) that can reduce the temperature and thermal budget of the growing film. The ALD mode is designed to epitaxially grow thin layers of transparent conductors, insulators, and semiconductor seed layers. The semiconductor layer is much thicker than the other layers and the semiconductor body is grown epitaxially fast using LPCVD since the ALD process is rather slow. Another fitting in an ALD chamber is a bellows shaft (bellow) extending from the top of the ALD chamber. Electromagnets attached to the ends of the bellows shaft facilitate mask manipulation during via processing. Another accessory that facilitates mask handling is a rotary heater station for the template wafer.

Step 400D provides a crystallographic template for processing the wafer. Step 400E is to fabricate a wafer-sized multi-junction solar device, such as 110 or 210, including metallization for conductive electrodes and vias. Step 400F is to connect the solar device to the wiring circuit 111 on the base substrate 112 and remove the wafer process. Step 400G is a process of repeating steps 400D through 400F to fabricate a plurality of solar devices. Finally, step 400H is to fabricate and attach the top laminate 101 on a plurality of solar devices to form a solar module.

Step 400E is further divided into the following sequence of substeps:

(i) performing ALD/LPCVD to form a first PV cell, further comprising the steps of:

(a) ALD of the first transparent electrode;

(b) placing a baffle having a first shape (i.e., cylindrical) over a small portion of the first transparent electrode;

(d) LPCVD of p-n junctions;

(e) ALD of the second transparent electrode;

(f) placing a baffle having a first shape over a small portion of the second transparent electrode;

and

(g) ALD of an electrically isolating layer;

(ii) (ii) repeating step (i) to form a second PV cell;

(iii) replacing a plurality of baffles having a first shape with a plurality of baffles having a second shape (e.g., conical) that is smaller than the first shape;

(iv) ALD of a bottom encapsulation layer comprising a sleeve for a through via;

(v) removing the baffle;

(vi) removing the processed wafer and the overgrown layer thereof from the ALD/LPCVD tool;

(vii) physically masking to determine the positions of the electrical pads corresponding to the positions of the through holes; and

(viii) physical Vapor Deposition (PVD) is used to metalize the vias and pads.

Fig. 6(a) - (x) are a series of schematic diagrams illustrating a manufacturing process 600 for manufacturing the solar device 110 depicted in fig. 3(a) through 3 (d). These figures can be easily expanded to produce more complex solar devices 210 as shown in fig. 4(a) to 4 (d).

The fabrication process 600 begins by introducing a crystalline wafer into an ALD chamber. The PV cell 102 is grown first, followed by the electrically insulating transparent layer 105, the PV cell 108 and the encapsulation layer 105E. Epitaxial layers are grown continuously without opening the ALD chamber, with a mask placed over the Gn electrode for the via. In one of the last steps (as shown in fig. 6 (v)), the wafer with the overgrown film is connected to the wiring circuit 111 on the bottom substrate 112 of the solar module 100. The template wafer is removed and reinstalled on the ALD chamber before the top laminate 101 is applied and another run is performed.

Reference numerals used in fig. 6(a) to 6 (x). Different from those used in fig. 2(a) to 4(d), in order to avoid possible confusion between similar elements having slightly different shape representations.

In fig. 6(a), a single crystal wafer 602 is placed in an ALD chamber to serve as a recyclable processing template for an MJSD film. The wafer may be substantially any single crystal surface or the epitaxially grown material may be selected from materials that can withstand processing temperatures up to about 600 c. This list may include, but is not limited to, pyroxene Graphite (pyrolitic Graphite), mica, CaF₂(111)，Si(111)，Si(110)，Si(100)，SiC，Ge(111)，Ge(110)，GaAs(111)，GaAs(100)，Al₂O₃TaC (111), TaC (001), TiC (111), ZrC, HfC, NbC (111), Ni (111), Ni (001), Pt (111). To be a substrate for the h-BN layer that initiates the MJSD stack, the wafer should obtain a flat and dangling keyless surface. Although graphite and mica are naturally such 2D dangling unbonded substrates that van der waals (vdW) epitaxial 2D/2D crystals can be grown, modifications must be made to the 3D wafer to achieve quasi van der waals (QvdW) epitaxy. In QvdW epitaxy, 2D crystals are grown on 3D crystals, where the surface of the 3D wafer has fixed free radicals or dangling bonds, which must be saturatedAnd (c) and (d). This may be accomplished by surface treatment or the film 604 may include hydrogenation (Ge: H), fluorination, sulfidation, nitridation, phosphatization, arsenization, antimonization, electroplating, graphitization, and the like. As is known in the art, oxide or other contaminants are removed prior to loading the wafer onto the ALD tool. An argon plasma clean may be performed prior to growth in the ALD chamber into which the plasma module enters.

In fig. 6(b), a package 2D crystal layer 303 may be grown. Its function is to ensure the safety of the latter Gn electrode, since it will be exposed to the surrounding atmosphere after the completion of the multijunction solar device stack. The preferred material is h-BN. The ALD precursor of h-BN can be, but is not limited to, tris (ethylmethylaminoborane (TEMAB, C)₉H₂₄BN₃) Used as the reaction solution at 250 ℃ and 300 ℃ with NH₃Precursors for h-BN synthesis with co-reactants of plasma, as described by Park, h. et al, "large-scale synthesis of uniform hexagonal boron nitride films by plasma-enhanced atomic layer deposition", journal of scientific reports, volume 7, page 40091; doi:10.1038/srep40091(2017) (Sci. Rep.7, 40091; doi:10.1038/srep40091 (2017). Again, BN can pass through BBr₃And NH₃Deposition, as described in american chemical society for applied materials and interfaces (applied. mater. interfaces), 2017, 9(19), pages 16669 to 16678; and BN can be by BCl₃And NH₃Deposition, as described by Langmuir, 2016, 32, pages 2601 to 2607. Other precursors of BN are ammonia borane, NH₃-BH₃Borazine, B₃H₆N₃And Diborane (Diborane) B₂H₆And ammonia; borane (Borazene) (H)₂B--NH₂) (ii) a Trichloroborazine (Trichloroborazine), Cl₃B₃N₃H₃；B₁₀H₁₄/NH₃Trimethyl borate (trimethyl borate), B (OMe)₃And the like.

In fig. 6(c), an n-doped graphene layer 311 is grown on the h-BN layer 303. A wide variety of graphene precursors can be used, such as any organic species including alkanes, alkenes, aryl, acetylene, formic acid, benzene, hexane, oils, polymers, and the like.Plasma enhanced ALD for use of benzene and H at 400 deg.C₂The plasma grows graphene as first and second reactants, respectively, as described in journal of materials chemistry C (j.mater.chem.c), 2014, 2 nd, page 7570. Another precursor may be acetylene. To add doping nitrogen to the graphite honeycomb, ammonia, hydrazine, nitrogen or ammonia plasma may be used, for example, methylamine may be used for ammonia.

In fig. 6(d), a physical mask 606 is placed on Gn layer 311 to expose electrical contact to cathode 311. The mask does not allow any deposition at this location. The mask material may be any ceramic material, graphite, boron nitride, stainless steel, or other different material that does not react or dope the device. The mask is a magnetic material in the shape of a coin, encapsulated in a ceramic material, with a diameter ranging from 1 mm to 30 mm, depending on the wafer size. The mask is placed on the wafer without opening the ALD chamber.

In fig. 6(e), an n-type photosensitive absorber 312 is grown on the Gn surface. Any material in table 1 with a sufficient bandgap may be used as the n-type material. Each material is a compound of a cation of a group 13 metal Ga, In or a group 15 metalloid As, Sb or Bi with a group 16 chalcogen (chalcogenide) anion such As S, Se or Te. The deposition sequence was as follows: in III-VI materials, the order in a single slab is X/M/M/X, where M is a metal or metalloid and X is a chalcogenide. E.g., InSe is actually In₂Se₂A flat sheet, consisting of four layers: Se/In/Se. M₂X₃The material comprises five layers: X/M/X/M/X. ALD precursors may be, but are not limited to:

for Ga and In: metal alkyls, e.g. trimethylgallium, Ga (CH)₃)₃(ii) a Amide ligands, e.g. hexakis (dimethylamino) digallium (Ga)₂(NMe₂)₆) β diketone compounds (beta diketonate) such as indium acetylacetonate (iridium acetate), halides such as InCl₃(ii) a NN 'diisopropylacetamide salt (InIII) (NN' diisopropyracetamidate (InIII)). The halide contributes to high temperature growth, thereby improving crystallinity.

For arsenic: AsH of arsine gas₃(ii) a An alkyl group, a carboxyl group,(CH₃)₃(ii) a Aryl radical, AsPh₃(ii) a Tert-butyliminoarsine (tert-butylimine arsine).

For antimony: halide, SbCl₃(ii) a Amino, tris (dimethylamino) antimony (tris (dimethylamino) antimony), Sb (N (CH)₃)₂)₃(ii) a Alkyl radical (CH)₃)₃Sb。

For chalcogenides: elements S, Se; hydrides, H₂S，H₂Se; alkyl, diisopropyltellurium (diisopropyltellurium), Te (C)₃H₇)₂(ii) a Aryl, SPh₂(ii) a Hydrosilicosilane Se (SiH3) 2; silyl groups: (SiMe)₃)Se，(SiEt₃)2Se，(SiMe₃)₂Te，(SiEt₃)₂Te, and the like. Higher temperatures are preferred for better crystallinity and are facilitated by smaller precursor molecules.

Returning to fig. 6(e), an epitaxial seed layer of about 1nm is grown by ALD mode and then switched to LPCVD mode to perform most of this layer. The n-type absorber 312 is As having an Eg of 1.78eV₂Se₃. The ALD layer sequence for a plate is Se/As/Se/As/Se. Will SeH₂The gas is introduced into the chamber at a wafer temperature of about 350 deg.c. After nitrogen purge, AsH was introduced₃The gas reacts with the absorbed Se to release H₂A gas. N is a radical of₂Purging allows repeated cycles of depositing the Se layer, the As layer and the last Se layer to obtain As₂Se₃. Obtaining an As₂Se₃The process of plate layering can be repeated 5 to 300 times to obtain the desired number of plates. To save time, As is grown by ALD mode only₂Se₃While the entire thickness is achieved in a chamber or integrated tool (cluster tool) connected to the ALD tool by means of LPCVD mode.

As shown in FIG. 6(f), at 312As₂Se₃A p-type absorber 313 is grown on the slab layer. To obtain an Eg and type II band alignment of 1.7eV (for p-n junctions), at the same As₂Se₃Doping the flat layer with Te: as₂(Te_xSe_1-x)₃. Growth details are similarIn FIG. 6(e), except that the SeH is introduced before the ALD chamber₂Gas and TeH₂Gas mixing (by Al)₂Te₃Reaction with HCl to produce H₂Te gas). Note that one, two or three selenium tablets may be mixed. Likewise, As₂(Te_xSe_1-x)₃The total number of plate layers may be different from As₂Se₃The number of layers.

In FIG. 6(g), after returning to ALD mode, at₂(Te_xSe_1-x)₃The absorber is ALD grown with a graphene monolayer 314. The Gn layer may be p-doped with boron acceptor atoms. This can be achieved by adding B to the graphene precursor₂H₆(diborane), borane or BCl₃To be executed.

In fig. 6(h), the mask 608 is positioned to form a contact to the Gn layer of fig. 6 (g). The details are the same as in fig. 6 (d).

Fig. 6(i) shows the growth of a 2D hexagonal boron nitride layer 301 that electrically isolates PV cells 310 and 320. The h-BN layer is produced in the ALD chamber using boron/nitrogen precursors, as shown in FIG. 6 (b).

Fig. 6(j) shows the production of graphene anode 321 in PV cell 320, which is similar to the production of anode 314 in fig. 6 (g). In figure (k), a mask 610 is introduced to expose the contacts to the anode 321 of figure 6(j), similar to figure 6 (d).

Fig. 6(l) shows ALD/LPCVD growth of a p-type photosensitive infrared absorber 322(Eg ═ 1.0eV) of a PV cell 320, which may be In₂Te₃. This 2D layer is essentially a (Te-In-Te) plate, repeated 50 to 200 times. The precursor of Te may be TeH₂. The indium precursor may be trimethylindium, In (CH)₃)₃(ii) a Halides, e.g. InCl₃。In₂Te₃Growing the seed layer by an ALD mode; LPCVD mode is used for continuous growth.

Fig. 6(m) shows the corresponding n-type absorber 323 of the PV cell junction 120 fabricated in LPCVD mode. InTe_1- _xSe_xCan be an absorbing material, the Eg of which should be 0.9 eV. Such a 2D absorber consists of 50-200 In (Te1-xSex) plates, with two indium layers sandwiched between two Te_1-xSe_xBetween the individual layers: (Te)_1-xSe_x-In-In-Te_1-xSe_x). Can be In two sandwich layers or with one of them (e.g., Te-In-Se)_xTe_1-x) Some substitutions (x) in Se with Se were done. First, a chalcogenide Te layer may be deposited. The precursors of tellurium and selenium are the same as in fig. 6 (f). Then, two indium layers are deposited, since the indium precursor may be the same as in fig. 6 (l). Finally, deposit Te_1-xSe_xLayers to complete the plate. Or, if Te is to be grown in all plates_1-xSe_xSe in (e) instead of (x), the entire growth can be done using a fast LPCVD mode.

Fig. 6(n) shows the growth of graphene layer 324 as the cathode of PV cell 320. In an n-type absorber InTe_1- _xSe_xOn the surface of which N-doped graphene is grown. The details are shown in FIG. 6 (c).

In fig. 6(o), a mask 612 is placed to expose the contacts to the cathode 324 of fig. 6(n), the details of which are the same as in fig. 6 (d). In FIG. 6(p), masks 606, 608, and 610 are removed to make room for the new mask of FIG. 6(q) that will replace them. To release the masks from the film covering them, a simple bush (bushing) can be used to resist the pull-out of the electromagnetic shaft.

In fig. 6(q), new masks 606 ', 608 ', and 610 ' are placed in the remaining apertures of masks 606, 608, and 610. The masks 606 ', 608 ', 610 ' have the form of cone valves or poppet valves (also referred to as mushroom valves). The idea is to allow the h-BN layer of fig. 6(r) to conformally coat the vertical surfaces of the remaining holes of masks 606, 608 and 610, but not the bottoms (horizontal regions) of these holes. While the vertical walls are electrically insulated, only the target contact to the electrode (anode or cathode) is exposed for further pad (padding). ALD processes are known for their conformal coverage capabilities. Thus, when the diameter of the mask is small (with the exception of the bottom relative to the original mask), the h-BN layer will cover and isolate the inner vertical surfaces of the holes.

In fig. 6(r), an h-BN layer 302 is grown on the graphene electrode 324 to seal the apparatus and to serve as an insulator to insulate the vertical surface of the remaining hole in fig. 6(p), forming an insulating sleeve for the conductive through hole. The h-BN layer is substantially the same as layer 303 of FIG. 6 (b).

In fig. 6(s), all masks are removed, the chamber is opened, and the overgrown (overgrown) wafer is released.

In step 6(t), physical shadow mask 614 is placed around the remaining holes in FIG. 6(s), which exposes the holes and adjacent areas for metallization pads.

In fig. 6(u), a metal alloy such as a Cu/Ag layer 616 is grown which penetrates into the via and contacts the exposed Gn electrode at the bottom. The area surrounding the hole on the surface of the solar device is also grown through mask 614 to form a contact pad for the next device-to-device connection. After growth, mask 614 is removed.

In fig. 6(v), a permanent base substrate 618 for the released and flipped solar device is prepared. The substrate may be prepared in advance with metal circuit traces 620 so that the pads 616 of the device will fit the metal lines and be integrated with the sister device. The substrate 618 should be dielectric, but not limited to a polymer film or a glass article. It may be transparent, opaque or reflective. The reflective substrate may act as a mirror to reflect photons that were not absorbed on the first pass through the PV cell, providing another opportunity for them to be absorbed. The mirror material may be aluminum, copper, silver, gold, titanium nitride, zirconium nitride or alloys of these mirrors.

As shown in fig. 6(w), the overgrown wafer 602 with its h-BN surface and exposed 616 pads is coupled to a substrate 618. The pads 616 fit into the metal circuit 620 of the substrate 618 and are soldered. After soldering, the solid template wafer 602 is peeled from the solar device and placed back into the ALD chamber for reuse. Note that if the wafer 602 is full on both sides, a delaminated wafer having a second full side is introduced to the second permanent wafer 618 and another solar device is formed.

In fig. 6(x), a top laminate 622 is fabricated by placing glass or polymer film on a plurality of solar devices. The polymer may be a spray-coated silicone, polycarbonate sheet or other transparent and durable polymer. The micro-pyramidal surface and anti-reflection coating are incorporated into the top laminate 622. Note that in the present invention, there are no metal lines on top of the solar device that may block the penetration and absorption of solar radiation.

It should be understood that the above description is intended only as an example, and that many other embodiments are possible within the scope of the invention as defined in the appended claims.

The claims (modification according to treaty clause 19)

1. A voltage matched solar module for converting incident solar radiation into electrical energy, characterized by: sequentially comprises the following steps:

a plurality of wafer-sized multijunction solar devices, each solar device comprising:

a first Photovoltaic (PV) cell that first receives the incident solar radiation;

an electrically insulating transparent layer;

a second PV cell that receives the incident solar radiation after the first PV cell; and

a packaging layer; and

a wiring circuit, a bottom substrate adjacent to the module size,

wherein:

the first PV cell and the second PV cell each comprise two transparent electrodes and a p-n junction;

the first and second PV cells are aligned to completely overlap and are electrically connected to the wiring circuit by conductive vias; and

the wiring circuit includes a plurality of serial strings electrically connected in parallel and having approximately the same voltage.

2. The solar module of claim 1, wherein: the wiring circuit includes at least two serial strings electrically connected to the first PV cell.

3. The solar module of claim 1, wherein: the voltage is equal to a number of devices in the plurality of solar devices multiplied by an open circuit voltage of the second PV cell.

4. The solar module of claim 1, wherein: each solar device includes a monolithic stack of a plurality of pellicles comprising a two-dimensional (2D) material.

6. The solar module of claim 4, wherein: the 2D material includes at least one of inorganic, organic, and metal-organic materials having an amorphous, polycrystalline, or single crystal structure.

7. The solar module of claim 4, wherein: the 2D material is a crystalline film, either lamellar or non-lamellar.

9. The solar module of claim 1, wherein: the p-n junction comprises a 2D semiconductor material having a direct bandgap transition.

10. The solar module of claim 1, wherein: the p-n junction includes an n-region and a p-region that together form a type II band alignment.

11. The solar module of claim 1, wherein: the p-n junction comprises a semiconductor material selected from the group consisting of: chemical groups V and VI, chemical groups I-II-IV-VI, I-III-VI, I-IV-VI, IV-VI, I-VI, II-VI, III-IV, III-V, IV-III-V, IV-VI, V-VI, FeS₂And perovskite compounds.

13. The solar module of claim 1, wherein: the conductor adjacent the n-type semiconductor comprises n-type material and the conductor adjacent the p-type semiconductor comprises p-type material.

14. The solar module of claim 1, wherein: each conductive via is enclosed within an insulative sleeve and terminated on the encapsulation layer with a pad.

19. The solar module of claim 18, wherein: the metal film includes a metal or a metal alloy, and is processed to form the wiring circuit so that most of the metal film can function as a reflector.