阅读说明：本技术 多模态可重构物理不可克隆函数电路及其方法 (Multi-mode reconfigurable physical unclonable function circuit and method thereof ) 是由 崔益军 黎江 刘伟强 王成华 于 2021-09-13 设计创作，主要内容包括：本发明涉及多模态可重构物理不可克隆函数电路和方法,电路包括PUF基本单元,PUF基本单元包括顶部数据选择器、多个1T1R单元、底部数据选择器以及读取电路,本发明通过可调节的编程电压,能够在多种工作模式下进行切换,通过不同的配置策略,其可以选择任意的基本单元实现1bit的弱PUF。此外,该PUF可以灵活地映射到RRAM交叉阵列中,与基于RRAM的内存计算架构相兼容,以适应物联网对于计算和安全的需求。实验结果均匀性、唯一性、稳定性以及资源利用率,并且通过了美国国家标准与技术研究院的随机性测试。(The invention relates to a multi-mode reconfigurable physical unclonable function circuit and a method, wherein the circuit comprises a PUF basic unit, the PUF basic unit comprises a top data selector, a plurality of 1T1R units, a bottom data selector and a reading circuit, the circuit can be switched under various working modes through adjustable programming voltage, and through different configuration strategies, any basic unit can be selected to realize 1-bit weak PUF. In addition, the PUF can be flexibly mapped into the RRAM cross array and is compatible with a memory computing architecture based on RRAM, so that the computing and security requirements of the Internet of things are met. The experimental results are uniform, unique, stable and resource utilization rate, and pass the randomness test of national institute of standards and technology.)

1. The multimode reconfigurable physical unclonable function circuit is characterized in that: the PUF basic unit comprises a top data selector (1), a plurality of 1T1R units (2), a bottom data selector (3) and a reading circuit (4), wherein each 1T1R unit (2) is connected with the same top data selector (1) and the same bottom data selector (3) in parallel, the reading circuit (4) is connected with the bottom data selector (3), and the top data selector (1) and the bottom data selector (3) can input an excitation signal and two selectable programming voltages V_program1And V_program2The read circuit (4) includes a ground resistor R_G1And R_G2Respectively connected to the bottom data selector (3) for adapting to different programming voltages by selecting different V_program1And V_program2And a ground resistance R_G1And R_G2And the PUF basic unit can be switched between the RRAM weak writing mechanism mode and the RRAM parallel connection competition mechanism mode.

2. The multi-modal reconfigurable physically unclonable function circuit of claim 1, wherein: the 1T1R cell (2) is formed by connecting a transistor and an RRAM in series.

3. The multi-modal reconfigurable physically unclonable function circuit of claim 2, wherein: and the 1T1R unit (2) is provided with an excitation signal input end for configuring a transistor.

4. The multi-modal reconfigurable physically unclonable function circuit of claim 3, wherein: the transistor is NMOS.

5. The multi-modal reconfigurable physically unclonable function circuit of claim 1, wherein: a plurality of PUF units are connected to form a PUF array, a plurality of PUF arrays are connected to form a PUF column, a plurality of PUF columns are connected to form a PUF block, and a plurality of PUF blocks form a complete PUF chip.

6. The multi-modal reconfigurable physically unclonable function circuit of claim 5, wherein: the PUF chip is connected with a peripheral circuit, and the peripheral circuit comprises a time sequence control circuit, a column decoder, a programming driver, an addressing selection circuit and a reading selection circuit.

7. A method of using a multi-modal reconfigurable physically unclonable function circuit as claimed in claim 3, wherein:

through a top data selector (1),Bottom data selector (3) and read circuit (4) select V_program1And R_G1The PUF elementary cell is configured in a mode based on RRAM weak write mechanism, since the transition between the high resistance state and the low resistance state of the RRAM is usually abrupt, when the applied supply voltage reaches a positive threshold, the conductance value of the RRAM will increase significantly, and because the positive thresholds of the RRAMs are different due to random errors introduced by the active layer channels in the manufacturing process, 50% of the RRAMs will switch to the low resistance state when the appropriate positive voltage is applied, so that the weak write mechanism of the RRAM can be used as an entropy source of the PUF, and any number of 1T1R cells can be opened by an excitation signal, and then V is applied_program1Then, the weak write operation of a plurality of RRAMs can be completed simultaneously;

v is selected by a top data selector (1), a bottom data selector (3) and a read circuit (4)_program2And R_G2The PUF basic unit is configured to be an RRAM parallel competition mechanism mode, a 1bit response value is generated by two parallel 1T1R units due to inconsistency of resistance state transition between RRAM periods, and when two parallel RRAM are in a high resistance state, V is passed_program2One or only one of the two RRAM switches to the low resistance state upon application of a voltage exceeding the forward threshold, and in repeated operation, the one or only one RRAM still completes the resistance state transition, thereby acting as an entropy source for the PUF and producing a stable response value of 1 bit.

Technical Field

The invention belongs to the technical field of hardware safety, and particularly relates to a multi-mode reconfigurable physical unclonable function circuit and a method thereof.

Background

In Internet of things (IoT) and edge computing, terminal devices have strong demands for privacy and security protection. Before the relevant data is processed, the identity authentication of the system needs to be completed to ensure the security of the system. In the field of autonomous driving automobiles, for example, any malicious attack on the device may lead to fatal errors and even threaten the life safety of the user. In 2020, researchers have demonstrated a security breach of tesla autonomous cars. The traditional security authentication scheme based on the software cryptographic algorithm can resist most attacks, but needs a large amount of hardware resources to realize the attack, and is not suitable for low-cost and battery-powered Internet of things equipment. Meanwhile, physical Attack modes such as Side Channel Attack (SCA) Attack, clone Attack and the like have shown strong damage capability to hardware systems.

Nodes of the internet of things, edge computing terminals and the like need a high-reliability security authentication method to prevent clone attack and counterfeiting. A physically unclonable function is considered a promising hardware security primitive that takes advantage of manufacturing process errors of electronic devices to produce unique, uncopyable electronic fingerprints. Two identical electronic products will produce two different outputs (responses) for the same input due to manufacturing process errors. The low power consumption, unclonable, and non-fixed storage characteristics of the PUF provide a reliable chip digital fingerprint for the device, which may provide secure and reliable security authentication for the device. An excitation signal is input to the PUF, which generates a unique and unpredictable Response value according to the chip internal difference, and the PUF can complete the security authentication of the device through such excitation and Response Pairs (CRPs). A simple PUF-based authentication protocol includes three phases of configuration, enrollment, and deployment. All configurable cells need to prepare and configure the initial state of the PUF cell before enrollment. For example, RRAM requires initialization of internal structures and initial programming to either a high resistance state or a low resistance state. In an enrollment phase, the PUF produces a number of pairs of stimulus responses and stores them in a secure database; meanwhile, the indexes of the PUF are evaluated, and the performance of the PUF is verified. In order to complete the authentication of the device, the authentication system sends an excitation signal to the device to be authenticated, the PUF device generates a corresponding response value according to the received excitation and feeds the response back to the authentication system, and the system compares the excitation response of the device with the excitation response stored in the database: if the excitation response pairs are the same, the equipment passes the authentication; if not, authentication fails.

Existing PUF designs (such as an arbitration PUF and a ring oscillator PUF) based on Complementary Metal-Oxide-Semiconductor (CMOS) technology have good uniqueness and stability, but have low area efficiency and high power consumption. Due to the extremely high circuit density and the configurable potential, the PUF circuit structure based on the novel nonvolatile memory is widely concerned. The PUF design based on the RRAM has the advantages of low power consumption, small area, high density and the like, can be compatible with a non-von Neumann memory computing architecture, and can well support the security certification of resource limited nodes such as the next generation of Internet of things and edge computing.

However, the practical RRAM device has non-ideal characteristics, which results in poor stability of PUF design. The existing design is complex to realize, and the reconfigurability and the resource utilization rate need to be further improved. In addition, the existing PUF circuit structure based on RRAM has more concern about security, but has less consideration on resource consumption and cost, so that a PUF circuit with higher design density and stronger reconfigurability is required, and the stability of the RRAM PUF needs to be improved to meet the requirements of practical application. In addition, due to the great requirement of the edge computing node on security and the rapid development of the memory computing in the edge computing, how to coordinate the PUF with the Crossbar architecture of the memory computing is also significant.

Disclosure of Invention

In order to solve the problems, the patent newly provides a multi-mode reconfigurable physical unclonable function circuit and a method thereof.

In order to achieve the technical purpose, the technical scheme adopted by the invention is as follows:

the multimode reconfigurable physical unclonable function circuit comprises a PUF basic unit, wherein the PUF basic unit comprises a top data selector, a plurality of 1T1R units, a bottom data selector and a reading circuit, and each 1T1R unit is connected with the same top data selector and the same bottom data selector in parallel and readsThe circuit is connected with a bottom data selector, and the top data selector and the bottom data selector can input excitation signals and two selectable programming voltages V_program1And V_program2The read circuit includes a ground resistor R_G1And R_G2Respectively connected to the bottom data selector for adapting to different programming voltages by selecting different V_program1And V_program2And a ground resistance R_G1And R_G2And the PUF basic unit can be switched between the RRAM weak writing mechanism mode and the RRAM parallel connection competition mechanism mode.

In order to optimize the structural form, the specific measures adopted further comprise:

the 1T1R cell is formed by a transistor and a RRAM connected in series.

The unit 1T1R is provided with an excitation signal input terminal for configuring a transistor.

The transistor is an NMOS.

The PUF units are connected to form a PUF array, the PUF arrays are connected to form a PUF column, the PUF columns are connected to form a PUF block, and the PUF blocks form a complete PUF chip.

The PUF chip is connected to peripheral circuits including a timing control circuit, a column decoder and a programming driver, an address select, and a read select.

The use method of the multi-mode reconfigurable physical unclonable function circuit comprises the following steps:

selecting V by a top data selector, a bottom data selector and a read circuit_program1And R_G1The PUF basic unit is configured to be based on an RRAM weak writing mechanism mode, because the transition between the high resistance state and the low resistance state of the RRAM is usually abrupt, when the applied power supply voltage reaches a positive threshold value, the conductance value of the RRAM is remarkably increased, and the positive threshold values of the RRAMs are different due to random errors introduced by the active layer channels in the manufacturing process, so that 50% of the RRAMs are switched to the low resistance state when the proper positive voltage is applied, and therefore the weak writing mechanism of the RRAM can be used as an entropy source of the PUF, and any number of 1T1R units are opened through an excitation signalThen applying V_program1Then weak write operations of multiple RRAMs can be completed simultaneously.

Selecting V by a top data selector, a bottom data selector and a read circuit_program2And R_G2The PUF basic unit is configured to be an RRAM parallel competition mechanism mode, a 1bit response value is generated by two parallel 1T1R units due to inconsistency of resistance state transition between RRAM periods, and when two parallel RRAM are in a high resistance state, V is passed_program2One or only one of the two RRAM switches to the low resistance state upon application of a voltage exceeding the forward threshold, and in repeated operation, the one or only one RRAM still completes the resistance state transition, thereby acting as an entropy source for the PUF and producing a stable response value of 1 bit.

The invention provides a multimode reconfigurable PUF circuit based on RRAM and a method thereof, which have the following advantages:

1. by adjusting the programming voltage, the PUF circuit can be configured to different working modes, switch between RRAM weak writing mechanism mode and RRAM parallel competition mechanism mode, and utilize the randomness of RRAM inherent resistance state switching to drive the RRAM to be converted into an unpredictable High Resistance State (HRS) or Low Resistance State (LRS) to generate a unique response value. Through different configuration strategies, any basic unit can be selected to realize 1bit weak PUF.

2. The circuit of the invention can be flexibly mapped into an RRAM cross array (Crossbar), is compatible with an RRAM-based memory computing architecture, enables corresponding rows and columns in the Crossbar, namely selects the corresponding RRAM, and applies V_program1Or V_program2Two working modes of the multi-mode physical unclonable function can be realized, and the requirements of the Internet of things on calculation and safety are met.

Drawings

FIG. 1 is a schematic diagram of a multi-modal reconfigurable physically unclonable function circuit design;

FIG. 2 is a schematic diagram of a RRAM weak write mechanism;

FIG. 3 is a schematic diagram of a PUF implementation based on the RRAM weak write mechanism that enables two 1T1R cells;

FIG. 4 is a schematic diagram of a PUF implementation based on the RRAM weak write mechanism that enables n-1T 1R cells;

FIG. 5 is a diagram of PUF elementary cells based on the RRAM parallel contention mechanism;

fig. 6 is a PUF read-write voltage diagram based on the RRAM parallel contention mechanism.

FIG. 7 is a schematic diagram of an implementation of a multi-modal PUF in a RRAM Crossbar architecture based on a separate RRAM weak write mechanism;

fig. 8 is a schematic diagram of an implementation of a multi-modal PUF in a RRAM Crossbar architecture based on two RRAM contention mechanisms.

FIG. 9 is a spectral distribution plot of 100 128-bit responses collected in parallel contention mode;

FIG. 10 is a graph of the uniformity profile of the response in the parallel contention mode.

FIG. 11 is a graph of uniqueness and stability distribution in the parallel contention mode.

The reference numbers in the figures are: top data selector 1, 1T1R cell 2, bottom data selector 3, read circuit 4.

Detailed Description

Embodiments of the present invention are described in further detail below with reference to the accompanying drawings.

The multimode reconfigurable physical unclonable function circuit based on the novel Resistive Random Access Memory (RRAM) of the embodiment is shown in fig. 1. The overall architecture of a configurable multi-modal reconfigurable physically Unclonable Function circuit design (PUF) with a 1k × 1k RRAM array is given, with a timing controller, read-write modules and row-column decoders. The 1T1R structure may make the proposed design compatible with mainstream storage applications based on RRAM arrays, and the 1T1R (1 transducer 1 RRAM) structure may minimize design overhead. The PUF elementary cell, shown in the lower right corner of fig. 1, consists of a parallel array of 1k 1T1R, with top and bottom data selectors, adjustable programming voltage, and optional series ground resistance. The 1T1R cell serves as a basic cell of the PUF, and can prevent the influence of leakage current and the like on the response of the PUF. Prior to the generation of the pair of excitation responses,the PUF requires a write operation to set the initial state of the RRAM. Since the resistance distribution of the high resistance state is wider with larger process variation, the RRAM is initially reset to HRS. Selecting the corresponding 1T1R cell using the input stimulus as an address, enabling the NMOS to turn on the corresponding RRAM, applying different programming voltages (V)_program1And V_program2) The PUF can be configured into two different modes of operation, including a weak write mode and a parallel contention mode. The bit width of the addressing circuitry for the basic cells of the PUF is 10 bits (in a 1Mb RRAM array, 1k, i.e. 2, is included¹⁰Individual PUF elementary cells) the minimum excitation bit length for addressing is 20 bits. 20 bit addressing and 2 bit working mode and read-write configuration, and 22 bit excitation is input. A PUF elementary cell generates a 1bit response in one read, so that a 1Mb RRAM PUF can generate a 1kb response value at the same time. Furthermore, after one write phase, multiple reads can be performed by inputting different read addresses.

The RRAM PUF can be configured into two different working modes by selecting different power supply voltages and series resistances through a data selector. When selecting V_program1And R_G1When it is configured as a weak write mode, the operation principle is as shown in fig. 2. The RRAM has two states of a high resistance state and a low resistance state, and is converted into the low resistance state when a forward voltage exceeding a forward threshold is applied, which is called Set operation; when a reverse voltage exceeding a reverse threshold is applied, the RRAM is transited to a high resistance state, which is called Reset operation. When the RRAM is initialized to the high resistance state, 50% of all RRAMs transition to the low resistance state and the remaining 50% remain in the high resistance state when a Set pulse is applied that is just the positive threshold. Whether a particular RRAM will complete a resistance state transition is stable and unpredictable for a particular RRAM and, therefore, may act as an entropy source for the PUF. PUF configuration based on RRAM weak write mechanism is shown in FIG. 3 and FIG. 4, in order to configure multiple RRAMs simultaneously, 1, 2 1T1R cells can be opened simultaneously as shown in FIG. 3 or multiple 1T1R cells can be opened as shown in FIG. 4, so as to obtain enough pairs of stimulus responses. After configuration is complete, the response may be read by the node voltage between the RRAM and the resistor by address selection of a particular RRAM. When the RRAM is in a low-resistance state, the node is at a high potential according to the voltage division principle of the resistor; when the RRAM is in the high impedance state, the node is at the low potential. In a 1Mb RRAM PUF, since the RRAM capacity is 1Mb, the maximum number of pairs of excitation responses of the PUF based on the weak write mode is 1 Mb.

When selecting V_program2And R_G2The RRAM PUF is configured in a parallel competition mode, the basic unit of the RRAM PUF is shown in figure 5, two RRAMs are connected in parallel, and a common node CE is connected with a grounding resistor R_G2. The operation of this mode generating response is Reset-Set. In Reset operation, both RRAMs are first configured to a high impedance state and then at V_program2A Set voltage is applied when there is and only one RRAM transitioning to the low resistance state due to differences in RRAM internal resistance state transitions. When one RRAM is changed into a low resistance state, the voltage of the CE node is suddenly changed into a high potential, so that the resistance value of the other RRAM is prevented from switching. FIG. 6 shows V in contention mode_program2And voltage sequence control, wherein a-2V Reset voltage and a 1.5V Set voltage are sequentially applied to two parallel RRAMs. In the reading process, one of the RRAMs needs to be floated, the potential of the CE node is read to generate a 1-bit response value, and the reading mode is the same as the weak writing mode. In order to generate a 1bit response, two 1T1R cells need to be selected simultaneously to realize parallel competition PUF, so that the maximum number of pairs of excitation responses which can be generated in the PUF basic cell containing 1k RRAMs is=523,776. Thus, in a 1Mb multi-modal reconfigurable PUF, this mode can result in a 5.23 × 10 PUF⁸The response value of bit.

On the RRAM Crossbar architecture, dot product operation is easy to realize. To date, RRAM Crossbar (from device level to system level) has made considerable progress in-memory computing applications. To improve the security of edge computing devices, a multi-modal reconfigurable PUF implemented on a RRAM crossbar architecture is shown in fig. 7 and 8. By enabling any row and column in the Crossbar, one RRAM can be selected to implement a weak write PUF, as shown in fig. 7; similarly, a parallel competing PUF is implemented by enabling two rows and one column or one row and two columns, selecting two parallel RRAM. This implementation has no fundamental unit limitations and can utilize either or both RRAMs to generate a 1-bit response during a read and write cycle. This implementation may improve the area efficiency by 2 compared to classical PUF designs based on fixed 2T 2R.

In the case of parallel contention, we have collected 100 response values of 128-bit, whose spectral diagram is shown in fig. 9, white indicates that the bit response is "0" and blue indicates that the response is "1". As can be seen from the figure, the response values of the PUF have no significant correlation under the spatial distribution. Also, as can be seen from the PUF uniformity distribution of fig. 10, the mean value of Hamming Distance (HD) thereofμ=49.99%, varianceσ=1.8604%, the uniformity of the PUF response is 49.99%, very close to the ideal value of 50%. Fig. 11 shows the distribution of the uniqueness and stability of the response in the competition mode, and it can be seen that the uniqueness (inter-chip HD) is 0.50026 (ideal value is 0.5), the stability (intra-chip HD) is 0.00038 (ideal value is 0), and there is a difference of 1316 ×, showing superior stability.

The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may be made by those skilled in the art without departing from the principle of the invention.