阅读说明：本技术 一种电容耦合斩波放大器 (Capacitor coupling chopper amplifier ) 是由 李靖 吴健民 张中 宁宁 于奇 于 2020-06-15 设计创作，主要内容包括：本发明属于集成电路领域,尤其涉及一种电容耦合斩波放大器。本发明通过将纹波抑制环路与跨导自举技术相结合,纹波消除环路将放大器主通路输出中的纹波转化为电流,反馈回运放Gm1的输出端,形成负反馈从而抑制了纹波,并在结合的过程中将纹波抑制环路中的跨导放大器的电流减小了B倍(B跨导自举技术中电流镜的放大倍数)；一方面提高运放第一级跨导,降低噪声,同时减少了纹波抑制环路中跨导放大器的尾电流,从而降低了功耗。(The invention belongs to the field of integrated circuits, and particularly relates to a capacitor coupling chopper amplifier. According to the invention, a ripple suppression loop is combined with a transconductance bootstrap technology, a ripple elimination loop converts ripples in the output of a main channel of an amplifier into current, and the current is fed back to the output end of an operational amplifier Gm1 to form negative feedback, so that the ripples are suppressed, and the current of a transconductance amplifier in the ripple suppression loop is reduced by B times (the amplification times of a current mirror in the B transconductance bootstrap technology) in the combination process; on one hand, the first-stage transconductance of the operational amplifier is improved, noise is reduced, and meanwhile, the tail current of a transconductance amplifier in a ripple suppression loop is reduced, so that power consumption is reduced.)

1. A capacitively coupled chopper amplifier comprising an amplifier main path 101 and a ripple rejection loop 102, wherein:

the amplifier main path 101 consists of an operational amplifier Gm1, a chopper CH1 and an integrator 105; the integrator 105 is composed of an operational amplifier Gm2 and Miller capacitors Cm1 and Cm 2; the chopper CH1 comprises CH1_ a and CH1_ b;

the output of the amplifier main path 101 is connected with the input of the ripple suppression loop 102, and the output of the ripple suppression loop 102 is connected with the output of the operational amplifier Gm1 in the amplifier main path 101 to form negative feedback;

the output end of the amplifier main channel 101 is connected with the lower pole plates of the detection capacitors Cs1 and Cs2, the upper pole plates of the detection capacitors Cs1 and Cs2 are connected with the input end of the chopper CH2, the output end of the chopper CH2 is connected with the input end of the integrator 104, the output end of the integrator 104 is connected with the input end of the transconductance amplifier 103, and the output end of the transconductance amplifier 103 is fed back to the output end of the operational amplifier Gm 1;

the specific architecture of the amplifier main channel 101 includes: a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, an eleventh PMOS transistor PM11, a twelfth PMOS transistor PM12, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, an eighth NMOS transistor NM8, a chopper CH1_ a, a CH1_ b, miller capacitors Cm1, Cm 2;

the first PMOS tube PM1, the second PMOS tube PM2, the third PMOS tube PM3 and the fourth PMOS tube PM4 are input tubes of the operational amplifier Gm 1; the source ends of the second PMOS pipe PM2 and the third PMOS pipe PM3 are connected with the drain end of the fifth PMOS pipe PM 5; a fifth PMOS pipe PM5 is a current source, and the source end of the fifth PMOS pipe PM5 is connected with power supply voltage; the source ends of the first PMOS pipe PM1 and the fourth PMOS pipe PM4 are connected and connected with the drain end of the sixth PMOS pipe PM 6; the sixth PMOS transistor PM6 is a current source, and its source is connected to the power voltage. The drain terminal of the first PMOS tube PM1 is connected with the drain terminal of the first NMOS tube NM1 and the input terminal of the chopper CH1_ a; the first NMOS transistor NM1 and the second NMOS transistor NM2 are current mirror loads, the grid ends of the first NMOS transistor NM1 and the second NMOS transistor NM2 are connected with each other and are connected with the drain end of the second NMOS transistor NM2, and the source ends of the first NMOS transistor NM1 and the second NMOS transistor NM2 are connected with each other and; the drain terminal of the fourth PMOS tube PM4 is connected with the drain terminal of the fourth NMOS tube NM4 and the other input terminal of the chopper CH1_ a; the third PMOS tube PM3 and the fourth PMOS tube PM4 are current mirror loads, the grid ends of the third PMOS tube PM3 and the fourth PMOS tube PM4 are connected with each other and are connected with the drain end of the third NMOS tube NM3 in parallel, and the source ends of the third PMOS tube PM3 and the fourth PMOS tube PM4 are connected with each other and are grounded; the output end of the chopper CH1_ a is connected with the source end of a fifth NMOS tube NM5 and the source end of a sixth NMOS tube NM 6; the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are cascode transistors, the gate ends of the cascode transistors are connected and connected with a bias voltage Vb3 in parallel, and the drain end of the fifth NMOS transistor NM5 is connected with the drain end of the ninth PMOS transistor PM 9; the drain terminal of the sixth NMOS transistor NM6 is connected to the drain terminal of the tenth PMOS transistor PM 10; the ninth PMOS tube PM9 and the tenth PMOS tube PM10 are cascode tubes, the gate ends of the cascode tubes are connected and connected with a bias voltage Vb2 in parallel, and the source end of the ninth PMOS tube PM9 is connected with the output end of the chopper CH1_ b; the source end of the tenth PMOS tube PM10 is connected with the other output end of the chopper CH1_ b, and the input end of the chopper CH1_ b is respectively connected with the drain end of the seventh PMOS tube PM7 and the drain end of the eighth PMOS tube PM 8; the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 are current sources, the grid ends of the current sources are connected with the bias voltage CMFB1 in parallel, and the source ends of the current sources are connected with the power voltage in parallel; the drain terminal of the ninth PMOS tube PM9 is an operational amplifier first-stage output terminal, and is connected with the gate terminal of the eleventh PMOS tube PM11 and the upper polar plate of the Miller capacitor Cm1, and the lower polar plate of the Miller capacitor Cm1 is connected with the drain terminal of the eleventh PMOS tube PM 11; the source end of an eleventh PMOS tube PM11 is connected with the power supply voltage, and the drain end of the eleventh PMOS tube PM11 is connected with the drain end of a seventh NMOS tube NM 7; the drain terminal of the tenth PMOS tube PM10 is the other output terminal of the first stage of the operational amplifier, and is connected with the gate terminal of the twelfth PMOS tube PM12 and the upper polar plate of the Miller capacitor Cm2, and the lower polar plate of the Miller capacitor Cm2 is connected with the drain terminal of the twelfth PMOS tube PM 12; the source end of the twelfth PMOS tube PM12 is connected with the power supply voltage, and the drain end of the twelfth PMOS tube PM12 is connected with the drain end of the eighth NMOS tube NM 8; the seventh NMOS transistor NM7 and the eighth NMOS transistor NM8 are current sources, the gate terminals of which are connected to each other and connected to the bias voltage CMFB2, and the source terminals of which are connected to each other and grounded;

the ripple suppression loop 102 comprises detection capacitors Cs1, Cs2, a chopper CH2, an integrator 104 and a transconductance amplifier 103; the integrator 104 consists of an operational amplifier Gm3, and integrating capacitors Cint1 and Cint 2; the detection capacitors Cs1 and Cs2 are used for detecting ripple voltage in the output of the amplifier main channel 101 and converting the ripple voltage into current, the chopper CH2 demodulates the current, the current is converted into voltage through the integrator 104, the voltage is converted into current through the transconductance amplifier 103, and the current is compensated and output by the operational amplifier Gm1 to form negative feedback.

The transconductance amplifier 103 comprises a thirteenth PMOS transistor PM13, a fourteenth PMOS transistor PM14 and a fifteenth PMOS transistor PM 15. A thirteenth PMOS transistor PM13 is a current source, a gate terminal of which is connected to a bias voltage Vb1, a fourteenth PMOS transistor PM14 and a fifteenth PMOS transistor PM15 are input pair transistors of the transconductance amplifier Gm4, an input of which is connected to an output of the integrator 104, a drain terminal of the fourteenth PMOS transistor PM14 is connected to a drain terminal of the second PMOS transistor PM2, and a drain terminal of the fifteenth PMOS transistor PM15 is connected to a drain terminal of the third PMOS transistor PM 3.

2. The capacitively coupled chopper amplifier of claim 1, wherein:

the working process is as follows:

when the input signal contains offset voltage, the voltage is converted into current through the operational amplifier Gm1 and is modulated to high frequency through the chopper CH 1; ripple voltage is formed at the output end of the amplifier main channel 101 through the integrator 105, the ripple voltage is converted into current through the detection capacitors Cs1 and Cs2 in the ripple suppression loop 102, demodulated back to low frequency through the chopper CH2, converted into voltage through the integrator 104, converted into current through the transconductance amplifier 103, and finally fed back to the output end of the operational amplifier Gm1 to form negative feedback.

3. The capacitively coupled chopper amplifier of claim 2, wherein:

the feedback mode is specifically as follows:

the output of the transconductance amplifier 103 is connected with the drain terminals of a second PMOS tube PM2 and a third PMOS tube PM3 in the first-stage operational amplifier Gm 1; the current of the two branches of the second PMOS transistor PM2 and the third PMOS transistor PM3 is amplified by B times by a current mirror composed of the first NMOS transistor NM1 and the second NMOS transistor NM2 and a current mirror composed of the third NMOS transistor NM3 and the fourth NMOS transistor NM 4.

Technical Field

The invention belongs to the field of integrated circuits, and particularly relates to a capacitor coupling chopper amplifier.

Background

With the rapid development of the internet of things in recent years, more and more practical applications require low-frequency signal measuring devices, such as electroencephalograms (EEG), Electrocardiograms (ECG) and Electromyograms (EMG), which are all required to be converted into electric signals by sensors for detection. These biological signals are weak, and are as small as tens of microvolts to tens of millivolts, and the frequency range provided is only from direct current to hundreds of Hz, and at such low frequencies, they are usually affected by non-ideal factors such as flicker noise and offset voltage, which have proven to be rather unfavorable for signal acquisition, so it is necessary to adopt corresponding techniques to eliminate these non-ideal factors while processing the weak biological signals. Compared with the traditional operational amplifier, the high-precision instrument amplifier has the advantages of high input impedance, low noise, low offset voltage, high common mode rejection ratio and the like, and the high-precision instrument amplifier with low noise and low ripple performance is particularly important for processing weak signals.

The dynamic offset cancellation technology adopted for reducing system offset and noise generally comprises a self-zeroing technology and a chopping technology, but the self-zeroing technology can introduce oversampling broadband noise, and meanwhile, residual offset can be brought by injection of switch charge, so that the self-zeroing technology is not suitable for the low-noise field, and the chopping technology is generally adopted for canceling offset and noise. Because the traditional chopper stabilization structure has compromise between residual offset and residual ripple amplitude, in order to solve the problem, a ripple rejection loop (ripple reduction loop) is introduced to realize lower performance of the residual offset and reduce the output ripple amplitude.

The common ripple rejection loop structure principle is that output ripples are sampled by a capacitor, integrated by an integrator and finally converted into feedback current compensation offset through a transconductance amplifier, so that the ripples are rejected. In order to adequately compensate for the offset, the tail current of the transconductance amplifier must be large enough, and therefore this configuration increases power consumption, which is undesirable in some portable devices.

Disclosure of Invention

In view of the above problems or disadvantages, an object of the present invention is to provide a capacitor-coupled chopper amplifier, which reduces noise and power consumption by combining a ripple cancellation loop with a transconductance bootstrapping technique, in order to solve the problem that the power consumption of the existing ripple suppression loop is relatively high.

In order to achieve the purpose, the technical scheme of the invention is as follows:

a capacitively coupled chopper amplifier includes an amplifier main path 101 and a ripple rejection loop 102.

The amplifier main path 101 consists of an operational amplifier Gm1, a chopper CH1 (comprising CH1_ a and CH1_ b) and an integrator 105; the integrator 105 is composed of an operational amplifier Gm2 and miller capacitors Cm1, Cm 2. The output of the amplifier main path 101 is connected to the input of the ripple suppression loop 102, and the output of the ripple suppression loop 102 is connected to the output of the operational amplifier Gm1 in the amplifier main path 101, forming negative feedback.

The output end of the amplifier main channel 101 is connected with the lower pole plates of the detection capacitors Cs1 and Cs2, the upper pole plates of the detection capacitors Cs1 and Cs2 are connected with the input end of the chopper CH2, the output end of the chopper CH2 is connected with the input end of the integrator 104, the output end of the integrator 104 is connected with the input end of the transconductance amplifier 103, and the output end of the transconductance amplifier 103 is fed back to the output end of the operational amplifier Gm 1.

The architecture of the amplifier main path 101 comprises: a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, an eleventh PMOS transistor PM11, a twelfth PMOS transistor PM12, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, an eighth NMOS transistor NM8, a chopper CH1_ a, a CH1_ b, miller capacitors Cm1, and Cm 2.

The first PMOS tube PM1, the second PMOS tube PM2, the third PMOS tube PM3 and the fourth PMOS tube PM4 are input tubes of the operational amplifier Gm 1; the source ends of the second PMOS pipe PM2 and the third PMOS pipe PM3 are connected with the drain end of the fifth PMOS pipe PM 5; a fifth PMOS pipe PM5 is a current source, and the source end of the fifth PMOS pipe PM5 is connected with power supply voltage; the source ends of the first PMOS pipe PM1 and the fourth PMOS pipe PM4 are connected and connected with the drain end of the sixth PMOS pipe PM 6; the sixth PMOS transistor PM6 is a current source, and its source is connected to the power voltage. The drain terminal of the first PMOS tube PM1 is connected with the drain terminal of the first NMOS tube NM1 and the input terminal of the chopper CH1_ a; the first NMOS transistor NM1 and the second NMOS transistor NM2 are current mirror loads, the grid ends of the first NMOS transistor NM1 and the second NMOS transistor NM2 are connected with each other and are connected with the drain end of the second NMOS transistor NM2, and the source ends of the first NMOS transistor NM1 and the second NMOS transistor NM2 are connected with each other and; the drain terminal of the fourth PMOS tube PM4 is connected with the drain terminal of the fourth NMOS tube NM4 and the other input terminal of the chopper CH1_ a; the third PMOS tube PM3 and the fourth PMOS tube PM4 are current mirror loads, the grid ends of the third PMOS tube PM3 and the fourth PMOS tube PM4 are connected with each other and are connected with the drain end of the third NMOS tube NM3 in parallel, and the source ends of the third PMOS tube PM3 and the fourth PMOS tube PM4 are connected with each other and are grounded; the output end of the chopper CH1_ a is connected with the source end of a fifth NMOS tube NM5 and the source end of a sixth NMOS tube NM 6; the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are cascode transistors, the gate ends of the cascode transistors are connected and connected with a bias voltage Vb3 in parallel, and the drain end of the fifth NMOS transistor NM5 is connected with the drain end of the ninth PMOS transistor PM 9; the drain terminal of the sixth NMOS transistor NM6 is connected to the drain terminal of the tenth PMOS transistor PM 10; the ninth PMOS tube PM9 and the tenth PMOS tube PM10 are cascode tubes, the gate ends of the cascode tubes are connected and connected with a bias voltage Vb2 in parallel, and the source end of the ninth PMOS tube PM9 is connected with the output end of the chopper CH1_ b; the source end of the tenth PMOS tube PM10 is connected with the other output end of the chopper CH1_ b, and the input end of the chopper CH1_ b is respectively connected with the drain end of the seventh PMOS tube PM7 and the drain end of the eighth PMOS tube PM 8; the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 are current sources, the grid ends of the current sources are connected with the bias voltage CMFB1 in parallel, and the source ends of the current sources are connected with the power voltage in parallel; the drain terminal of the ninth PMOS tube PM9 is an operational amplifier first-stage output terminal, and is connected with the gate terminal of the eleventh PMOS tube PM11 and the upper polar plate of the Miller capacitor Cm1, and the lower polar plate of the Miller capacitor Cm1 is connected with the drain terminal of the eleventh PMOS tube PM 11; the source end of an eleventh PMOS tube PM11 is connected with the power supply voltage, and the drain end of the eleventh PMOS tube PM11 is connected with the drain end of a seventh NMOS tube NM 7; the drain terminal of the tenth PMOS tube PM10 is the other output terminal of the first stage of the operational amplifier, and is connected with the gate terminal of the twelfth PMOS tube PM12 and the upper polar plate of the Miller capacitor Cm2, and the lower polar plate of the Miller capacitor Cm2 is connected with the drain terminal of the twelfth PMOS tube PM 12; the source end of the twelfth PMOS tube PM12 is connected with the power supply voltage, and the drain end of the twelfth PMOS tube PM12 is connected with the drain end of the eighth NMOS tube NM 8; the seventh NMOS transistor NM7 and the eighth NMOS transistor NM8 are current sources, the gate terminals of which are connected to each other and connected to the bias voltage CMFB2, and the source terminals of which are connected to each other and connected to ground.

The ripple suppression loop 102 comprises detection capacitors Cs1, Cs2, a chopper CH2, an integrator 104 and a transconductance amplifier 103; the integrator 104 is composed of an operational amplifier Gm3 and integrating capacitors Cint1 and Cint 2. The detection capacitors Cs1 and Cs2 are used for detecting ripple voltage in the output of the amplifier main channel 101 and converting the ripple voltage into current, the chopper CH2 demodulates the current, the voltage is converted into the voltage through the integrator 104, the current is converted into the current through the transconductance amplifier 103, and the current is compensated and returned to the output of the operational amplifier Gm1 to form negative feedback, so that ripple is suppressed.

The transconductance amplifier 103 comprises a thirteenth PMOS transistor PM13, a fourteenth PMOS transistor PM14 and a fifteenth PMOS transistor PM 15. A thirteenth PMOS transistor PM13 is a current source, a gate terminal of which is connected to a bias voltage Vb1, a fourteenth PMOS transistor PM14 and a fifteenth PMOS transistor PM15 are input pair transistors of the transconductance amplifier Gm4, an input of which is connected to an output of the integrator 104, a drain terminal of the fourteenth PMOS transistor PM14 is connected to a drain terminal of the second PMOS transistor PM2, and a drain terminal of the fifteenth PMOS transistor PM15 is connected to a drain terminal of the third PMOS transistor PM 3.

Compared with the prior art, the invention has the following beneficial effects: according to the invention, by combining the ripple suppression loop with the transconductance bootstrapping technology, the transconductance is improved, and meanwhile, the feedback current is amplified by B times through the current mirror in the transconductance bootstrapping technology (B is the amplification factor of the current mirror in the transconductance bootstrapping technology), so that the tail current of the transconductance amplifier 103 can be reduced by B times, the overall power consumption is reduced, and the low-power-consumption portable device is more favorably applied.

Drawings

Fig. 1 is a schematic diagram of the overall structure of the capacitively coupled chopper amplifier of the present invention.

Fig. 2 is a schematic diagram of a combination of the transconductance amplifier 103 and the transconductance bootstrapping technique according to the present invention.

Detailed Description

The technical solution of the present invention is specifically described below with reference to the accompanying drawings and examples.

Fig. 1 is a schematic diagram of the overall structure of the capacitively coupled chopper amplifier of the present invention, which includes an amplifier main path 101 and a ripple suppression loop 102.

The output of the amplifier main path 101 is connected with the input of the ripple suppression loop 102, and the output of the ripple suppression loop 102 is connected with the output of the operational amplifier Gm1 in the amplifier main path 101 to form negative feedback, thereby suppressing the ripple in the output signal.

The working process of the capacitive coupling chopper amplifier in the embodiment is as follows:

when an input signal contains offset voltage, the voltage is converted into current through the operational amplifier Gm1, the current is modulated to high frequency through the chopper CH1, ripple voltage is formed at the output end of the amplifier main channel 101 through the integrator 105, the ripple voltage is converted into current through the detection capacitors Cs1 and Cs2 in the ripple suppression loop 102, the current is demodulated back to low frequency through the chopper CH2, the current is converted into voltage through the integrator 104, the voltage is converted into current through the transconductance amplifier 103, and the current is finally fed back to the output end of the operational amplifier Gm1 to form negative feedback, so that the amplitude of ripple is suppressed.

As shown in fig. 2, the specific feedback manner is that the output of the transconductance amplifier 103 is connected to the drain terminals of the second PMOS transistor PM2 and the third PMOS transistor PM3 in the first-stage operational amplifier Gm1, because the currents of the two branches of the second PMOS transistor PM2 and the third PMOS transistor PM3 are amplified by B times by the current mirror formed by the first NMOS transistor NM1 and the second NMOS transistor NM2 and the current mirror formed by the third NMOS transistor NM3 and the fourth NMOS transistor NM4, the current of the current source of the transconductance amplifier 103 can be reduced by B times, thereby saving power consumption.

In summary, it can be seen that the capacitor-coupled chopper amplifier provided by the present invention combines a ripple suppression loop with a transconductance bootstrapping technique, where the ripple cancellation loop converts ripples in the output of the main path of the amplifier into current, and feeds the current back to the output end of the operational amplifier Gm1 to form negative feedback, so as to suppress the ripples, and reduce the current of the transconductance amplifier in the ripple suppression loop by B times (the amplification factor of a current mirror in the transconductance bootstrapping technique B) in the combining process; on one hand, the first-stage transconductance of the operational amplifier is improved, noise is reduced, and meanwhile, the tail current of a transconductance amplifier in a ripple suppression loop is reduced, so that power consumption is reduced.

Although the present invention has been described in terms of a capacitively coupled chopper amplifier circuit, it is not intended to limit the present invention, and those skilled in the art may make insubstantial changes or modifications without departing from the spirit of the invention.