阅读说明：本技术 快速启用的电源 (Fast-start power supply ) 是由 翁德雷·波克 约翰·皮戈特 于 2020-03-05 设计创作，主要内容包括：用于快速启用电源的方法包括通过第一分支传导第一电流,该第一分支包括响应于通过启用信号启用第一开关而与该第一开关串联连接的第一晶体管。通过该第一晶体管的第一栅极与第一源极之间的第一电容从偏置轨道去除第一电荷。通过第二分支传导第二电流,该第二分支包括响应于通过该启用信号启用第二开关而与第二晶体管串联连接的该第二开关。通过该第二晶体管的第二漏极与第二栅极之间的第二电容将第二电荷添加到该偏置轨道,其中该第一栅极和该第二栅极连接到该偏置轨道并且通过镜像参考电压偏置。(A method for quickly enabling a power supply includes conducting a first current through a first branch including a first transistor connected in series with a first switch in response to the first switch being enabled by an enable signal. The first charge is removed from the bias rail by a first capacitance between a first gate and a first source of the first transistor. A second current is conducted through a second branch that includes a second switch connected in series with a second transistor in response to enabling the second switch by the enable signal. Adding a second charge to the bias rail through a second capacitance between a second drain and a second gate of the second transistor, wherein the first gate and the second gate are connected to the bias rail and biased by a mirror reference voltage.)

1. A fast-enabled power supply, comprising:

a bias chain configured to generate a mirror reference voltage on a bias rail;

a first branch comprising a first transistor having a first drain connected to a first node, a first source connected to a first switch, and a first gate connected to the bias rail, the first switch configured to short the first source to a second node in response to an enable signal;

a first capacitor between the first gate and the first source;

a second branch comprising a second transistor having a second drain connected to a second switch, a second source connected to the second node, and a second gate connected to the bias rail, the second switch configured to short the second drain to the first node in response to the enable signal; and

a second capacitance between the second drain and the second gate, wherein first charge removed from the bias rail by the first capacitance is cancelled by second charge added to the bias rail by the second capacitance in response to the enable signal.

2. The fast-enabled power supply of claim 1, wherein the first charge is equal to the second charge, and wherein a first width of the first transistor divided by a second width of the second transistor defines an optimal transistor ratio.

3. The fast-enabled power supply of claim 2 wherein the optimal transistor ratio is one-half, wherein each of the transistors of the fast-enabled power supply comprises an n-channel field effect transistor.

4. The fast-enabled power supply of claim 1, wherein the first switch comprises an n-channel field effect transistor comprising: a first switch drain connected to the first source; a first switch gate connected to the enable signal, the enable signal configured to enable the first switch; and a first switched source connected to the second node.

5. The fast-enabled power supply of claim 1, wherein the second switch comprises a high voltage n-channel field effect transistor, the n-channel field effect transistor comprising: a second switch drain connected to the first node; a second switch gate connected to the enable signal, the enable signal configured to enable the second switch; and a second switch source connected to the second drain.

6. The fast-enabled power supply of claim 1, wherein the bias chain comprises a bias transistor comprising a bias drain connected to a power supply, a bias gate connected to the bias drain and the bias rail, and a bias source connected to the second node.

7. The fast-enabled power supply of claim 6 further comprising a bias compensation device connected between the bias source and the second node, wherein the bias compensation device has the same voltage drop as the first switch when the first switch is enabled.

8. The fast-enabled power supply of claim 1 further comprising a protection device connected between the first node and the first drain, wherein the protection device has the same voltage drop as the second switch when the second switch is enabled.

9. A method for quickly enabling a power supply, comprising:

generating a mirror reference voltage on the bias rail;

conducting a first current through a first branch between a first node and a second node, the first branch comprising a first transistor connected in series with a first switch in response to the first switch being enabled by an enable signal;

removing a first charge from the bias rail through a first capacitance between a first gate and a first source of the first transistor, wherein the first gate is biased by the mirror reference voltage;

conducting a second current through a second branch between the first node and the second node, the second branch comprising a second switch connected in series with a second transistor in response to enabling the second switch by the enable signal; and

adding a second charge to the bias rail through a second capacitance between a second drain and a second gate of the second transistor, wherein the second gate is biased by the mirror reference voltage.

10. A fast-enabled power supply, comprising:

a first branch comprising a first transistor having a first drain connected to a protection device, a first source connected to a first switch, and a first gate connected to a bias rail, the protection device connected to a first node, the first switch configured to short the first source to a second node in response to an enable signal;

a first parasitic capacitance between the first gate and the first source;

a second branch comprising a second transistor having a second drain connected to a second switch, a second source connected to a compensation device, and a second gate connected to the bias rail, the compensation device connected to the second node, the second switch configured to short the second drain to the first node in response to the enable signal; and

a second parasitic capacitance between the second drain and the second gate, wherein first charge removed from the bias rail by the first capacitance is cancelled by second charge added to the bias rail by the second capacitance in response to the enable signal.

Technical Field

The present disclosure relates generally to switchable power supplies and, more particularly, to power supplies that can be quickly started while minimizing settling time.

Background

Low power integrated circuits ("ICs") often use circuits or groups of blocks that are periodically enabled and disabled to conserve power. For example, in a DC/DC power converter operating in a Pulse Frequency Modulation (PFM) mode, a circuit block switches between an active state and an inactive state at each clock cycle. Generally, these circuit blocks include digital circuits that are turned on or off, and analog circuits that have power supplies that are also switched. For high performance analog circuits that require fast and stable response, these power supplies must turn on quickly and settle to a stable value in a short period of time.

Previous attempts to solve the problem of quickly enabling power supplies have included the use of current control circuits that waste current and are not suitable for low power circuits. Another solution utilizes a closed loop circuit, which reduces the settling time of the output current and consumes a significant amount of static power in some cases. Finally, another previous solution uses large capacitors that are large in area, slow and often sensitive to load conditions.

Disclosure of Invention

According to a first aspect of the present invention there is provided a fast-enabling power supply comprising:

a bias chain configured to generate a mirror reference voltage on a bias rail;

a first branch comprising a first transistor having a first drain connected to a first node, a first source connected to a first switch, and a first gate connected to the bias rail, the first switch configured to short the first source to a second node in response to an enable signal;

a first capacitor between the first gate and the first source;

a second branch comprising a second transistor having a second drain connected to a second switch, a second source connected to the second node, and a second gate connected to the bias rail, the second switch configured to short the second drain to the first node in response to the enable signal; and

a second capacitance between the second drain and the second gate, wherein first charge removed from the bias rail by the first capacitance is cancelled by second charge added to the bias rail by the second capacitance in response to the enable signal.

In accordance with one or more embodiments, the first charge is equal to the second charge, and a first width of the first transistor divided by a second width of the second transistor defines an optimal transistor ratio.

In accordance with one or more embodiments, the optimal transistor ratio is one-half, wherein each of the transistors of the fast-enabled power supply comprises an n-channel field effect transistor.

According to one or more embodiments, the first switch comprises an n-channel field effect transistor comprising: a first switch drain connected to the first source; a first switch gate connected to the enable signal, the enable signal configured to enable the first switch; and a first switched source connected to the second node.

In accordance with one or more embodiments, the second switch comprises a high voltage n-channel field effect transistor comprising: a second switch drain connected to the first node; a second switch gate connected to the enable signal, the enable signal configured to enable the second switch; and a second switch source connected to the second drain.

In accordance with one or more embodiments, the bias chain includes a bias transistor including a bias drain connected to a power supply, a bias gate connected to the bias drain and the bias rail, and a bias source connected to the second node.

According to one or more embodiments, further comprising a bias compensation device connected between the bias source and the second node, wherein the bias compensation device has the same voltage drop as the first switch when the first switch is enabled.

According to one or more embodiments, the protection device is connected between the first node and the first drain, wherein the protection device has the same voltage drop as the second switch when the second switch is enabled.

According to one or more embodiments, the first switch is configured to be turned on and off, and the compensation device is connected between the second source and the second node, wherein when the first switch is enabled, the compensation device has the same voltage drop as the first switch.

According to one or more embodiments, the first capacitance is a first parasitic capacitance of the first transistor, and the second capacitance is a second parasitic capacitance of the second transistor.

According to a second aspect of the present invention, there is provided a method for quickly enabling a power supply, comprising:

generating a mirror reference voltage on the bias rail;

conducting a first current through a first branch between a first node and a second node, the first branch comprising a first transistor connected in series with a first switch in response to the first switch being enabled by an enable signal;

removing a first charge from the bias rail through a first capacitance between a first gate and a first source of the first transistor, wherein the first gate is biased by the mirror reference voltage;

conducting a second current through a second branch between the first node and the second node, the second branch comprising a second switch connected in series with a second transistor in response to enabling the second switch by the enable signal; and

adding a second charge to the bias rail through a second capacitance between a second drain and a second gate of the second transistor, wherein the second gate is biased by the mirror reference voltage.

In accordance with one or more embodiments, further comprising determining an optimal transistor ratio by dividing a first width of the first transistor by a second width of the second transistor, wherein the optimal transistor ratio results in the first charge being equal to the second charge.

In accordance with one or more embodiments, determining the optimal transistor ratio results in the first width being half of the second width, wherein each of the transistors of the power supply comprises an n-channel field effect transistor.

According to one or more embodiments, further comprising compensating an impedance of the second switch by a protection device between the first node and the first drain, wherein the protection device has a same voltage drop as the second switch when the second switch is enabled.

According to one or more embodiments, further comprising compensating an impedance of the first switch by a compensation device between the second source and the second node, wherein the compensation device has the same voltage drop as the first switch when the first switch is enabled.

In accordance with one or more embodiments, generating the mirrored reference voltage includes supplying current through a bias transistor including a bias drain connected to a power supply, a bias gate connected to the bias drain and the bias rail, and a bias source connected to the second node.

According to one or more embodiments, further comprising compensating an impedance of the first switch by a bias compensation device connected between the biased source and the second node, wherein the bias compensation device has the same voltage drop as the first switch when the first switch is enabled.

According to a third aspect of the present invention there is provided a fast-enabled power supply comprising:

a first branch comprising a first transistor having a first drain connected to a protection device, a first source connected to a first switch, and a first gate connected to a bias rail, the protection device connected to a first node, the first switch configured to short the first source to a second node in response to an enable signal;

a first parasitic capacitance between the first gate and the first source;

a second branch comprising a second transistor having a second drain connected to a second switch, a second source connected to a compensation device, and a second gate connected to the bias rail, the compensation device connected to the second node, the second switch configured to short the second drain to the first node in response to the enable signal; and

a second parasitic capacitance between the second drain and the second gate, wherein first charge removed from the bias rail by the first capacitance is cancelled by second charge added to the bias rail by the second capacitance in response to the enable signal.

In accordance with one or more embodiments, the protection device has the same voltage drop as the second switch when the second switch is enabled.

According to one or more embodiments, the compensation device has the same voltage drop as the first switch when the first switch is enabled.

Drawings

The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

FIG. 1 is a schematic diagram of a fast-enabled power supply according to an example embodiment of the present disclosure.

FIG. 2 is a schematic diagram of a fast-enabled power supply according to an example embodiment of the present disclosure.

FIG. 3 is a graphical view of timing waveforms for an enable signal using the embodiment of FIG. 2.

FIG. 4 is a graphical view of timing waveforms of the generated currents using the embodiment of FIG. 2.

FIG. 5 is a graphical view of timing waveforms of enable signals without using a fast-enabled power supply.

FIG. 6 is a graphical view of timing waveforms of current generated without using a fast-enabled power supply.

FIG. 7 is a flowchart representation of a method for generating a fast-enabled power supply according to an example embodiment of the present disclosure.

Detailed Description

Various embodiments described herein provide for fast enablement of a switching power supply to minimize settling time and thereby provide a stable and accurate current output more quickly. In particular, the circuits and methods of embodiments of the present disclosure use two switched current branches that combine to provide a stable power supply output with negligible area increase and minimal impact on quiescent current. Each branch is referred to as a bias current branch and includes a switched drain or switched source of the respective transistor to counteract charge removal (e.g., mirror reference) on the bias line, while charge injection occurs on the same bias line. Counteracting charge removal, either fully or partially, by charge injection involves designing the respective transistors on each branch to have an optimal transistor ratio. In one embodiment, the respective transistor widths define an optimal transistor ratio, and thus the respective parasitic capacitances of the transistors. Charge removal or injection occurs through these parasitic capacitances in response to the respective transistors of the enabled current branches.

Fig. 1 illustrates an embodiment 10 of a fast-enabled power supply according to the present disclosure. Embodiment 10 includes a bias chain 12 connected between a bias supply 14 and a second node 16. A power supply 18 is connected between the bias power supply 14 and the bias transistor 20. The bias transistor 20 includes a bias drain 22 connected to the power supply 18, a bias source 24 connected to the second node 16, and a bias gate 26 connected to the bias drain 22 and a bias rail 28.