Wireless terminal, clock synchronization method and system
阅读说明：本技术 无线终端、时钟同步方法及系统 (Wireless terminal, clock synchronization method and system ) 是由 杨申 于 2020-06-02 设计创作，主要内容包括：本公开实施例公开了一种无线终端、时钟同步方法及系统,所述无线终端包括：GPS模块、PLL模块、误差计算模块和同步处理模块；所述GPS模块用于持续监测GPS授时信号；PLL模块用于产生预定频率的内部时钟信号；误差计算模块用于,接收GPS授时信号,接收内部时钟信号,若GPS授时信号未消失,通过所述内部时钟信号对所监测的GPS授时信号进行计数,根据计数结果确定GPS授时信号的真实频率,根据真实频率确定预定频率的误差值；所述同步处理模块用于,接收所述内部时钟信号,根据所述内部时钟信号的计数值和所述误差值计算通信时间,以及根据所计算的通信时间发送信号,使时钟同步系统中各无线终端在GPS授时信号中断时也能同步通信。(The embodiment of the disclosure discloses a wireless terminal, a clock synchronization method and a system, wherein the wireless terminal comprises: the system comprises a GPS module, a PLL module, an error calculation module and a synchronous processing module; the GPS module is used for continuously monitoring GPS time service signals; the PLL module is used for generating an internal clock signal with a preset frequency; the error calculation module is used for receiving a GPS time service signal, receiving an internal clock signal, counting the monitored GPS time service signal through the internal clock signal if the GPS time service signal does not disappear, determining the real frequency of the GPS time service signal according to the counting result, and determining the error value of the preset frequency according to the real frequency; the synchronous processing module is used for receiving the internal clock signal, calculating communication time according to the count value of the internal clock signal and the error value, and sending a signal according to the calculated communication time, so that each wireless terminal in the clock synchronous system can synchronously communicate when the GPS time service signal is interrupted.)
1. A wireless terminal is characterized by comprising a GPS module, a PLL module, an error calculation module and a synchronous processing module;
the GPS module is used for continuously monitoring GPS time service signals;
the PLL module is used for generating an internal clock signal with a preset frequency;
the error calculation module is used for receiving the GPS time service signal and receiving the internal clock signal, counting the monitored GPS time service signal through the internal clock signal if the GPS time service signal does not disappear, determining the real frequency of the GPS time service signal according to the counting result, and determining the error value of the preset frequency according to the real frequency;
the synchronous processing module is used for receiving the internal clock signal, calculating communication time according to the count value of the internal clock signal and the error value, and sending a signal according to the calculated communication time.
2. The wireless terminal of claim 1, wherein calculating a communication time based on the count value of the internal clock signal and the error value comprises: compensating the internal clock signal according to the error value to calculate a communication time.
3. The wireless terminal of claim 1, further comprising a digital compensated crystal oscillator and a digital-to-analog converter;
the input end of the digital-to-analog converter is connected with the error calculation module, and the output end of the digital-to-analog converter is connected with the input end of the digital compensation crystal oscillator;
the output end of the digital compensation crystal oscillator is connected with the PLL module;
the error calculation module is used for inputting the error value into the digital-to-analog converter, and the digital-to-analog converter is used for converting the error value into an analog signal and inputting the analog signal into the digital compensation crystal oscillator;
the digital compensation crystal oscillator is used for adjusting the frequency of a clock signal generated by the PLL module according to the received analog signal, so that the digital-to-analog converter adjusts the analog signal input to the digital compensation crystal oscillator according to the received error value, and the oscillation frequency of the digital compensation crystal oscillator is adjusted.
4. The wireless terminal according to claim 3, further comprising a locking module, configured to receive an error value of the error calculation module if the error calculation module is in an unlocked state, and control the error calculation module to enter a locked state when the error value is smaller than a predetermined error threshold within a predetermined time period.
5. The wireless terminal of claim 4, wherein the locking module is further configured to control the error calculation module to enter an unlocked state if the GPS time signal disappears.
6. The wireless terminal of claim 4, wherein the locking module is further configured to periodically control the error calculation module to enter an unlocked state.
7. The wireless terminal according to claim 1, wherein the synchronization processing module is further configured to receive a GPS time signal monitored by the GPS module, receive the internal clock signal if the GPS time signal disappears, and calculate a communication time according to a count value of the internal clock signal and the error value; and if the GPS time service signal does not disappear, calculating communication time according to the GPS time service signal.
8. A method of clock synchronization, performed by a wireless terminal, the method comprising:
continuously monitoring a GPS time service signal and generating an internal clock signal with a preset frequency;
if the GPS time service signal does not disappear, counting the monitored GPS time service signal through the internal clock signal, determining the real frequency of the GPS time service signal according to the counting result, and determining the error value of the preset frequency according to the real frequency;
calculating a communication time according to the count value of the internal clock signal and the error value, and transmitting a signal according to the calculated communication time.
9. The clock synchronization method of claim 8, wherein the calculating a communication time from the count value of the internal clock signal and the error value comprises:
if the GPS time service signal disappears, calculating communication time according to the count value of the internal clock signal and the error value;
and if the GPS time service signal does not disappear, calculating communication time according to the GPS time service signal.
10. A clock synchronization system comprising a plurality of wireless terminals according to any of claims 1-7.
Technical Field
The embodiment of the disclosure relates to the technical field of wireless communication, in particular to a wireless terminal, a clock synchronization method and a clock synchronization system.
Background
Time Division Duplex (TDD) wireless communication over the public network can provide Time synchronization via a base station, but TDD communication over SDR (Software defined Radio) without a base station cannot provide a Time reference via the base station.
In order to solve the problem of time synchronization of multiple components or modules in an SDR, GPS (global positioning System) satellite time service is usually adopted to perform time synchronization, so that multiple components in the SDR all communicate based on the same time reference, thereby achieving time synchronization of the whole SDR.
The GPS signal may be interrupted in special environments such as buildings, underground, culverts and the like, once some parts or modules in the SDR enter the special environments, the time synchronization may be interrupted because the GPS time service signal cannot be received.
Disclosure of Invention
In view of the above, embodiments of the present disclosure provide a wireless terminal, a clock synchronization method and a clock synchronization system, so that each wireless terminal in the clock synchronization system can synchronize communication even when the GPS signal is interrupted.
Additional features and advantages of the disclosed embodiments will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosed embodiments.
In a first aspect of the present disclosure, an embodiment of the present disclosure provides a wireless terminal, including a GPS module, a PLL module, an error calculation module, and a synchronization processing module;
the GPS module is used for continuously monitoring GPS time service signals;
the PLL module is used for generating an internal clock signal with a preset frequency;
the error calculation module is used for receiving the GPS time service signal, receiving the internal clock signal, counting the monitored GPS time service signal through the internal clock signal if the GPS time service signal does not disappear, determining the real frequency of the GPS time service signal according to the counting result, and determining the error value of the preset frequency according to the real frequency;
the synchronous processing module is used for receiving the internal clock signal, calculating communication time according to the count value of the internal clock signal and the error value, and sending a signal according to the calculated communication time.
In one embodiment, calculating the communication time according to the count value of the internal clock signal and the error value comprises: compensating the internal clock signal according to the error value to calculate a communication time.
In one embodiment, the wireless terminal further comprises a digital compensated crystal oscillator and a digital-to-analog converter;
the input end of the digital-to-analog converter is connected with the error calculation module, and the output end of the digital-to-analog converter is connected with the input end of the digital compensation crystal oscillator;
the output end of the digital compensation crystal oscillator is connected with the PLL module;
the error calculation module is used for inputting the error value into the digital-to-analog converter, and the digital-to-analog converter is used for converting the error value into an analog signal and inputting the analog signal into the digital compensation crystal oscillator;
the digital compensation crystal oscillator is used for adjusting the frequency of a clock signal generated by the PLL module according to the received analog signal, so that the digital-to-analog converter adjusts the analog signal input to the digital compensation crystal oscillator according to the received error value, and the oscillation frequency of the digital compensation crystal oscillator is adjusted.
In an embodiment, the wireless terminal further includes a locking module, configured to receive an error value of the error calculation module if the error calculation module is in an unlocked state, and control the error calculation module to enter a locked state when the error value is smaller than a predetermined error threshold within a predetermined time period.
In an embodiment, the locking module is further configured to control the error calculation module to enter an unlocked state if the GPS time signal disappears.
In an embodiment, the locking module is further configured to periodically control the error calculation module to enter an unlocked state.
In an embodiment, the synchronous processing module is further configured to receive a GPS time signal monitored by the GPS module, where the GPS time signal disappears, receive the internal clock signal, and calculate a communication time according to a count value of the internal clock signal and the error value; and if the GPS time service signal does not disappear, calculating communication time according to the GPS time service signal.
In a second aspect of the present disclosure, an embodiment of the present disclosure further provides a clock synchronization method, performed by a wireless terminal, the method including:
continuously monitoring a GPS time service signal and generating an internal clock signal with a preset frequency;
if the GPS time service signal does not disappear, counting the monitored GPS time service signal through the internal clock signal, determining the real frequency of the GPS time service signal according to the counting result, and determining the error value of the preset frequency according to the real frequency;
calculating a communication time according to the count value of the internal clock signal and the error value, and transmitting a signal according to the calculated communication time.
In one embodiment, the calculating the communication time according to the count value of the internal clock signal and the error value includes: if the GPS time service signal disappears, calculating communication time according to the count value of the internal clock signal and the error value; and if the GPS time service signal does not disappear, calculating communication time according to the GPS time service signal.
In a third aspect of the present disclosure, an embodiment of the present disclosure further provides a clock synchronization system, including a plurality of wireless terminals as described in the first aspect.
The technical scheme provided by the embodiment of the disclosure has the beneficial technical effects that:
the GPS timing signal is continuously monitored through the GPS module, the internal clock signal with the preset frequency is generated through the PLL module, when the GPS timing signal does not disappear through the error calculation module, the monitored GPS timing signal is counted through the internal clock signal to determine the real frequency of the GPS timing signal, the error value of the frequency of the internal clock signal is determined according to the real frequency, the communication time is calculated through the synchronous processing module according to the count value and the error value of the internal clock signal to send the signal according to the real frequency, and therefore all wireless terminals in the clock synchronization system can synchronously communicate when the GPS signal is interrupted.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments of the present disclosure will be briefly described below, and it is obvious that the drawings in the following description are only a part of the embodiments of the present disclosure, and for those skilled in the art, other drawings can be obtained according to the contents of the embodiments of the present disclosure and the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a wireless terminal provided according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of another wireless terminal provided in accordance with an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of another wireless terminal provided according to an embodiment of the present disclosure;
FIG. 4 is a control flow diagram of a lock module provided in accordance with an embodiment of the present disclosure;
FIG. 5 is a schematic structural diagram of a clock synchronization system provided in accordance with an embodiment of the present disclosure;
fig. 6 is a schematic flowchart of a clock synchronization method according to an embodiment of the present disclosure.
Detailed Description
In order to make the technical problems solved, technical solutions adopted and technical effects achieved by the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described in further detail below with reference to the accompanying drawings, and it is obvious that the described embodiments are only some embodiments, but not all embodiments, of the embodiments of the present disclosure. All other embodiments, which can be obtained by a person skilled in the art without making creative efforts based on the embodiments of the present disclosure, belong to the protection scope of the embodiments of the present disclosure.
It should be noted that the terms "system" and "network" are often used interchangeably in the embodiments of the present disclosure. Reference to "and/or" in embodiments of the present disclosure is meant to include any and all combinations of one or more of the associated listed items. The terms "first", "second", and the like in the description and claims of the present disclosure and in the drawings are used for distinguishing between different objects and not for limiting a particular order.
It should also be noted that, in the embodiments of the present disclosure, each of the following embodiments may be executed alone, or may be executed in combination with each other, and the embodiments of the present disclosure are not limited specifically.
The names of messages or information exchanged between devices in the embodiments of the present disclosure are for illustrative purposes only, and are not intended to limit the scope of the messages or information.
The technical solutions of the embodiments of the present disclosure are further described by the following detailed description in conjunction with the accompanying drawings.
Fig. 1 shows a schematic structural diagram of a wireless terminal according to an embodiment of the present disclosure, which is applicable to a situation where the wireless terminal continues to perform synchronous communication during a GPS time service signal interruption period, as shown in fig. 1, the wireless terminal according to the embodiment includes a
The
In the embodiment, a GPS time signal is continuously monitored through a GPS module, an internal clock signal with a preset frequency is generated through a PLL module, when the GPS time signal is not disappeared, the error calculation module counts the monitored GPS time signal through the internal clock signal to determine the real frequency of the GPS time signal, the error value of the frequency of the internal clock signal is determined according to the real frequency, the communication time is calculated according to the count value and the error value of the internal clock signal through a synchronous processing module to send the signal according to the real frequency, and each wireless terminal in the clock synchronization system can synchronously communicate when the GPS time signal is interrupted.
Further, in the above embodiments, the
As shown in fig. 2, the wireless terminal includes a
On the basis of the embodiment shown in fig. 1, the
Further, in order to save power consumption, the
Further, if the GPS time service signal disappears, the error calculation module is controlled to enter an unlocking state so as to reinitialize the pulse frequency of the PLL module after the GPS time service signal is recovered until the error of the pulse frequency is stably controlled within an allowable precision range.
Further, the
Fig. 4 is a schematic control flow diagram of a lock module according to an embodiment of the present disclosure, as shown in fig. 4, for example, a PLL module may be used to generate a clock signal with a frequency of 1GHz, so that the time counting precision may be 1 nanosecond, and this embodiment may also use other clock frequencies to count time according to the precision requirement.
The pulse-per-second signal received by the GPS module is denoted by PPS _ IN, and the timing signal finally used by the wireless terminal is denoted by PPS _ OUT. The frequency at which the GPS module can receive the PPS _ IN is related to the time accuracy thereof, and for example, the GPS module receives pulses of seconds, one second receives one PPS _ IN signal, i.e., the time interval between adjacent pulses of seconds is 1 second. The time interval of the PPS _ IN signal is counted with a 1GHz clock signal. Theoretically, a pulse with a frequency of 1GHz should be 1000000000 times per second. Due to the crystal oscillator error, the exact 1000000000 cannot be obtained, and the practical result is usually more or less than 1000000000. For example, if the count is 1GHz, the actual count of the adjacent second pulses of PPS _ IN may be 1000010000 times per second, and the clock is used to count the time interval of PPS _ IN, the result will be 1.000010000 seconds, and the timing is not accurate, so that the timing is performed according to the frequency generated by the PLL module, and the timing is synchronized with the timing signal received by the GPS module.
Because some wireless terminals in the same clock synchronization system can not time according to the signal of the GPS module temporarily, and need to use a local PLL module for timing, the problem of non-uniformity of the PLL module and the GPS timing needs to be avoided. The problem of non-uniform timing can be solved by adopting various modes.
For example, the error value may be directly recorded, and the counting result may be directly compensated according to the error value, and referring to fig. 1, the terminal using the local PLL timing uses the error calculated in the previous time to compensate the next PPS _ OUT based on the local PLL timing, so as to keep the timing consistent with the GPS module timing.
For another example, the digital compensated crystal oscillator DCXO may be further used to adjust the PLL module, determine the error according to the count of the PLL module, and adjust the DCXO by using the digital-to-analog converter DAC, so that the error value between the timing by using the PLL module and the timing by using the GPS module is within a certain error range, and the schematic structural diagram of the terminal refers to fig. 2.
As shown in fig. 2, a lock module may be provided to control whether the error calculation module is operational. In one aspect, the locking module may be configured to control the error calculation module to enter a locked state and stop working. Specifically, the error value of the error calculation module may be received when the error calculation module is in the unlocked state, and when the error value is smaller than the predetermined error threshold value within a predetermined time period, the error calculation module is controlled to enter the locked state, for example, the error value continues to stabilize within 500ns (nanoseconds) for 5 minutes.
On the other hand, the locking module can also control the error calculation module to enter an unlocking state to work. For example, if the GPS time signal disappears, the error calculation module is controlled to enter an unlocked state, or, for example, the error calculation module may be periodically controlled to enter an unlocked state.
If the PPS _ IN signal is monitored to disappear, the locking module controls the error calculation module to enter an unlocking state, the wireless terminal adopts a local PLL module to time, and the stage (PPS _ IN signal disappearance stage) can be called a holding stage. After the locking module controls the error calculation module to enter the unlocking state, if the PPS _ IN signal can be monitored, the error calculation module can adjust the DCXO through the DAC according to the error magnitude between the PPS _ OUT and the PPS _ IN, and the adjustment process can be called a taming stage. If the locking module controls the error calculation module to enter the locking state, the locking state continuation phase can be called a locking phase.
Fig. 4 shows an example of a jump process at the wireless terminal IN the above three states, as shown IN fig. 4, after the wireless terminal is powered on, if the PPS _ IN signal can be received, the clock signal of the PLL module is adjusted by using the GPS clock, and the tame stage is entered.
The specific adjustment method includes various, for example, during the acclimation phase, the DCXO can be adjusted by the DAC according to the error magnitude between PPS _ OUT and PPS _ IN. For example, IN the training phase, the frequency of 1G output by the PLL module is taken as an example, and the time interval of PPS _ IN can be calculated by using the number of pulses of the PLL module and compared with the theoretical value of 1000000000. And obtaining a corresponding error value, converting the error value into a control voltage adjustment value of the DCXO, and then adjusting the DCXO through the DAC, so that the 1GHz output by the local PLL tends to be accurate, and the error is in a nanosecond level. Taking the error threshold as 500ns as an example, the actual error threshold can be configured as required, so that after the acclimation stage is completed, the error between PPS _ OUT and PPS _ IN can be controlled within 500 ns. This process needs to be repeated for a plurality of times, and when the error is within 500ns and the error lasts for a predetermined time (for example, 5 minutes), if the errors are within 500ns, the crystal oscillator is stable and the accuracy is satisfactory, the error calculation module can be controlled to enter the locking state, and the stage in the locking state is called the locking stage.
The DCXO is not adjusted during the locking phase, but the error between PPS _ OUT and PPS _ IN may be continuously calculated, for example, if the error is continuously monitored for more than 500ns within 5 seconds, the error calculation module is controlled to enter the unlocking state, and the domestication phase is returned again. IN the locking phase, if the PPS _ IN signal is monitored to disappear, a holding state is entered. Whether the PPS _ IN disappears or not can be determined by reading the state of the GPS module, and whether a PPS _ IN signal is received or not can be monitored.
IN the hold phase, since PPS _ IN is inactive, the local PPS _ OUT is continuously output according to the output of the lock phase PLL. According to tests, the PPS _ OUT can be kept at the error precision of 1 microsecond within 1 hour by adopting a high-precision low-temperature drift crystal oscillator. IN the hold state, if PPS _ IN can be detected again, the locking phase can be returned again.
According to the technical scheme of the embodiment, the timing of the local PLL module is adjusted and acclimated through the time service signal received by the GPS module, so that each wireless terminal can determine accurate time by adopting the local PLL module at the time service interruption stage received by the GPS module, and the inertia and stability of synchronous communication can be maintained.
Fig. 5 is a schematic structural diagram of a clock synchronization system according to an embodiment of the present disclosure, and as shown in fig. 5, the clock synchronization system according to this embodiment includes a plurality of wireless terminals corresponding to the embodiments described in fig. 1 to fig. 4. In a clock synchronization system including N wireless terminals (N is a natural number greater than 2), the wireless terminals implement communication in a manner of respective communication time, that is, each wireless terminal performs signal transmission at the allocated communication time and performs reception at other times. At this time, in order to ensure that communication between wireless terminals does not conflict, each wireless terminal is required to be able to accurately calculate the transmission time, and N terminals need to keep time accurate synchronization.
By means of the embodiment, for SDR TDD communication, a central endpoint is not required. In the beginning stage, each wireless terminal is automatically synchronized to the PPS of the GPS, and each wireless terminal automatically selects own communication time by taking the PPS as a reference according to an upper-layer protocol strategy. And when the GPS signal disappears, the PPS after local correction is used as a clock reference, so that the accurate synchronization of the communication of each wireless terminal in the clock synchronization system is ensured.
Fig. 6 is a schematic flowchart of a clock synchronization method according to an embodiment of the present disclosure, where this embodiment is applicable to a case where any wireless terminal in a clock synchronization system calculates a communication time transmission signal, and the method may be executed by any wireless terminal in the clock synchronization system, as shown in fig. 6, the clock synchronization method according to this embodiment includes:
in step S610, the GPS time signal is continuously monitored, and an internal clock signal of a predetermined frequency is generated. In the step, the GPS time signal can be continuously monitored through a GPS module arranged in the wireless terminal, and an internal clock signal with a preset frequency is generated through a PLL module arranged in the wireless terminal.
In step S620, if the GPS time signal does not disappear, the monitored GPS time signal is counted by the internal clock signal, a real frequency of the GPS time signal is determined according to a count result, and an error value of the predetermined frequency is determined according to the real frequency.
In step S630, a communication time is calculated according to the count value of the internal clock signal and the error value, and a signal is transmitted according to the calculated communication time. This step can be implemented in a variety of ways, for example, mathematically compensating the internal clock signal for the error value to calculate the communication time. For another example, the frequency of the internal clock signal generated by the PLL module may be adjusted to gradually reduce the error, and specifically, a digital compensated crystal oscillator and a digital-to-analog converter may be used to adjust the frequency of the internal clock signal generated by the PLL module according to the error value to be infinitely close to the predetermined frequency according to the structure shown in fig. 2.
In some embodiments, the communication time may be continuously calculated according to the count value of the internal clock signal and the error value, and may be calculated according to whether the GPS time signal is good or not, and selectively according to the count value of the internal clock signal and the error value. The method specifically comprises the following steps: if the GPS time service signal disappears, calculating communication time according to the count value of the internal clock signal and the error value; and if the GPS time service signal does not disappear, calculating communication time according to the GPS time service signal.
In this embodiment, a GPS time signal is continuously monitored by any wireless terminal in the clock synchronization system, and an internal clock signal with a predetermined frequency is generated, if the GPS time signal does not disappear, the monitored GPS time signal is counted by the internal clock signal to determine a real frequency, an error value is determined according to the real frequency, communication time is calculated according to a count value of the internal clock signal and the error value, and a signal is transmitted according to the calculated communication time, so that each wireless terminal in the clock synchronization system can perform synchronous communication even when the GPS time signal is interrupted.
The foregoing description is only a preferred embodiment of the disclosed embodiments and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the disclosure in the embodiments of the present disclosure is not limited to the particular combination of the above-described features, but also encompasses other embodiments in which any combination of the above-described features or their equivalents is possible without departing from the scope of the present disclosure. For example, the above features and (but not limited to) the features with similar functions disclosed in the embodiments of the present disclosure are mutually replaced to form the technical solution.
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