阅读说明：本技术 一种半双工中继电路 (Half-duplex relay circuit ) 是由 郑德华 赵显云 于 2020-06-12 设计创作，主要内容包括：本发明公开了一种半双工中继电路,包括第一RS485芯片U1、第二RS485芯片U2、第一反相器U3、第二反相器U4、上拉电阻R7、上拉电阻R9、电容C1、电容C2、电阻R9以及电阻R10,第一RS485芯片U1从总线1上获得数据包,并输出低电平有效的脉冲信号至第二反相器U4,反向后输出高电平,以使第二RS485芯片U2为发送状态,完成总线1到总线2的信号中继,总线2到总线1的中继与总线1到总线2的中继相反,能很好解决现有信号中继器只能单向传输信号的缺点,中继器的安装布置变得简单；且由于采用非隔离式,成本低、电路简单可靠。(The invention discloses a half-duplex relay circuit, which comprises a first RS485 chip U1, a second RS485 chip U2, a first inverter U3, a second inverter U4, a pull-up resistor R7, a pull-up resistor R9, a capacitor C1, a capacitor C2, a resistor R9 and a resistor R10, wherein the first RS485 chip U1 obtains a data packet from a bus 1, outputs a low-level effective pulse signal to the second inverter U4, and outputs a high level after reversing so that the second RS485 chip U2 is in a sending state to complete signal relay from the bus 1 to the bus 2, the relay from the bus 2 to the bus 1 is opposite to the relay from the bus 1 to the bus 2, the defect that the existing signal relay can only transmit signals in a single direction can be well solved, and the installation arrangement of the relay becomes simple; and because the non-isolated type is adopted, the cost is low, and the circuit is simple and reliable.)

1. A half-duplex relay circuit, comprising: the bus interface circuit comprises a first RS485 chip U1, a second RS485 chip U2, a first inverter U3, a second inverter U4, a pull-up resistor R7 and a pull-up resistor R9, wherein the A end and the B end of the first RS485 chip U1 are respectively connected with a bus 1, the RO end of the first RS485 chip U1 is respectively connected with the input end of the second inverter U4 and the DI end of the second RS485 chip U2, and the output end of the second inverter U4 is respectively connected with the DI end of the second RS485 chip U1The end is connected with the DE end, the DI end of the first RS485 chip U1 is respectively connected with the RO end of the second RS485 chip U2 and the input end of the first phase inverter U3, and the output end of the first phase inverter U3 is respectively connected with the output end of the first RS485 chip U1The end of the second RS485 chip U2 is connected with the DE end, the A end and the B end of the second RS485 chip U2 are respectively connected with the bus 2, one end of a pull-up resistor R7 is connected with the input end of a first inverter U3, the other end of the pull-up resistor R7 is respectively connected with an external power supply and the power supply end of the first inverter U3, one end of a pull-up resistor R9 is connected with the input end of a second inverter U4, and the other end of the pull-up resistor R9 is connected with the power supply end of the second inverter U4; the LED driving circuit further comprises a resistor R10 and a capacitor C2, one end of the resistor R10 is connected with the RO end of the first RS485 chip U1 and the DI end of the second RS485 chip U2 respectively, the other end of the resistor R10 is connected with the pull-up resistor R9, one end of the capacitor C2 and the input end of the second inverter U4 respectively, and the other end of the capacitor C2 is connected with the ground end; the LED driving circuit further comprises a resistor R8 and a capacitor C1, one end of the resistor R8 is connected with the DI end of the first RS485 chip U1 and the RO end of the second RS485 chip U2 respectively, the other end of the resistor R8 is connected with one end of a pull-up resistor R7, one end of a capacitor C1 and the input end of the first inverter U3 respectively, and the other end of the capacitor C1 is connected with the ground end.

2. The half-duplex relay circuit of claim 1, wherein: the LED module further comprises a diode D1 and a diode D2, wherein the anode of the diode D1 is connected with the capacitor C1, the cathode of the diode D1 is connected with the DI end of the first RS485 chip U1 and the RO end of the second RS485 chip U2, the anode of the diode D2 is connected with the capacitor C2, and the cathode of the diode D2 is connected with the RO end of the first RS485 chip U1 and the DI end of the second RS485 chip U2.

3. The half-duplex relay circuit of claim 1, wherein: still include resistance R2 and resistance R5, the one end of resistance R2 is connected with B end and bus 1 of first RS485 chip U1 respectively, the other end of resistance R2 is connected with A end and bus 1 of first RS485 chip U1 respectively, the one end of resistance R5 is connected with B end and bus 2 of second RS485 chip U2 respectively, the other end of resistance R5 is connected with A end and bus 2 of first RS485 chip U2 respectively.

4. A half-duplex relay circuit according to claim 3, wherein: still include resistance R1, resistance R3, resistance R4 and resistance R6, the one end ground connection of resistance R1, the other end and the resistance R2 of resistance R1 are connected, the one end and the external power supply of resistance R3 are connected, the other end and the resistance R2 of resistance R3 are connected, the one end ground connection of resistance R4, the other end and the resistance R5 of resistance R4 are connected, the one end and the external power supply of resistance R6 are connected, the other end and the resistance R5 of resistance R6 are connected.

Technical Field

The invention relates to the technical field of relay circuits, in particular to a half-duplex relay circuit.

Background

Disclosure of Invention

The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides a non-isolated half-duplex relay circuit which is low in cost, simple and reliable in circuit.

The technical scheme adopted by the embodiment of the invention for solving the technical problem is as follows: a half-duplex relay circuit comprises a first RS485 chip U1, a second RS485 chip U2, a first phase inverter U3, a second phase inverter U4, a pull-up resistor R7 and a pull-up resistor R9, wherein an A end and a B end of a first RS485 chip U1 are respectively connected with a bus 1, an RO end of the first RS485 chip U1 is respectively connected with an input end of the second phase inverter U4 and a DI end of a second RS485 chip U2, and an output end of the second phase inverter U4 is respectively connected with an output end of the second RS485 chip U1

The end is connected with the DE end, the DI end of the first RS485 chip U1 is respectively connected with the RO end of the second RS485 chip U2 and the input end of the first phase inverter U3, and the output end of the first phase inverter U3 is respectively connected with the output end of the first RS485 chip U1The end of the second RS485 chip U2 is connected with the DE end, the A end and the B end of the second RS485 chip U2 are respectively connected with the bus 2, one end of a pull-up resistor R7 is connected with the input end of a first inverter U3, the other end of the pull-up resistor R7 is respectively connected with an external power supply and the power supply end of the first inverter U3, one end of a pull-up resistor R9 is connected with the input end of a second inverter U4, and the other end of the pull-up resistor R9 is connected with the power supply end of the second inverter U4; the LED driving circuit further comprises a resistor R10 and a capacitor C2, one end of the resistor R10 is connected with the RO end of the first RS485 chip U1 and the DI end of the second RS485 chip U2 respectively, the other end of the resistor R10 is connected with the pull-up resistor R9, one end of the capacitor C2 and the input end of the second inverter U4 respectively, and the other end of the capacitor C2 is connected with the ground end; the LED driving circuit further comprises a resistor R8 and a capacitor C1, one end of the resistor R8 is connected with the DI end of the first RS485 chip U1 and the RO end of the second RS485 chip U2 respectively, the other end of the resistor R8 is connected with the pull-up resistor R7, one end of the capacitor C1 and the input end of the first inverter U3 respectively, and the other end of the capacitor C1 is connected with the DI end of the first RS485 chip U1 and the input end of the second RS485 chip U38One end is connected with the grounding end.

The half-duplex relay circuit further comprises a diode D1 and a diode D2, wherein the anode of the diode D1 is connected with a capacitor C1, the cathode of the diode D1 is respectively connected with the DI end of the first RS485 chip U1 and the RO end of the second RS485 chip U2, the anode of the diode D2 is connected with the capacitor C2, and the cathode of the diode D2 is respectively connected with the RO end of the first RS485 chip U1 and the DI end of the second RS485 chip U2.

The half-duplex relay circuit further comprises a resistor R2 and a resistor R5, one end of the resistor R2 is connected with the end B of the first RS485 chip U1 and the bus 1, the other end of the resistor R2 is connected with the end A of the first RS485 chip U1 and the bus 1, one end of the resistor R5 is connected with the end B of the second RS485 chip U2 and the bus 2, and the other end of the resistor R5 is connected with the end A of the first RS485 chip U2 and the bus 2.

The half-duplex relay circuit further comprises a resistor R1, a resistor R3, a resistor R4 and a resistor R6, one end of the resistor R1 is grounded, the other end of the resistor R1 is connected with the resistor R2, one end of the resistor R3 is connected with an external power supply, the other end of the resistor R3 is connected with the resistor R2, one end of the resistor R4 is grounded, the other end of the resistor R4 is connected with the resistor R5, one end of the resistor R6 is connected with the external power supply, and the other end of the resistor R6 is connected with the resistor R5.

The invention has the beneficial effects that: a half-duplex relay circuit comprises a first RS485 chip U1, a second RS485 chip U2, a first inverter U3, a second inverter U4, a pull-up resistor R7, a pull-up resistor R9, a capacitor C1, a capacitor C2, a resistor R9 and a resistor R10, wherein the first RS485 chip U1 obtains a data packet from a bus 1 and outputs a low-level effective pulse signal to the second inverter U4, and outputs a high level after reversing so that the second RS485 chip U2 is in a sending state and completes signal relay from the bus 1 to the bus 2, relay from the bus 2 to the bus 1 is opposite to relay from the bus 1 to the bus 2, the defect that an existing signal relay can only transmit signals in a single direction can be well overcome, and the installation arrangement of the relay becomes simple; and because the non-isolated type is adopted, the cost is low, and the circuit is simple and reliable.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a circuit diagram of a half-duplex relay circuit.

Detailed Description

Reference will now be made in detail to the present preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout.

In the description of the present invention, a plurality of means is two or more, and greater than, less than, more than, etc. are understood as excluding the present number, and greater than, less than, etc. are understood as including the present number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.

In the description of the present invention, it should be understood that the orientation or positional relationship referred to in the description of the orientation, such as the upper, lower, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.

In the present invention, unless explicitly defined otherwise, the terms "disposed," "mounted," "connected," and the like are to be understood in a broad sense, and for example, may be directly connected or indirectly connected through an intermediate; can be fixedly connected, can also be detachably connected and can also be integrally formed; may be a mechanical connection; either as communication within the two elements or as an interactive relationship of the two elements. The specific meaning of the above-mentioned words in the present invention can be reasonably determined by those skilled in the art in combination with the detailed contents of the technical solutions.

Referring to fig. 1, a half-duplex relay circuit includes: the bus structure comprises a first RS485 chip U1, a second RS485 chip U2, a first inverter U3, a second inverter U4, a pull-up resistor R7 and a pull-up resistor R9, wherein the A end and the B end of the first RS485 chip U1 are respectively connected with a bus 1, the RO end of the first RS485 chip U1 is respectively connected with the input end of the second inverter U4 and the DI end of the second RS485 chip U2, and the output end of the second inverter U4 is respectively connected with the DI end of the second RS485 chip U1The end is connected with the DE end, the DI end of the first RS485 chip U1 is respectively connected with the RO end of the second RS485 chip U2 and the input end of the first phase inverter U3, and the output end of the first phase inverter U3 is respectively connected with the output end of the first RS485 chip U1The end of the second RS485 chip U2 is connected with the DE end, the A end and the B end of the second RS485 chip U2 are respectively connected with the bus 2, one end of a pull-up resistor R7 is connected with the input end of a first inverter U3, the other end of the pull-up resistor R7 is respectively connected with an external power supply and the power supply end of the first inverter U3, one end of a pull-up resistor R9 is connected with the input end of a second inverter U4, and the other end of the pull-up resistor R9 is connected with the power supply end of the second inverter U4; the LED driving circuit further comprises a resistor R10 and a capacitor C2, one end of the resistor R10 is connected with the RO end of the first RS485 chip U1 and the DI end of the second RS485 chip U2 respectively, the other end of the resistor R10 is connected with the pull-up resistor R9, one end of the capacitor C2 and the input end of the second inverter U4 respectively, and the other end of the capacitor C2 is connected with the ground end; the LED driving circuit comprises a resistor R8 and a capacitor C1, wherein one end of the resistor R8 is connected with the DI end of the first RS485 chip U1 and the RO end of the second RS485 chip U2 respectively, the other end of the resistor R8 is connected with one end of a pull-up resistor R7, one end of a capacitor C1 and the input end of a first inverter U3 respectively, and the other end of the capacitor C1 is connected with the ground end.

In the invention, when the bus 1 and the bus 2 are idle, the input end of the first inverter U3 and the input end of the second inverter U4 are respectively pulled up to a high level by the pull-up resistor R7 and the pull-up resistor R9, so that the output end of the first inverter U3 and the output end of the second inverter U4 output a low level in an inverted mode, and the first RS485 chip U1 and the second RS485 chip U2 are both in a receiving mode; when a data packet is sent from the bus 1, the first RS485 chip U1 receives the data packet and outputs the data packet from the RO terminal, and is input to the input end of a second inverter U4 after passing through a low-pass filter circuit consisting of a resistor R10 and a capacitor C2, since the data packet output by the RO terminal of the first RS485 chip U1 is a pulse signal with low level and high effect, the input of the second inverter U4 is now a low signal for the entire packet time length, therefore, the output terminal of the second inverter U4 inverts and outputs high, so as to make the second RS485 chip U2 in a transmitting mode, meanwhile, the data packet output from the RO terminal of the first RS485 chip U1 is input to the DI terminal of the second RS485 chip U2, then the second RS485 chip U2 sends out a data packet to the bus 2, when the data packet is sent, the bus 1 and the bus 2 are restored to an idle state, the first RS485 chip U1 and the second RS485 chip U2 are both in a receiving mode, and then the signal relay from the bus 1 to the bus 2 is completed;

when a data packet is sent from the bus 2, the second RS485 chip U2 receives the data packet and outputs the data packet from the RO terminal, and is input to the input end of the first inverter U3 after passing through a low-pass filter circuit consisting of a resistor R8 and a capacitor C1, since the data packet output by the RO terminal of the second RS485 chip U2 is a pulse signal with low level and high effect, the input of the first inverter U3 is now low for the entire packet time, therefore, the output terminal of the first inverter U3 inverts and outputs high, causing the first RS485 chip U1 to be in a transmit mode, meanwhile, the data packet output from the RO terminal of the second RS485 chip U2 is input to the DI terminal of the first RS485 chip U1, and then the first RS485 chip U1 sends out a data packet to the bus 1, when the data packet sending is finished, the bus 1 and the bus 2 are restored to the idle state, the first RS485 chip U1 and the second RS485 chip U2 are both in a receiving mode, and then the signal relay from the bus 2 to the bus 1 is finished.

The half-duplex relay circuit further comprises a diode D1 and a diode D2, wherein the anode of the diode D1 is connected with a capacitor C1, the cathode of the diode D1 is respectively connected with the DI end of the first RS485 chip U1 and the RO end of the second RS485 chip U2, the anode of the diode D2 is connected with the capacitor C2, and the cathode of the diode D2 is respectively connected with the RO end of the first RS485 chip U1 and the DI end of the second RS485 chip U2; the diode D1 and the diode D2 are used for accelerating discharge of the capacitor C1 and the capacitor C2, and can accelerate inversion of the first inverter U3 and the second inverter U4.

The half-duplex relay circuit further comprises a resistor R2 and a resistor R5, one end of the resistor R2 is connected with the B end of the first RS485 chip U1 and the bus 1 respectively, the other end of the resistor R2 is connected with the A end of the first RS485 chip U1 and the bus 1 respectively, one end of the resistor R5 is connected with the B end of the second RS485 chip U2 and the bus 2 respectively, and the other end of the resistor R5 is connected with the A end of the first RS485 chip U2 and the bus 2 respectively; the resistor R2 and the resistor R5 can avoid the problem of signal reflection.

The half-duplex relay circuit further comprises a resistor R1, a resistor R3, a resistor R4 and a resistor R6, wherein one end of the resistor R1 is grounded, the other end of the resistor R1 is connected with the resistor R2, one end of the resistor R3 is connected with an external power supply, the other end of the resistor R3 is connected with the resistor R2, one end of the resistor R4 is grounded, the other end of the resistor R4 is connected with the resistor R5, one end of the resistor R6 is connected with the external power supply, and the other end of the resistor R6 is connected with the resistor R5; the resistor R1, the resistor R3, the resistor R4 and the resistor R6 are bias resistors, and therefore the anti-interference capability of the bus is improved.

It is to be understood that the present invention is not limited to the above-described embodiments, and that equivalent modifications and substitutions may be made by those skilled in the art without departing from the spirit of the present invention, and that such equivalent modifications and substitutions are to be included within the scope of the appended claims.