阅读说明：本技术 一种离子同步加速器中快响应线性电源控制系统及方法 (System and method for controlling fast response linear power supply in ion synchrotron ) 是由 赵江 周忠祖 高大庆 张华剑 李继强 闫怀海 于 2020-06-04 设计创作，主要内容包括：本发明涉及一种离子同步加速器中快响应线性电源控制系统及方法,其特征在于,该快响应线性电源控制系统包括FPGA控制器、工控机、模拟调节器和状态板；FPGA控制器用于接收触发事例并转换为触发信号发送至工控机,以及实时采集快响应线性电源的电流波形信号；工控机用于产生给定波形信号以及实时采集快响应线性电源的电流反馈信号；模拟调节器用于产生功率管控制信号并发送至快响应线性电源,控制快响应线性电源的功率器件；状态板用于确定快响应线性电源的运行状态,对快响应线性电源进行分闸保护,以及根据所述工控机发送的命令控制该快响应线性电源控制系统的开关机或复位,本发明可以广泛应用于离子同步加速器领域中。(The invention relates to a control system and a method for a fast response linear power supply in an ion synchrotron, which is characterized in that the control system for the fast response linear power supply comprises an FPGA controller, an industrial personal computer, an analog regulator and a state board; the FPGA controller is used for receiving the trigger case, converting the trigger case into a trigger signal and sending the trigger signal to the industrial personal computer, and acquiring a current waveform signal of the fast response linear power supply in real time; the industrial personal computer is used for generating a given waveform signal and acquiring a current feedback signal of the fast response linear power supply in real time; the analog regulator is used for generating a power tube control signal and sending the power tube control signal to the fast response linear power supply to control a power device of the fast response linear power supply; the state board is used for determining the running state of the fast response linear power supply, performing switching-off protection on the fast response linear power supply, and controlling the on-off or resetting of the fast response linear power supply control system according to the command sent by the industrial personal computer.)

1. A fast response linear power supply control system in an ion synchrotron is characterized by comprising an FPGA controller, an industrial personal computer, an analog regulator and a state board;

the FPGA controller is used for receiving a trigger case, converting the trigger case into a trigger signal and sending the trigger signal to the industrial personal computer, acquiring a current waveform signal of the fast response linear power supply in real time, and sending an abnormal signal to the state board when the current waveform signal is abnormal;

the industrial personal computer is used for carrying out safety check on the given waveform data sent by the upper computer to obtain the given waveform data after the safety check, and generating a given waveform signal according to the trigger signal and the given waveform data after the safety check; collecting a current feedback signal of the fast response linear power supply in real time;

the analog regulator is used for generating a power tube control signal according to the current feedback signal and the given waveform signal, sending the power tube control signal to the fast response linear power supply and controlling a power device of the fast response linear power supply;

the state board is used for determining the running state of the fast response linear power supply according to a state signal fed back by a circuit sensor in the fast response linear power supply, performing switching-off protection on the fast response linear power supply according to an abnormal signal, and controlling the on/off or resetting of the fast response linear power supply control system according to a command sent by the industrial personal computer.

2. The system of claim 1, wherein the industrial personal computer is internally provided with a data checking unit, a data transmission unit, a waveform generator and a data acquisition card;

the data checking unit is used for carrying out safety checking on the given waveform data sent by the upper computer to generate the given waveform data after the safety checking;

the data transmission unit is used for sending the given waveform data after the safety verification to the waveform generator;

the waveform generator is used for receiving the trigger signal and generating a given waveform signal according to the given waveform data after the safety verification;

the data acquisition card is used for acquiring a current feedback signal of the fast response linear power supply in real time and sending the current feedback signal to the analog regulator.

3. The system as claimed in claim 2, wherein the waveform generator comprises a waveform generating module, a clock distribution circuit, a digital-to-analog converter and a FIFO memory;

the waveform generation module is used for receiving a rising edge trigger signal sent by the FPGA controller and generating a given waveform signal according to given waveform data after safety verification;

the clock distribution circuit is used for generating a required clock signal;

the digital-to-analog converter is used for converting a given waveform signal of digital quantity into a given waveform signal of analog quantity and outputting the given waveform signal to the analog regulator according to a required clock signal;

the FIFO memory is used for buffering the given waveform data after the safety check.

4. The system as claimed in claim 3, wherein the FPGA controller comprises a backplane, an FPGA core control board, an SDRAM module, a FLASH controller and an EPCS chip, wherein the system on chip of the FPGA core control board comprises a CPU, a trigger switching circuit, a current pulse width protection module, an EPCS controller, a UART controller, a timer controller and an Ethernet controller;

the bottom plate is provided with an AD board interface used for connecting the digital-to-analog converter, a 96-pin bus interface used for connecting the state board and the FPGA core control board;

the CPU is used for acquiring a current waveform signal of the fast response linear power supply in real time, receiving a trigger case, converting the trigger case into a trigger signal, sending the running state and the trigger signal of the fast response linear power supply to the industrial personal computer, and sending a startup and shutdown and reset command to the state board;

the trigger conversion circuit is used for converting the trigger signal into a rising edge trigger signal;

the current pulse width protection module is used for calculating the time that a current waveform signal acquired in real time exceeds a preset threshold value, judging that the current waveform signal is abnormal when the time exceeds a preset time range, and sending an abnormal signal to the state board;

the SDRAM module is used for storing various operating data of the CPU;

the EPCS chip is used for storing a configuration file of the FPGA core control panel circuit;

the EPCS controller is used for controlling the work of the EPCS chip;

the FLASH controller is used for storing the used application program codes;

the UART controller is used for realizing data communication between the state board and the FPGA core control board;

the timer controller is used for carrying out timing control on an application program used by the CPU;

the Ethernet controller is used for providing an Ethernet interface on the FPGA core control board.

5. The system as claimed in claim 3, wherein the current readback of the clock distribution circuit has three channels, all of which are the same output current signals, wherein one channel is connected to the data acquisition card and is used for on-line monitoring of current waveform; one path is connected with the analog regulator and used for current feedback regulation; and the other path of the current is connected with the FPGA controller and is used for performing abnormal interlocking protection on the current.

6. The system as claimed in claim 4, wherein the FPGA core control board is an FPGA chip of Intel's CycloneiV system.

7. A control method for a fast response linear power supply in an ion synchrotron is characterized by comprising the following steps:

1) the FPGA controller receives the trigger case, converts the trigger case into a trigger signal and sends the trigger signal to the industrial personal computer, the industrial personal computer carries out safety verification on given waveform data sent by the upper computer to obtain the given waveform data after the safety verification, and a given waveform signal is generated according to the trigger signal and the given waveform data after the safety verification;

2) the FPGA controller collects current waveform signals of the fast response linear power supply in real time, when the current waveform signals are abnormal, abnormal signals are sent to a state board, and the state board carries out brake-separating protection on the fast response linear power supply;

3) the industrial personal computer collects a current feedback signal of the fast response linear power supply in real time and sends the current feedback signal and a given waveform signal after safety verification to the analog regulator;

4) the analog regulator generates a power tube control signal according to the current feedback signal and the given waveform signal, sends the power tube control signal to the fast response linear power supply, and controls a power device of the fast response linear power supply in a linear mode;

5) the state board determines the running state of the fast response linear power supply according to a state signal fed back by a sensor circuit in the ion synchrotron;

6) meanwhile, the state board controls the on/off or reset of the fast response linear power supply control system according to the command sent by the industrial personal computer.

8. The method for controlling the fast response linear power supply in the ion synchrotron according to claim 7, wherein the specific process of the step 1) is as follows:

1.1) the FPGA controller receives the trigger case, converts the trigger case into a rising edge trigger signal and sends the rising edge trigger signal to the waveform generation module;

1.2) the data checking unit receives given waveform data sent by the upper computer and carries out safety checking, abnormal given waveform data are eliminated, and given waveform data after safety checking are generated;

1.3) the data transmission unit sends the given waveform data after the safety verification to the waveform generation module, and the waveform generation module receives the rising edge trigger signal and generates a given waveform signal according to the given waveform data after the safety verification;

1.4) the clock distribution circuit generates the required clock signal;

1.5) the digital-to-analog converter converts the given waveform signal of the digital quantity into the given waveform signal of the analog quantity and outputs the given waveform signal to the analog regulator according to a required clock signal.

9. The method for controlling the fast response linear power supply in the ion synchrotron according to claim 8, wherein the specific process of the step 1.2) is as follows:

1.2.1) the data checking unit receives given waveform data sent by the upper computer, checks the maximum value of the given waveform data in a point-by-point checking mode, and enters the step 1.2.2) if the maximum value of the given waveform data is within a preset range; otherwise, entering step 1.2.4);

1.2.2) the data checking unit checks the change rate between adjacent current values in the given waveform data in a point-by-point checking mode, and if the change rate is within a preset range, the step 1.2.3) is carried out; otherwise, go to step 12.4);

1.2.3) sending the given waveform data to a FIFO memory for buffering;

1.2.4) rejecting the given waveform data;

1.2.5) obtaining the given waveform data after safety verification.

10. The method for controlling a fast response linear power supply in an ion synchrotron according to claim 7, wherein the specific process of the step 2) is as follows:

2.1) the CPU collects the current waveform signal of the fast response linear power supply in real time;

2.2) the current pulse width protection module calculates the time when the current waveform signal acquired in real time exceeds a preset threshold value by adopting a hardware multiplication mode, judges that the current waveform signal is abnormal when the time exceeds a preset time range, and sends an abnormal signal to a state board, and the state board controls the fast-response linear power supply to be switched off.

Technical Field

The invention relates to a control system and a control method for a fast response linear power supply in an ion synchrotron, belonging to the field of ion synchrotrons.

Background

The ion synchrotron is a circular accelerating device which accelerates ions by a high-frequency electric field on a certain circular orbit, and the strength of a magnetic field in the ion synchrotron is increased along with the increase of the energy of the accelerated ions, so that the ion cyclotron frequency is kept synchronous with the electric field of the high-frequency accelerator. The magnetic field generated by the ion synchrotron is required to be constant or to change according to a required rule. The excitation power supply generates a magnetic field by supplying current to the magnet, and is generally divided into a current stabilization power supply and a pulse power supply, wherein the current stabilization power supply generates a constant magnetic field, and the pulse power supply can generate a magnetic field which changes according to a rule. Generally, a heavy ion synchrotron is generally composed of an ECR (electron cyclotron resonance) ion source, a low energy transport line, a synchrotron, a high energy beam line, and a terminal, and as a magnet power supply for an accelerator, it has high requirements in terms of current stability, current ripple, and current tracking accuracy. An injection BUMP (convex rail) power supply, a fast four-pole iron power supply and a switch iron power supply in the ion synchrotron are key fast response power supplies in the synchrotron, and the current waveform speed is high, so that the fast response power supplies are difficult to realize in a digital mode. The injection of the BUMP power supply is generally realized in a linear mode due to the fast response of the BUMP power supply, and the injected BUMP power supply is generally in charge of single or multiple injections of beam current of the ion synchrotron and has important influence on the acceleration efficiency of the ion synchrotron; the fast four-pole iron power supply mainly has the main functions of tracking and inhibiting ripples of beam current of the ion synchrotron, has high response speed, generally outputs sine wave current with the frequency of current waveform being 1K, and the main circuit of the power supply is generally realized in a linear mode; in addition, for a terminal with a special application, there are some cases where it is also necessary to switch the beam current quickly, for example: a breath-gated switch iron power supply in a heavy ion cancer treatment device generally has a step response time of less than 100us of power supply current, and the power supply also generally adopts an analog linear scheme as a main circuit. In summary, there is a kind of key fast response power supply in the ion synchrotron, and its main circuit is a linear circuit, which is a key device, and has important influence on the acceleration efficiency and beam quality of the ion synchrotron. At present, in the field of accelerator power supplies, most of the sub-synchrotrons adopt digital power supplies, and control systems of the power supplies adopt digital control interfaces. However, for the fast response linear power supply, a control method is needed to encapsulate the interface of the power supply and present a uniform digital interface to the outside to meet the requirement of the accelerator power supply control system.

Because the current response speed of the fast-response linear power supply is fast, the waveform period of the output current of the power supply is short, the direct current output time of the power supplies is usually not too long, otherwise, the power tube is damaged, and therefore, the fast waveform needs to be collected and protected in real time. Because the current waveform changes greatly in practical application, if the protection is carried out in an analog protection mode, the protection is not flexible, and meanwhile, the precision of a current waveform protection circuit can be influenced by the problems of temperature drift, aging and the like of electronic components, a digital protection mode is adopted, the protection precision is high, and the reliability is high, so that a protection mechanism is needed in a control system of the power supply to monitor the current waveform so as to improve the reliability of the power supply operation.

One of the main problems with fast response linear power control is how to convert the digitized power control interface and protocol to an analog control interface. The pulse power supply of the ion synchrotron is mostly a digital power supply, a self-defined transmission control protocol based on TCP/IP is adopted, if a set of interface and conversion mechanism is needed for controlling a fast-response linear power supply by using the protocol, a digital control quantity is converted into an analog control quantity, and one key link of the protocol is how to convert waveform data into a high-precision analog control signal, which is completed by a high-speed and high-precision DAC (digital-to-analog converter). The design of a high-speed high-precision DA board which can reliably run and can convert special waveform data into the data has certain difficulty, and a series of development and design such as interface processing, a PCB (printed circuit board), an interface configuration program, a data storage program, hardware driving and the like are required.

In addition, because the fast response linear power supply works in a linear region and has high response speed, any wrong waveform can cause the damage of a power supply power device, and the frequency of pulse waveform data transmission is very high in the process of debugging or replacing energy of the ion synchrotron, so that the mistake is difficult to avoid. Therefore, the waveform transmitted to the controller needs to be pre-determined, and further, when a waveform error is found in advance, the output of the analog control signal can be prohibited, so that the purpose of protecting the power device is achieved. However, none of the existing control methods can achieve the above-described functions.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a control system and method for a fast response linear power supply in an ion synchrotron, which can convert waveform data into a high-precision analog control signal and protect a power device in the fast response linear power supply.

In order to achieve the purpose, the invention adopts the following technical scheme: a fast response linear power supply control system in an ion synchrotron comprises an FPGA controller, an industrial personal computer, an analog regulator and a state board; the FPGA controller is used for receiving a trigger case, converting the trigger case into a trigger signal and sending the trigger signal to the industrial personal computer, acquiring a current waveform signal of the fast response linear power supply in real time, and sending an abnormal signal to the state board when the current waveform signal is abnormal; the industrial personal computer is used for carrying out safety check on the given waveform data sent by the upper computer to obtain the given waveform data after the safety check, and generating a given waveform signal according to the trigger signal and the given waveform data after the safety check; collecting a current feedback signal of the fast response linear power supply in real time; the analog regulator is used for generating a power tube control signal according to the current feedback signal and the given waveform signal, sending the power tube control signal to the fast response linear power supply and controlling a power device of the fast response linear power supply; the state board is used for determining the running state of the fast response linear power supply according to a state signal fed back by a circuit sensor in the fast response linear power supply, performing switching-off protection on the fast response linear power supply according to an abnormal signal, and controlling the on/off or resetting of the fast response linear power supply control system according to a command sent by the industrial personal computer.

Furthermore, a data calibration unit, a data transmission unit, a waveform generator and a data acquisition card are arranged in the industrial personal computer; the data checking unit is used for carrying out safety checking on the given waveform data sent by the upper computer to generate the given waveform data after the safety checking; the data transmission unit is used for sending the given waveform data after the safety verification to the waveform generator; the waveform generator is used for receiving the trigger signal and generating a given waveform signal according to the given waveform data after the safety verification; the data acquisition card is used for acquiring a current feedback signal of the fast response linear power supply in real time and sending the current feedback signal to the analog regulator.

Further, the waveform generator comprises a waveform generation module, a clock distribution circuit, a digital-to-analog converter and a FIFO memory; the waveform generation module is used for receiving a rising edge trigger signal sent by the FPGA controller and generating a given waveform signal according to given waveform data after safety verification; the clock distribution circuit is used for generating a required clock signal; the digital-to-analog converter is used for converting a given waveform signal of digital quantity into a given waveform signal of analog quantity and outputting the given waveform signal to the analog regulator according to a required clock signal; the FIFO memory is used for buffering the given waveform data after the safety check.

Further, the FPGA controller comprises a bottom plate, an FPGA core control board, an SDRAM module, a FLASH controller and an EPCS chip, wherein the system on chip of the FPGA core control board comprises a CPU, a trigger conversion circuit, a current pulse width protection module, an EPCS controller, a UART controller, a timer controller and an Ethernet controller; the bottom plate is provided with an AD board interface used for connecting the digital-to-analog converter, a 96-pin bus interface used for connecting the state board and the FPGA core control board; the CPU is used for acquiring a current waveform signal of the fast response linear power supply in real time, receiving a trigger case, converting the trigger case into a trigger signal, sending the running state and the trigger signal of the fast response linear power supply to the industrial personal computer, and sending a startup and shutdown and reset command to the state board; the trigger conversion circuit is used for converting the trigger signal into a rising edge trigger signal; the current pulse width protection module is used for calculating the time that a current waveform signal acquired in real time exceeds a preset threshold value, judging that the current waveform signal is abnormal when the time exceeds a preset time range, and sending an abnormal signal to the state board; the SDRAM module is used for storing various operating data of the CPU; the EPCS chip is used for storing a configuration file of the FPGA core control panel circuit; the EPCS controller is used for controlling the work of the EPCS chip; the FLASH controller is used for storing the used application program codes; the UART controller is used for realizing data communication between the state board and the FPGA core control board; the timer controller is used for carrying out timing control on an application program used by the CPU; the Ethernet controller is used for providing an Ethernet interface on the FPGA core control board.

Furthermore, the current readback of the clock distribution circuit has three channels, all of which are the same output current signals, wherein one channel is connected with the data acquisition card and is used for on-line monitoring of current waveforms; one path is connected with the analog regulator and used for current feedback regulation; and the other path of the current is connected with the FPGA controller and is used for performing abnormal interlocking protection on the current.

Furthermore, the FPGA core control board adopts an FPGA chip of a cyclonexiV system of Intel corporation.

A control method for a fast response linear power supply in an ion synchrotron comprises the following steps: 1) the FPGA controller receives the trigger case, converts the trigger case into a trigger signal and sends the trigger signal to the industrial personal computer, the industrial personal computer carries out safety verification on given waveform data sent by the upper computer to obtain the given waveform data after the safety verification, and a given waveform signal is generated according to the trigger signal and the given waveform data after the safety verification; 2) the FPGA controller collects current waveform signals of the fast response linear power supply in real time, when the current waveform signals are abnormal, abnormal signals are sent to a state board, and the state board carries out brake-separating protection on the fast response linear power supply; 3) the industrial personal computer collects a current feedback signal of the fast response linear power supply in real time and sends the current feedback signal and a given waveform signal after safety verification to the analog regulator; 4) the analog regulator generates a power tube control signal according to the current feedback signal and the given waveform signal, sends the power tube control signal to the fast response linear power supply, and controls a power device of the fast response linear power supply in a linear mode; 5) the state board determines the running state of the fast response linear power supply according to a state signal fed back by a sensor circuit in the ion synchrotron; 6) meanwhile, the state board controls the on/off or reset of the fast response linear power supply control system according to the command sent by the industrial personal computer.

Further, the specific process of the step 1) is as follows: 1.1) the FPGA controller receives the trigger case, converts the trigger case into a rising edge trigger signal and sends the rising edge trigger signal to the waveform generation module; 1.2) the data checking unit receives given waveform data sent by the upper computer and carries out safety checking, abnormal given waveform data are eliminated, and given waveform data after safety checking are generated; 1.3) the data transmission unit sends the given waveform data after the safety verification to the waveform generation module, and the waveform generation module receives the rising edge trigger signal and generates a given waveform signal according to the given waveform data after the safety verification; 1.4) the clock distribution circuit generates the required clock signal; 1.5) the digital-to-analog converter converts the given waveform signal of the digital quantity into the given waveform signal of the analog quantity and outputs the given waveform signal to the analog regulator according to a required clock signal.

Further, the specific process of step 1.2) is as follows: 1.2.1) the data checking unit receives given waveform data sent by the upper computer, checks the maximum value of the given waveform data in a point-by-point checking mode, and enters the step 1.2.2) if the maximum value of the given waveform data is within a preset range; otherwise, entering step 1.2.4); 1.2.2) the data checking unit checks the change rate between adjacent current values in the given waveform data in a point-by-point checking mode, and if the change rate is within a preset range, the step 1.2.3) is carried out; otherwise, go to step 12.4); 1.2.3) sending the given waveform data to a FIFO memory for buffering; 1.2.4) rejecting the given waveform data; 1.2.5) obtaining the given waveform data after safety verification.

Further, the specific process of step 2) is as follows: 2.1) the CPU collects the current waveform signal of the fast response linear power supply in real time; 2.2) the current pulse width protection module calculates the time when the current waveform signal acquired in real time exceeds a preset threshold value by adopting a hardware multiplication mode, judges that the current waveform signal is abnormal when the time exceeds a preset time range, and sends an abnormal signal to a state board, and the state board controls the fast-response linear power supply to be switched off.

Due to the adoption of the technical scheme, the invention has the following advantages: the invention can effectively solve the digital control of the fast response linear power supply, realize the unification of the power supply remote control interface in the ion synchrotron, provide a flexible and unified digital control mode and interface for the fast response linear power supply, and can be widely applied to accelerator application devices such as heavy ion medical devices, space irradiation laboratories and the like.

Drawings

FIG. 1 is a schematic diagram of the system of the present invention;

FIG. 2 is a schematic diagram of the construction of a machine tool in the system of the present invention;

FIG. 3 is a schematic diagram of the hardware structure of an FPGA (field programmable gate array) controller in the system of the present invention;

FIG. 4 is a schematic diagram of a system-on-chip with an FPGA core control board in the system of the present invention;

FIG. 5 is a flow chart of waveform verification in the method of the present invention.

Detailed Description

The present invention is described in detail below with reference to the attached drawings. It is to be understood, however, that the drawings are provided solely for the purposes of promoting an understanding of the invention and that they are not to be construed as limiting the invention.

Since the system and the method for controlling the fast response linear power supply in the ion synchrotron provided by the invention relate to the relevant contents of the fast response linear power supply, the relevant contents are described below, so that the contents of the invention are more clear to those skilled in the art.

The main circuit of the fast response power supply is generally linear, similar to a huge power amplifier, and has large current and short waveform period, generally about 1 ms. The waveforms of these power supplies generally require fast DACs to generate analog control signals, while fast protection of the various elements of the circuit is performed to ensure safe and reliable operation of the power supplies. The accelerator control system typically employs a unified digital control system to control the power supply, and the power supply waveform data is transmitted to the power supply according to a custom protocol.

Based on the above description, as shown in fig. 1, the fast response linear power control system in the ion synchrotron provided by the invention includes an FPGA controller 1, an industrial personal computer 2, an analog regulator 3, and a status board 4.

The FPGA controller 1 is used for receiving the trigger case, converting the trigger case into a trigger signal and sending the trigger signal to the industrial personal computer 2 so as to control the industrial personal computer 2 to output a waveform; and acquiring a current waveform signal of a fast response linear power supply in the ion synchrotron in real time, and sending an abnormal signal to the state board 4 when the current waveform signal is abnormal.

The industrial personal computer 2 is used for carrying out safety check on the given waveform data sent by the upper computer to obtain the given waveform data after the safety check, and generating a given waveform signal according to the trigger signal and the given waveform data after the safety check; collecting current feedback signals of the fast response linear power supply in real time, and sending the current feedback signals and given waveform signals to the analog regulator 3 to drive the analog regulator 3, wherein the given waveform signals are generated by a group of ordered decimal current data through a high-speed DAC (digital-to-analog converter), current readback has three channels which are the same output current signals, and one channel is connected with a data acquisition card 24 and is used for on-line monitoring of current waveforms; one path is connected with the analog regulator 3 and used for current feedback regulation; and the other path is connected with the FPGA controller 1 and is used for performing abnormal interlocking protection on the current.

The analog regulator 3 is used for generating a power tube control signal according to the current feedback signal and the given waveform signal, sending the power tube control signal to the fast response linear power supply, and controlling a power device of the fast response linear power supply in a linear mode, wherein the power tube control signal is an output driving signal.

The state board 4 is used for judging whether the fast response linear power supply has faults caused by circuit hardware, such as overcurrent, overvoltage, overtemperature and the like, according to state signals fed back by a circuit sensor in the fast response linear power supply, and determining the running state of the fast response linear power supply; according to the abnormal signal, switching-off protection is carried out on the fast response linear power supply; and controlling the on/off or resetting of the fast response linear power supply control system according to a command sent by the industrial personal computer 2.

In a preferred embodiment, as shown in fig. 2, a data verification unit 21, a data transmission unit 22, a waveform generator 23 and a data acquisition card 24 are disposed in the industrial personal computer 2, wherein the waveform generator 23 is a PCI bus-based high-speed circuit board, and the waveform generator 23 includes a waveform generation module, a clock distribution circuit, a digital-to-analog converter and a FIFO (first-in-first-out) memory.

The data checking unit 21 is configured to perform security checking on the given waveform data sent by the upper computer, remove abnormal given waveform data, and generate the given waveform data after the security checking.

The data transmission unit 22 is configured to send the given waveform data after the security verification to the waveform generation module, and meanwhile, implement data interaction between the ethernet and the data acquisition card 24.

The waveform generation module is used for receiving a rising edge trigger signal sent by the FPGA controller 1 and generating a given waveform signal according to given waveform data after safety verification, wherein the minimum point interval of waveform generation is 20 ns.

The clock distribution circuit is used for generating a required clock signal so as to generate a time interval according to the clock signal and further control the data output frequency of the digital-to-analog converter, and the current readback circuit has three channels which are all the same output current signals, wherein one channel is connected with the data acquisition card 24 and is used for on-line monitoring of current waveforms; one path is connected with the analog regulator 3 and used for current feedback regulation; and the other path is connected with the FPGA controller 1 and is used for performing abnormal interlocking protection on the current.

The digital-to-analog converter is configured to convert the given waveform signal of the digital quantity into the given waveform signal of the analog quantity, and output the given waveform signal to the analog regulator 3 according to a desired clock signal.

The FIFO memory is used for buffering the given waveform data after the safety check, and the size of the FIFO memory is 1 MDB.

The data acquisition card 24 is used for acquiring the current feedback signal of the fast response linear power supply in real time and sending the current feedback signal to the analog regulator 3 through the data transmission unit 22 via the ethernet interface.

In a preferred embodiment, as shown in fig. 3 and 4, the FPGA controller 1 includes a backplane, an FPGA core control board 11, an SDRAM (synchronous dynamic random access memory) module 12, a FLASH (FLASH memory) controller 13, and an EPCS (serial storage) chip 14, wherein the system on chip of the FPGA core control board 11 includes a CPU111, a trigger conversion circuit 112, a current pulse width protection module 113, an EPCS controller 114, a UART (universal asynchronous receiver transmitter receiver transmitter) controller 115, a timer controller 116, and an ethernet controller 117.

The bottom plate is provided with an AD board interface 15, a 96-pin bus interface 16 and an FPGA core control panel interface, the AD board interface 15 is used for connecting a digital-to-analog converter, the 96-pin bus interface 16 is used for connecting the status board 4, and the FPGA core control panel interface is used for connecting the FPGA core control panel 11.

The CPU111 is used for collecting current waveform signals of the fast response linear power supply in real time; receiving a trigger case and converting the trigger case into a trigger signal; the running state and the trigger signal of the fast response linear power supply are sent to the industrial personal computer 2 through the Ethernet interface; and sending the on-off and reset commands to the status board 4, wherein the triggering modes of the triggering signals comprise an external digital triggering mode and a bus software triggering mode.

The trigger converting circuit 112 is used to convert the trigger signal into a rising edge trigger signal.

The current pulse width protection module 113 is configured to calculate, in a hardware multiplication manner, a time when a current waveform signal acquired in real time exceeds a preset threshold, determine that the current waveform signal is abnormal when the time exceeds a preset time range, and send an abnormal signal to the state board 4, where the state board 4 controls the fast-response linear power supply to be switched off within a time less than 100 us.

The SDRAM module 12 is used for storing various operation data of the CPU 111.

The FLASH controller 13 is used to store application program codes used by the CPU111, and to store data that needs to be permanently saved, such as IP addresses and critical system parameters.

The EPCS chip 14 is configured to store a configuration file of the circuit of the FPGA core control board 11, where the configuration file is written by a hardware description language, compiled and stored in the EPCS chip, and when the FPGA core control board 11 is powered on, the circuit structure is first read into the FPGA core control board 11 from the EPCS chip, so as to complete circuit configuration of the FPGA core control board 11.

The EPCS controller 114 is used to control the operation of the EPCS chip.

The UART controller 115 is used to enable data communication between the status board 4 and the FPGA core control board 11.

The timer controller 116 is used to perform timing control of an application program used by the CPU 111.

The ethernet controller 117 is used to provide an ethernet interface on the FPGA core control board 11 for data transmission, status feedback and other communications.

In a preferred embodiment, the FPGA core control board 11 may be an FPGA chip of the cycleiv family of Intel corporation.

In a preferred embodiment, the clock distribution circuit may employ a clock distribution module of type PI49 FCT.

In a preferred embodiment, the AD board interface 15 may employ a 20 pin 2.54mm pitch connector and the 96 pins may employ a standard 96 pin connector.

In a preferred embodiment, the circuit board of the FPGA core control board 11 may be a six-layer board for routing convenience and considering the high-speed electromagnetic compatibility characteristics of the circuit.

In a preferred embodiment, the DAC may be a 14bit, 50Ms/s DAC chip available from AD corporation.

Based on the control system of the fast response linear power supply in the ion synchrotron, the invention also provides a control method of the fast response linear power supply in the ion synchrotron, which comprises the following steps:

1) the FPGA controller 1 receives the trigger case, converts the trigger case into a trigger signal and sends the trigger signal to the industrial personal computer 2, the industrial personal computer 2 carries out safety check on given waveform data sent by the upper computer, eliminates abnormal given waveform data, obtains given waveform data after the safety check, and generates given waveform signals according to the trigger signal and the given waveform data after the safety check, and the method specifically comprises the following steps:

1.1) the FPGA controller 1 receives the trigger case, converts the trigger case into a rising edge trigger signal and sends the rising edge trigger signal to a waveform generation module of the industrial personal computer 2.

1.2) as shown in fig. 5, the data verification unit 21 receives given waveform data sent by the upper computer, performs security verification, eliminates abnormal given waveform data, and generates given waveform data after security verification:

1.2.1) the data checking unit 21 receives given waveform data sent by an upper computer according to a self-defined TCP/IP protocol, checks the maximum value of the given waveform data in a point-by-point checking mode, and enters the step 1.2.2 if the maximum value of the given waveform data is within a preset range); otherwise, step 1.2.4) is entered.

1.2.2) the data checking unit 21 checks the change rate between adjacent current values in the given waveform data in a point-by-point checking mode, and if the change rate is within a preset range, the step 1.1.3) is carried out; otherwise, step 1.1.4) is entered.

1.2.3) sending the given waveform data to a FIFO memory for buffering.

1.2.4) culling the given waveform data.

1.2.5) obtaining the given waveform data after safety verification.

1.3) the data transmission unit 22 sends the given waveform data after the safety verification to the waveform generation module, and the waveform generation module receives the rising edge trigger signal and generates a given waveform signal according to the given waveform data after the safety verification.

1.4) the clock distribution circuit generates the required clock signal to control the data output frequency of the digital-to-analog converter according to the time interval of clock signal generation.

1.5) the digital-to-analog converter converts the given waveform signal of the digital quantity into the given waveform signal of the analog quantity and outputs the given waveform signal to the analog regulator 3 in accordance with a desired clock signal.

2) The FPGA controller 1 collects current waveform signals of the fast response linear power supply in real time, sends abnormal signals to the state board 4 when the current waveform signals are abnormal, and the state board 4 carries out brake-separating protection on the fast response linear power supply, and specifically comprises the following steps:

2.1) the CPU111 collects the current waveform signal of the fast response linear power supply in real time.

2.2) the current pulse width protection module 113 calculates the time that the current waveform signal collected in real time exceeds the preset threshold value by adopting a hardware multiplication mode, when the time exceeds the preset time range, the current waveform signal is judged to be abnormal, an abnormal signal is sent to the state board 4, and the state board 4 controls the fast-response linear power supply to be switched off within the time less than 100 us.

3) The industrial personal computer 2 collects the current feedback signal of the fast response linear power supply in real time and sends the current feedback signal and the given waveform signal to the analog regulator 3.

4) The analog regulator 3 generates a power tube control signal according to the current feedback signal and the given waveform signal, and sends the power tube control signal to the fast response linear power supply to control a power device of the fast response linear power supply in a linear mode.

5) The state board 4 judges whether the fast response linear power supply has faults caused by circuit hardware, including overcurrent, overvoltage, overtemperature and the like, according to a state signal fed back by a circuit sensor in the fast response linear power supply, and determines the running state of the fast response linear power supply.

6) Meanwhile, the state board 4 controls the on/off or reset of the fast response linear power supply control system according to the command sent by the industrial personal computer 2.

The above embodiments are only used for illustrating the present invention, and the structure, connection mode, manufacturing process, etc. of the components may be changed, and all equivalent changes and modifications performed on the basis of the technical solution of the present invention should not be excluded from the protection scope of the present invention.