阅读说明：本技术 具有功率传输的电隔离低延迟开关驱动电路 (Electrically isolated low delay switch drive circuit with power transfer ) 是由 卡尔·里尼 约瑟夫·杜根 于 2018-10-08 设计创作，主要内容包括：本申请涉及电子器件,具体地涉及开关驱动电路,并且更具体地涉及具有从开关驱动器输入侧到开关侧的功率传输的电隔离开关电路。更具体地,本申请提供了一种开关驱动电路,该开关驱动电路通过使用单个变压器将控制信号传输至次级侧以控制该开关,并向次级侧电路供电以响应于该控制信号来驱动该开关。通过在汲取电流之前先检测控制信号,可以减少变压器中漏感的影响。(The present application relates to electronic devices, in particular to switch driver circuits, and more particularly to electrically isolated switch circuits with power transfer from the input side of the switch driver to the switch side. More particularly, the present application provides a switch driving circuit that controls a switch by transmitting a control signal to a secondary side using a single transformer, and supplies power to a secondary side circuit to drive the switch in response to the control signal. By detecting the control signal before drawing current, the effect of leakage inductance in the transformer can be reduced.)

1. An isolated drive circuit for controlling the operation of a switch by using a single transformer having a primary winding and a secondary winding, the isolated drive circuit comprising:

a control circuit for switching the switch in response to a control signal transmitted in a pulse form from the secondary winding of the transformer;

a power circuit for supplying power to the control circuit, the power circuit extracting power from each pulse of the secondary winding of the transformer;

wherein the power supply circuit is configured to delay substantial extraction of the power from each pulse while the control circuit detects the pulse.

2. The isolated drive circuit of claim 1, wherein the power supply circuit is configured to delay the extraction of the power until the amplitude of the pulse has reached a predetermined level.

3. An isolated drive circuit according to claim 1 or 2, wherein the power supply circuit comprises at least one switch positioned after the secondary winding of the transformer for switchably connecting the winding to the power supply circuit.

4. The isolated drive circuit of claim 3, wherein the at least one switch is a diode.

5. The isolated drive circuit of claim 3, wherein the at least one switch is a transistor.

6. An isolated drive circuit for controlling operation of a switch in response to a bipolar pulse signal passing from a primary winding of a transformer to a secondary winding of the transformer, the drive circuit comprising a pulse rectifier circuit for converting received negative pulses into a first control signal and for converting received positive pulses into a second control signal, wherein the first and second control signals are unipolar with respect to a common reference voltage.

7. The isolated drive circuit of claim 6, wherein the secondary winding of the transformer includes a first output node and a second output node, and the pulse rectifier circuit comprises:

a first switch for connecting the second output node to the common reference voltage, wherein the first switch is responsive to a voltage present at the first node; and

a second switch for connecting the first output node to the common reference voltage, wherein the second switch is responsive to a voltage present at the second node.

8. An isolated drive circuit for controlling the operation of a switch by using pulses transferred from a primary side winding of a transformer to a secondary side winding of the transformer, the circuit comprising a control circuit, wherein the control circuit is configured to extract a clock signal from the transferred pulses and to use the extracted clock signal for timing to enable synchronous control of the switch.

9. The isolated drive circuit of claim 8, wherein the synchronous control operates based on a transition of the pulse delivered.

10. An isolated drive circuit for controlling the operation of a switch by using pulses delivered by a transformer,

the circuit comprises a control circuit, wherein the control circuit is configured to control the switch in response to a detected transition of the delivered pulse; and

a demodulator for extracting information from the pulses for use by the control circuit.

11. The isolated drive circuit of claim 10, wherein the demodulator extracts information in the pulses that appears as amplitude.

12. An isolated drive circuit as claimed in claim 10 or 11, wherein the information extracted is used to set parameters in the control circuit.

13. An isolated drive circuit for controlling the operation of a switch by passing bipolar pulse signals from a primary winding of a transformer to a secondary winding of the transformer, each bipolar signal comprising a positive pulse and a negative pulse,

wherein the isolation drive circuit is configured to generate a bipolar pulse starting from a positive pulse or a negative pulse, an

The isolation drive circuit includes a control circuit that responds to an arrival sequence of positive and negative pulses within a single polarity pulse in controlling operation of the switch.

14. An isolated drive circuit for effecting control of a switch by using a primary side winding of a transformer to deliver a pulse to a control circuit connected to a secondary side winding of the transformer and for supplying power to a power supply located on a secondary side of the control circuit, the isolated drive circuit comprising a modulator responsive to auxiliary control information for modulating the pulse delivered with the auxiliary control information.

15. An assembly comprising the isolated drive circuit of any preceding claim and a transformer.

Technical Field

The present application relates to electronic devices, in particular to a switch driver circuit, and more particularly to an electrically isolated switch circuit with power transfer from the input side of the switch driver to the switch side.

Background

In the field of power electronics, switch drive circuits are used to turn a switch on and off.

Switches are widely used in a variety of electronic systems. The switch typically controls the current flowing from the power source to the load. For example, in contrast to controlled resistance devices used in linear amplifiers and linear regulators, switches are typically either fully on (to their lowest on-state resistance) or fully off (to their highest off-state resistance). The control electrode of the switch, commonly referred to as the gate (or base) of the switch, is driven by a switch driver circuit, or sometimes also referred to as a gate driver circuit. The switch is typically voltage controlled, turning on when the gate voltage (with respect to the other electrode of the switch, commonly referred to as its source or emitter) exceeds a certain magnitude of the manufacturer specified threshold voltage, and turning off when the gate voltage remains below this certain magnitude of threshold voltage. The present invention is primarily directed to the driving of these voltage controlled switches, such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), silicon carbide (SiC) transistors, gallium nitride (GaN) transistors or Insulated Gate Bipolar Transistors (IGBTs), but the invention can also be used to drive less common current controlled switches, such as Bipolar Junction Transistors (BJTs) or gate-implanted transistors (GITs).

The switch drive circuit receives its control instructions from a controller, such as a Pulse Width Modulation (PWM) controller, through one or more switch driver inputs. The switch driver circuit passes its drive signals directly (or indirectly through a network of active and passive components) to the various terminals (gate and source) of the switch.

In the presence of non-ideal switching parameters (e.g., input gate capacitance) and parasitic negative feedback (e.g., miller effect), key performance parameters of a switch driver circuit include its performance in driving switches with low propagation delay.

Switches are often used in electronic systems where galvanic isolation must be used to prevent undesirable direct current flow from one side of the isolation barrier to the other. Galvanic isolation is commonly used to separate circuits to protect users from direct contact with hazardous voltages. Galvanic isolation may also be used to intentionally separate circuits with dangerous or safe voltages on either side of the isolation barrier to simplify circuit design, reduce cost or improve system performance.

It is often the case that the inputs of the control circuit and the switch driver are located on one side of the electrical isolation barrier, while the switches driven by the switch driver are located on the other side of the isolation barrier. In other words, the switch drive circuit crosses the isolation barrier and therefore is typically a safety critical component. Various transmission techniques may facilitate signals to be transmitted across the electrical isolation barrier, which may include optical, magnetic, and capacitive coupling techniques. The present invention is directed to an electrically isolated switch driver circuit that uses magnetic coupling across an isolation barrier to transmit drive signal information.

It is often the case that the inputs to the controller and the switch driver are referenced to a reference node on the side of the isolation barrier. Throughout this document, the first reference node is referred to as the "main ground" and ground symbols with the appended label "P" are used in the various figuresThe description is given. The switch driver output reference node and the reference electrode of the switch are connected on the other side of the isolation barrier, referred to in this document as "floating ground", and the ground symbol with the appended label "F" is used in the various figuresThe description is given. If multiple switches are to be driven in a more complex electronic system, there may be multiple different floating ground nodes (typically one for each switch), whereas in such a system, only one main ground node is typically required.

It is well known that the isolation switch drive circuit can also be advantageously used in electronic systems where galvanic isolation is not strictly required in practice. In those cases, the galvanic isolation nature of the switch driver circuit may simplify the circuit design needed to drive a "floating switch" (i.e., a switch whose reference electrode is not connected to controller ground). The floating switch is sometimes also referred to as a "high side switch". The electrically isolated switch driver circuit of the present invention may also be used to drive floating switches, and may be referred to as a "floating switch driver circuit" or a "floating gate driver circuit" in those systems.

Fig. 1 illustrates a switch arrangement in a modern high-efficiency multi-stage switch-mode power converter (SMPC) used in an on-board battery charger of a modern Electric Vehicle (EV), which is an application example of an isolated switch driving circuit. The input section receives an ac input and provides surge and fuse protection and EMI filtering. The switch mode power converter is arranged as a totem pole Power Factor Correction (PFC) stage that converts an input Alternating Current (AC) voltage to a Direct Current (DC) voltage. This DC voltage is then provided as an input to an isolated DC-DC switching stage, which charges the battery. Isolation in the DC-DC switching stage is provided by transformer 130. This isolation may be understood as galvanic isolation.

A total of eight switches 140-. Of the eight primary side switches, four are referenced to primary side ground (141, 143, 145, 147) and the remaining four are floating switches (140, 142, 144, 146). None of the six switches on the secondary side (148-153) is referenced to the primary side ground. Thus, for a total of fourteen switches, thirteen switch drive circuits are required (152 and 153 are back-to-back protection switches, which may be driven by a single switch driver 161). All switches are controlled by a controller 160 located on the primary side and referenced to the primary side ground. As shown in the figures, the use of electrically isolated switch drive circuits 162 greatly simplifies the system design in all cases, since they are able to drive each switch regardless of which side of the isolation barrier they are located on, and regardless of whether the switches are floating with respect to ground. Only one type of switch driver circuit is required, reducing design time, cost and simplifying the system bill of materials.

Disclosure of Invention

An electrical isolation switch driver circuit is provided that transmits switch state information and powers circuitry on the floating side of the isolation barrier. It uses a single magnetic coupling device to achieve signal and power transfer. The magnetic coupling means is a transformer with a simple structure, preferably coupling the single first coil and the single second coil using a suitable magnetic material such as ferrite to achieve good coupling between the coils. The cross-sectional area and size of the transformer are very compact because only short pulses are transmitted, thereby minimizing the volt-second product across the coil. Signal and power transmission across the isolation barrier is accomplished by predetermined power transmission patterns so as not to slow down the speed of signal transmission. The speed of signal transmission is insensitive to transformer defects such as leakage inductance and variation in magnetizing inductance of the transformer.

Since the size of the transformer is very compact and the performance of the switch driver circuit is insensitive to the leakage inductance of the transformer, the transformer is very suitable for being fully integrated into one component with the primary and floating sides of the switch driver.

The floating-side drive circuit maintains control of the switch driver and can inhibit the switch driver independently of the primary side, for example, during a fault condition detected on the floating side. The floating-side fault condition may include: the floating side supply voltage drops below a safe value, or the operating temperature reaches a value outside of a safe limit, or the switch current exceeds a set current limit. The floating-side drive circuit may also optionally adjust the switch drive voltage to provide a well-controlled drive voltage that is independent of variations in circuit parameters.

The floating side driver circuit includes a clock recovery circuit and a synchronous Finite State Machine (FSM). The clock recovery circuit extracts asynchronous clock events from the incoming pulse stream and the synchronous FSM ensures that clean state transitions are performed at well-defined points in time. Compared with an asynchronous technology, the floating side control based on the synchronous FSM can bring stronger robustness and a scalable technical scheme. The primary side driver circuit can generate simple pulse patterns, or can generate more complex pulse patterns, which are then transmitted and injected into the FSM for processing by the FSM. The pulses transmitted by the primary side may optionally be width modulated or amplitude modulated in order to transmit additional information from the primary side drive circuit to the floating side drive circuit.

To start the system in order, the switch drive circuit may establish a safe floating-side operating voltage by transmitting a series of OFF signal pulses before assuming normal operation. After one or more of these OFF pulses are initiated, the operating voltage of the floating circuit reaches a suitable value, and normal switching drive operation can then commence.

By employing a refresh circuit on the primary side, the switch drive circuit described herein is also suitable for applications requiring the switch to be driven at a very low switching frequency, down to the quiescent on or off operation of the switch.

More specifically, a first embodiment of the present application provides an isolation drive circuit for controlling operation of a switch by using a single transformer having a primary winding and a secondary winding, the isolation drive circuit including a control circuit for switching the switch in response to a control signal transmitted in a pulse form from the secondary winding of the transformer, and a power supply circuit for supplying power to the control circuit. The power supply circuit extracts power from each pulse of the secondary winding of the transformer. However, the power supply circuit is configured to delay substantial extraction of power from the individual pulses to allow the control circuit to detect the pulses. In this case, the power supply circuit may be configured to delay the extraction of power until the amplitude of the pulse has reached a predetermined level. At least one switch may be provided after the secondary winding of the transformer to switchably connect the winding to the power circuit. The at least one switch may be a diode or a transistor.

A second embodiment provides an isolated drive circuit for controlling operation of a switch in response to a bipolar pulse signal transferred from a primary winding of a transformer to a secondary winding of the transformer, the drive circuit comprising a pulse rectifier circuit for converting received negative pulses to a first control signal and received positive pulses to a second control signal, wherein the first and second control signals are unipolar with respect to a common reference voltage. The secondary winding of the transformer suitably comprises a first output node and a second output node having a pulse rectifier circuit. The pulse rectifier circuit includes a first switch for connecting the second output node to a common reference voltage, wherein the first switch is responsive to a voltage present at the first node. The pulse rectifier circuit also includes a second switch for connecting the first output node to a common reference voltage, wherein the second switch is responsive to a voltage present at the second node.

A third embodiment provides an isolated drive circuit for controlling operation of a switch using pulses transferred from a primary side winding to a secondary side winding of a transformer, the circuit comprising a control circuit, wherein the control circuit is configured to extract a clock signal from the transferred pulses and use the extracted clock signal for timing to enable synchronous control of the switch. The synchronization control may operate based on the transition of the delivered pulses.

A fourth embodiment provides an isolated drive circuit for controlling the operation of a switch using pulses delivered by a transformer, the circuit comprising a control circuit configured to control the switch in response to a detected transition of a delivered pulse, the circuit further comprising a demodulator for extracting information from the pulse for use by the control circuit. The demodulator can extract the information that appears as amplitude in the pulse. The extracted information may be used to set parameters in the control circuit.

A fifth embodiment provides an isolated drive circuit for controlling operation of a switch by transferring a bipolar pulse signal from a primary winding of a transformer to a secondary winding of the transformer. It will be appreciated that each bipolar signal has a positive pulse and a negative pulse. The isolation drive circuit is configured to selectively generate a bipolar pulse starting from a positive pulse or a negative pulse. Also, the isolation drive circuit includes a control circuit responsive to the order of arrival of the positive and negative pulses within the unipolar pulse in controlling the operation of the switch.

A sixth embodiment provides an isolated drive circuit for enabling control of a switch by using a primary side winding of a transformer to deliver pulses to a control circuit connected to a secondary side winding of the transformer, and for supplying power to a power source located on a secondary side of the control circuit. The isolation drive circuit includes a modulator responsive to the auxiliary control information for modulating pulses communicated with the auxiliary control information.

Drawings

These and other embodiments will become apparent from the following description and the accompanying drawings, in which:

FIG. 1 provides a typical example system schematic employing various switches on the primary and secondary sides of an isolation barrier;

FIG. 2 illustrates a prior art transformer-based electrically isolated switch driver circuit in which the transformer operates at a switching frequency;

FIG. 3 illustrates a prior art optocoupler-based electrically isolated switch driver circuit;

FIG. 4 illustrates a prior art transformer-based electrically isolated switch driver circuit in which the transformer operates at a carrier frequency substantially greater than the switching frequency;

FIG. 5 illustrates a prior art capacitively coupled electrically isolated switch driver circuit;

FIG. 6 shows a block diagram of a galvanically isolated low delay switch drive circuit with power transfer;

FIG. 7 shows an electrical isolation switch drive circuit in a typical application with drive commands from a PWM controller and a switch drive circuit driving the switch across the isolation barrier;

FIG. 8 shows a typical primary side block diagram of an electrically isolated switch driver circuit;

FIG. 9 shows a high efficiency pulse rectification circuit and voltage supply circuit for use on the floating side of an electrically isolated switch driver circuit;

FIG. 10 illustrates the behavior and timing relationships of key signals of an electrically isolated switch driver circuit, here employing a simple pulse generation scheme;

FIG. 11 illustrates an alternative behavior and timing relationship of key signals of an electrically isolated switch driver circuit, here employing a more advanced pulse generation scheme;

FIG. 12 shows a signal extraction and clock recovery circuit for use on the floating side of an electrically isolated switch driver circuit;

FIG. 13 illustrates an example of a state transition diagram showing the operation of a clock-synchronized Finite State Machine (FSM) used on the floating side of an electrically isolated switch driver circuit;

FIG. 14 shows a circuit implementation example of a clock-synchronized Finite State Machine (FSM);

FIG. 15 shows a circuit implementation example of a power switch driver circuit on the floating side of the electrically isolated switch driver circuit; and

fig. 16 shows an example of a Pulse Amplitude Modulation (PAM) information transmission scheme embedded from the primary side to the floating side of the isolator driver.

DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION

Fig. 6 shows an example block diagram of an example arrangement of the present application, showing an embodiment of a switch driver circuit for controlling the operation of the switch. The switch driver circuit provides both control and power transfer. The gate driver crosses the galvanic isolation barrier through a single pulse transformer 51.

Control and power transfer is performed by transferring pulses from a first (primary side) winding to a second (secondary side) winding of a pulse transformer.

On the primary side circuit of the switch drive circuit, an input signal IN from an external controller enters the primary drive circuit 51. The primary drive circuit is powered by a primary side supply voltage referred to as Vdrv. Other supply voltages required by the primary side circuitry can be obtained from Vdrv by using an optional linear regulator.

The primary drive circuit receives an input signal IN and derives a switch drive command therefrom. For example, an input may be interpreted as having two states, high and low. If the state of the input IN is considered to be "high", it is assumed that the external switch driven by the floating side of the driver needs to be turned on. Conversely, if the state of the input IN is considered to be "low", it is assumed that the external switch needs to be turned off. IN alternative embodiments, the input IN may have more states (e.g., a "floating" state, neither high nor low) IN which the driver may enter an alternative mode of operation. IN the remainder of this document, the detection of a change IN the input signal IN will be referred to as a "switching event".

Optionally, the primary drive circuit may also provide a unidirectional or bidirectional enable pin EN. When inactive, the signal EN indicates that the driver enters the disabled mode. The disable mode is typically used to reduce the supply current of the switch driver. When active, the signal EN enables the driver and instructs it to enter a normal operating mode. Upon entering a primary-side fault condition, such as the operating Voltage Vdrv dropping below a sufficient level, also known as under-Voltage Lockout (UVLO), or operating Temperature outside of a desired range, also known as Over-Temperature-Protection (OTP), or similar problem, the driver itself may deactivate EN. When implemented in a bi-directional manner, the signal EN may be deasserted by an external controller or isolated switch driver, thereby enabling both devices to respond to a fault condition in a desirably synchronous manner. The bi-directional signal EN may be implemented using wired and connected structures familiar to those skilled in the art.

IN the switch-on command, when the input IN goes from low to high, pulse information is sent from the primary circuit 50 to the floating side of the driver through the transformer 51. Similarly, IN the switch-off command, when the input IN changes from high to low, pulse information is transmitted.

The pulses received on the floating side (on the secondary side of the transformer) are supplied to a power supply circuit which in turn converts them into a secondary side voltage source Vs. The pulses are also provided to a control circuit 57, which control circuit 57 provides a switching signal to operate the controlled switch. It is advantageous to separate the transfer of pulses between the power supply circuits from the control circuit, as this allows the control circuit to respond to the arrival of a pulse before the power supply circuit attempts to extract power from the pulse. More particularly, it will be appreciated that the transfer of power from the transformer windings is strongly affected by leakage inductance, as this limits the rate of change of voltage where current (power) is transferred. By allowing the control circuit to detect the arrival of a pulse from the secondary winding before the power supply attempts to draw a significant amount of current from the secondary winding, the effects of leakage inductance can be reduced. A substantial current reference is used because a small current may be drawn during the delay before the power supply begins to draw power. The delay may be implemented using a delay circuit. The delay circuit may impose a predetermined delay or may limit the power supply current drawn until the voltage (pulse amplitude) presented from the secondary side winding exceeds a predetermined voltage. In this case, the control circuit is suitably configured to detect the arrival of the pulse based on a voltage lower than a predetermined voltage. The delay circuit may comprise a switch for switchably connecting the secondary winding to the power supply circuit after the delay. As described below, the switch may inherently provide a delay.

In an exemplary arrangement, the floating supply circuit 52 provides a unipolar supply voltage with reference to a floating reference voltage (ground F). The power supply voltage appears as a charge in the floating supply capacitor 56. With the arrival of the pulse, the charge in the supply capacitor is replenished.

Although the control circuitry and power supply circuitry on the secondary side may operate using bipolar voltages, it will be appreciated that unipolar circuits are easier to implement in silicon processes (e.g., CMOS ICs). A pulse rectification scheme is used for this purpose. The pulse rectification scheme converts the bipolar pulses (negative and positive) into first and second control signals having a common polarity, wherein one of the first and second control signals represents a negative pulse and the other represents a positive pulse. Thus, as shown in the timing diagram of fig. 10, the bipolar nature of the signal Vf across the secondary winding of the transformer is converted into control signals Va and Vb, where Va represents a positive pulse and Vb represents a negative pulse. The use of a pulsed rectification scheme means that the voltages present in the control circuit and the power supply circuit are unipolar with respect to floating ground Vf.

The pulse rectification scheme based on the active switches within the power circuit 52 ensures that the pulsed power is transferred from the primary side to the floating side in an efficient manner. The rectification scheme may be shared with the control circuit 57. As a result of the pulsed power transfer, a floating operating voltage Vs is established with respect to the floating ground. The floating side circuitry of the switch driver may use this operating voltage Vs directly for power supply purposes. Optionally, the floating supply circuit 52 may further comprise means for deriving a calibrated floating supply voltage Vsr. The supply capacitor 56 may be an on-chip capacitor integrated into the floating drive circuit. Since the capacitance constraints apply to the chip integrated capacitors, the capacitor 56 may alternatively be implemented or modified by discrete off-chip capacitors connected in parallel.

The isolation pulse transformer 51 is typically only used to transmit short pulses. In this context, the term short pulse may be considered with respect to the duration of the switching period of the controlled switch. This can be seen IN fig. 10, where the duration of the pulse transmitted from the primary side Vp is short relative to the duration of the ON pulse IN the signal IN. Thus, the time integral of the applied voltage across the coil, i.e. vp and vf, remains small. This translates into a small flux swing in the transformer core, which in turn means that the cross-sectional area of the transformer core can be made small. Thus, the transformer 51 can be manufactured in a compact form, making it well suited for package integration. In the simplest implementation of a switching driver according to the present application, one polarization pulse will be sent on the pulse transformer 51 in each switching event.

Therefore, the transformer 51 operates at the switching frequency, so that the transformer loss is small. Note that this is in contrast to the high pulse repetition frequency employed in solutions such as reference 1.

In normal operation, the polarity of the applied coil voltage is varied in an alternating manner between pulses, resulting in an average magnetic flux of about 0 volt-seconds (Vs). The dipole flux swing around 0Vs further reduces the core losses and thus the size of the transformer core.

In addition, as will be discussed in more detail below, the requirements regarding leakage inductance of the transformer can be relaxed, making the transformer very simple in construction, where the primary and floating coils can be well separated in space. Thus, the transformer 51 can even meet stringent isolation barrier requirements with respect to isolation testing and operating voltage.

The pulsed rectified voltages va and vb with respect to the floating side ground generated by 52 are injected into a clock recovery circuit 53, which clock recovery circuit 53 extracts the clock signal from the pulses. The clock recovery circuit converts the analog voltages va and vb into digital signals a and B, and also generates a clock signal clk. In the simplest implementation of a switch driver, signals a and B are single bit signals. In more complex pulse coding schemes (e.g., using pulse amplitude modulation), signals a and B may be bit vectors that each carry two or more bits. The clock signal clk is typically asynchronous because the pulses are transferred from the primary side circuit to the floating side circuit after an asynchronous switching event. In other words, although the clock signal clk may arrive on the floating side periodically, they are typically not separated by even time intervals. The method of using the extracted clock signal means that the operation is based on pulse transitions rather than the pulse amplitude itself. Thus, by this approach, additional functionality and more advanced modulation schemes may be included. This is illustrated in the methods of fig. 11 and 16 discussed below.

By first carefully sequencing and prioritizing the floating side activity of signal detection and clock recovery, and then charge transferring the pulsed power into capacitor 56, it is ensured that the propagation delay of the driver, measured from the switching event detected at signal IN to the expected response of the driver's outputs OUTPU and OUTPD, is not affected by the transfer of power from the primary side to the floating side. This is a key aspect of the present application. This ensures that the propagation delay of the driver is substantially independent of the practical limitations of the pulse transformer 51 (including its leakage inductance).

The clock synchronization Finite State Machine (FSM)54 neither employs nor requires a synchronous clock signal. FSM 54 utilizes digital inputs a and B along with clock signal clk to achieve well-defined clock-synchronous state transitions. Regardless of its current state, an optional reset signal generated on the floating side of the switch driver may be used to asynchronously force FSM 54 into a known safe reset state. FSM 54 may be implemented in a conventional manner, which may use a Mealy or Moore type implementation. FSM 54 supports the interpretation of simple ON and OFF pulse transmission methods, as well as more complex pulse patterns that involve modulating the amplitude and/or duration of the pulses.

Output S of FSM 54 controls output switch drive circuit 55, which in turn generates pull-up switch drive signal OUTPU and pull-down switch drive signal OUTPD. In a simple implementation, the output S may be a one-bit digital signal. In other embodiments, FSM 54 facilitates the generation of bit vector S to satisfy the higher level control of power switch drive circuit 55 by FSM 54.

The output of the output switch driver circuit 55 is divided into two independent pull-up and pull-down paths, which can independently control the on and off output impedance of the gate driver. For less demanding applications a single push-pull output may be sufficient (only the outputs OUTPU and OUTPD need to be tied together).

It should be noted that IN contrast to prior art references 4-7, the floating side of the isolation driver always maintains full control of the switch drive, and when operating conditions are deemed inadequate (e.g., due to floating side UVLO or other fault conditions), even if a switch on command is detected at the input IN, the power switch may be automatically inhibited from opening. IN other words, the floating side circuit of the isolator switch driver may override the switch command received at the input IN, if necessary.

At system start-up, the floating side supply voltage can be safely established by sending a sufficient number of OFF pulses through the primary side before entering normal operation. This allows the floating-side power supply circuit 52 to boost and establish the operating voltage Vs while ensuring that the power switch is not inadvertently and prematurely turned on.

The present application also supports power switches that operate at very low switching frequencies all the way to dc (i.e., quiescent) operation. During quiescent operation, without any pulses reaching the floating side, the continuous supply current on the floating side will cause the supply capacitor 56 to slowly discharge. By detecting the absence of a state change at the input IN, the primary side can autonomously intervene and periodically transmit ON or OFF pulses (depending ON the quiescent state of the input IN) to maintain an ordered floating side operating voltage and to continuously maintain the power switches IN the desired state. The refresh operation is performed by a refresh circuit located in the primary side control circuit 50.

Fig. 7 shows the above-described electrically isolated switch driver 61 in a typical simplified system arrangement. PWM controller 60 provides input IN and bi-directional signal EN to isolation switch driver 61. On the floating side, an integrated floating supply capacitor 62 may be connected in parallel with a discrete capacitor 63, so that the value of the floating side supply capacitance increases.

The outputs of the isolated switch driver 61 (i.e., OUTPU and OUTPD) are connected to the gate G of the power switch 66 through resistors 64 and 65. By varying the resistance values of resistors 64 and 65, respectively, the system designer can independently adjust the effective on-resistance and off-resistance. The floating reference point of the driver is connected to the reference electrode S of the power switch 66 through pin OUTSS.

Fig. 8 shows an exemplary primary side block diagram of an electrically isolated switch driver circuit. The primary side power supply circuit 01 receives a primary side power supply voltage through pins VDRV and GND, and distributes the voltage VDRV and the main ground to the respective primary side circuit blocks. Circuit 01 may optionally generate other calibrated or uncalibrated supply voltages as required by other primary side circuit blocks. Circuit 01 may also include other optional functions such as primary side Under Voltage Lockout (UVLO), Over Temperature Protection (OTP), or the like. Circuit 01 may also support the power-saving off mode by using the bidirectional signal EN discussed previously.

Circuit module 02 conditions the input signal received at pin IN and compares it to two or more determined state voltage thresholds. If the input IN is found to be a logic high level, it is assumed that the power switch needs to be turned on. If the input IN is found to be a logic low level, it is assumed that the power switch needs to be turned off. Alternatively, additional states of the signal IN may be detected. For example, it may be advantageous to detect a floating input state. For example, upon detecting a floating IN, the isolator switch driver may enter a power saving mode.

The primary circuit block 03 detects a change IN the logic state of the input IN. In response to a change in logic state, module 03 generates a short single pulse or a higher order pulse train pattern. IN the simplest implementation, a pulse of a certain duration and a certain voltage polarity is generated across the primary winding of the pulse transformer 09 when the input IN transitions from low to high, whereas a pulse of the same duration but opposite voltage polarity is generated when the input IN transitions from high to low. This is shown in fig. 10 (signals 200 and 201). The rising edge of the input IN generates a short voltage pulse vp (201) of positive polarity, while the negative edge generates a short voltage pulse vp of negative polarity.

The duration of the pulses is just long enough for the floating side of the isolator driver to reliably detect their presence and also to support a sufficient amount of pulse power transferred to the floating side power supply circuit. In a typical application, the duration of the pulse can be a fraction of the total switching time period. During normal operation, subsequent pulses sent across the isolation transformer 09 have alternating polarity, ensuring that the average core flux remains near zero.

The pulses generated by module 03 are conditioned by circuit module 04 to ensure that the conventionally arranged H-bridge switches 05-08 operate efficiently while not cross-conducting and with a suitable level of gate drive. The H-bridge may be implemented using standard nMOS or pMOS devices, as shown in fig. 8.

In a higher level implementation of the isolator driver, the circuit 03 can generate a more complex pulse pattern and transmit through the pulse transformer 09. Fig. 11 shows an exemplary standby pulse pattern. Here, the low-to-high transition of input IN generates a pair of voltage pulses of opposite polarity, with positive pulses followed by negative pulses forming a pair of pulses (signal 211) as shown IN fig. 11. Similarly, the high-to-low transition of input IN generates a pulse pair having a negative voltage pulse followed by a positive voltage pulse. The advantage of generating multiple pulses per IN state transition is that multiple power pulses are transferred to the floating side per switching cycle, thereby relieving the requirements on the floating side power supply (including its energy storage capacitor). Disadvantages of transmitting multiple pulses IN each IN state transition include: 1) the iron core loss in the pulse transformer is increased due to the fact that the pulse repetition frequency is effectively increased; 2) higher level pulse mode decoding in the secondary side results in potentially higher propagation delay. However, by increasing the pulse repetition frequency, the duration of the pulses can be reduced even further compared to a single pulse IN each IN state transition.

Fig. 9 illustrates an exemplary pulse rectification scheme that includes a high efficiency pulse rectification circuit and a voltage supply circuit used on the floating side of an electrically isolated switch driver circuit. A high efficiency active pulse rectification circuit consists of active nMOS switches 11 and 12 and optional potential connection resistors 13 and 14.

The floating-side bipolar coil voltage vf is shown in fig. 10 (signal 202). The voltage vf is essentially a floating-side copy of the primary winding voltage vp (signal 201), which is scaled by the turns ratio of the pulse transformer 10.

Upon the occurrence of a positive polarity and a sufficiently large voltage pulse vf, the switch 11 of fig. 9 is turned on and temporarily establishes a connection between the lower terminal of the transformer 10 and the floating-side ground. This produces a positive voltage pulse va with respect to the floating side ground for the duration of the input positive voltage pulse vf, as shown in fig. 10 (signal 204). Conversely, a sufficiently large voltage pulse vf with a negative polarity will turn on the switch 12, temporarily establishing a connection between the dashed terminal of the pulse transformer 10 and the floating side ground. This produces a positive voltage pulse vb relative to the floating side ground as shown in fig. 10 (signal 205).

In essence, the high efficiency pulse rectification circuit formed by switches 11 and 12 prevents any other component terminals of the floating side circuit from being substantially exposed to a negative voltage (ground with respect to the floating side), which greatly simplifies the integration of the components into an Integrated Circuit (IC). This fact is also illustrated in fig. 10 and 11 by the fact that the only bipolar voltages in the circuit are represented by the pulse transformer voltages vp and vf (signals 201, 202, 211, 212). All floating-side signals and circuit nodes remain substantially unipolar with respect to the floating-side ground.

The active pulse rectification scheme just described allows power to be transferred from the primary side to the floating side with much higher power transfer efficiency, resulting in much lower conduction losses, compared to diode-based pulse rectification schemes. However, if such losses are acceptable, diodes may be employed.

The bundled resistors 13 and 14 ensure that during the pulse-free period the circuit nodes va and vb remain definite with respect to the floating side ground. Resistors 13 and 14 slightly pull circuit nodes va and vb to the floating side ground whenever voltage vf is close to zero. The resistance values of the resistors 13 and 14 can be chosen to be high, kilo-ohms (kQ) or higher, to ensure that the efficiency of the power transfer is largely unaffected.

The outputs of the pulse rectification circuit, namely va and vb, can be used to transfer power to the floating side supply capacitor 17. As shown in fig. 9, a simple charging scheme based on diodes (using diodes 15 and 16) can be used. The charge of the supply capacitor 17 is replenished whenever the voltage at node va or vb exceeds the instantaneous floating side supply voltage Vs by one diode forward drop. Resistors in series with diodes 15 and 16 may be used to limit the ripple charging current into capacitor 17, but are generally not required. The supplemental charge charged to the supply capacitor 17 at each power pulse ultimately originates at the primary side of the isolation switch circuit. The recharge current flowing into the floating supply capacitor 17 flows through a pair of diagonal primary H-bridge switches, pulse transformer coils, floating side pulse rectifier switches (11 or 12) and peak rectifier diodes (15 or 16). The components in the recharging path are of low impedance, ensuring that the capacitor 17 is recharged quickly each time a pulse is transmitted. The slew rate of the recharge current pulse into the capacitor 17 is limited by the leakage inductance of the pulse transformer.

It is important to note that the pulse rectification circuit ensures that the voltages va and vb are allowed to rise rapidly to appreciable and detectable levels before the diodes 15 or 16 become forward biased. Thus, diodes 15 and 16 may be used to achieve the above-mentioned reference delay between the detection of the control circuit of the pulse and the power supply circuit drawing power from the winding. Therefore, the switch-on information and the switch-off information carried by the start of the voltage pulse can be quickly detected by a clock recovery circuit (discussed below) before a large number of current pulses supplemented into the capacitor 17 start to flow. It is further important to note that the leakage inductance of the pulse transformer 10 does not slow down the initial rising edges of va and vb. Therefore, signal transmission from the primary driving circuit to the floating-side circuit is substantially independent of the leakage inductance.

The recharge current flowing into the supply capacitor 17 supplements its charge and supplements the voltage Vs across the capacitor 17. This is shown in fig. 10 (signal 207) and fig. 11 (signal 217). Shortly after the rising edge of the voltage va or vb, the voltage Vs is filled. During normal operation, the voltage Vs is kept above a certain lower limit so that the floating side circuit remains energized at all times.

It may be desirable to generate additional calibrated floating-side supply voltages. This can be simply achieved by using optional linear regulators 18 and 20 which provide a calibrated supply voltage Vsr and a calibrated digital supply voltage Vc. The floating-side protection circuit module 19 generates a reset signal if any of the floating-side supply voltages drops below an acceptable level, or if any other floating-side circuit problem (e.g., overheating) is detected.

At system start-up, the capacitor 17 will discharge before any pulse arrives and there is no supply voltage available on the floating side of the driver. The voltage Vs is close to zero and the derived voltages Vsr and Vc are also close to zero. To safely and quickly raise the floating-side supply voltage Vs to an acceptable level, the primary-side circuit can send one or more OFF pulses on the isolation barrier. Each OFF pulse will be pulse rectified because neither the pulse rectifying switches 11 and 12 nor the pulse charging diodes 15 and 16 need any operating voltage. After transmission of one or more OFF pulses, the voltage Vs will quickly reach a sufficient operating level. Sending an OFF pulse during system start-up ensures that the power switch does not turn on accidentally or prematurely.

In case the switching frequency drops to a very low level, or even reaches system conditions that require the power switch to be switched on or off statically, and in case no pulse reaches the floating side, the supply voltage Vs will decay to zero (since the floating side supply current will slowly discharge the capacitor 17). The primary side auto-refresh circuit is able to detect these low frequency or dc conditions and automatically intervene to transmit a refresh pulse of ON or OFF polarity across the pulse transformer 10 to maintain the power switch state and replenish the floating supply voltage Vs, depending ON the state of the input signal IN. This auto-refresh mode is transparently input to the user through the electrically isolated switch driver.

Fig. 12 shows a simple example of a signal extraction and clock recovery circuit used on the floating side of an electrically isolated switch driver circuit. A sufficiently large input voltage pulse at circuit node va is inverted and level-converted into a logic voltage range using an inverter based on nMOS 23 and pMOS 22. The output of the level-shifting inverter is fed into a schmitt trigger inverter 24, resulting in additional noise immunity and a steep slew rate. The output of the inverter 24 provides a reproduced accurate logic level image a with a very small propagation delay (typically tens or hundreds of picoseconds) relative to the input voltage pulse va. Alternatively, the logical two's complement of A, called A', can also be easily generated using the Schmitt trigger buffer 29 if required by the FSM. Side-by-side schmitt trigger elements with matching anti-phase and in-phase ensure that signals a and a' are active at approximately the same time.

The voltage pulse signal vb is processed in the same manner as by using a level-shifting inverter (followed by a schmitt trigger inverter 27) composed of an nMOS 26 and a pMOS 25. Optionally, a schmitt trigger buffer 21 may also be used to generate the two's complement of B, i.e., B', if desired.

By logically oring the digital signals a and B, the clock signal for edge sensitive circuits responding to rising edges can be easily generated because the pulses a and B never coincide, i.e., the pulses a and B do not take effect simultaneously. This is accomplished by the or gate 28 providing a clock signal clk that is used to clock the subsequent synchronous FSM discussed below.

It should be noted that even in the case where a vf voltage pulse of a certain polarity is followed by a voltage pulse of opposite polarity, the voltage vf must cross zero volts at a certain point, which means that one of the pulsed rectified signals (va or vb) falls to zero before the other pulse rises.

Deriving the clock signal from logic signals a and B by logic means such as or gate 28 ensures that signal a or B takes effect (propagation delay through one gate) before a valid rising clock edge. This will typically satisfy the set timing constraints of the synchronous execution FSM.

Typical clock signals generated by the clock recovery circuit are shown in fig. 10 (signal 203) and fig. 11 (signal 213).

Fig. 13 illustrates a state transition diagram illustrating the operation of a simple example embodiment of a clock-synchronized Finite State Machine (FSM). The three FSM states are: s _ RESET, S _ OFF and S _ ON. During normal operation, the FSM changes states accurately and synchronously after a determined clock event (i.e., a rising edge of the clock signal). The sync state transitions are shown using solid lines with arrows. The text form next to the arrowed state transition line shows the condition for each state transition. The real transition lines represent synchronous state transitions and the dashed transition lines represent asynchronous state transitions.

The simple FSM of fig. 13 requires only one independent steering logic input (a and its two's complement a') in addition to the clock signal. As shown, all state transitions are clocked except for the RESET state S _ RESET, which may be input asynchronously while the RESET signal is active.

When the FSM remains in the RESET state S _ RESET, the internal blocks of the floating-side circuit remain in the initialized state, and the output S of the FSM is forced to the safe default state. After release from the reset state, the FSM unconditionally enters the secure S _ OFF state at the first synchronization transition. Normal periodic synchronization operations may then commence.

The normal operation is very simple: at each active clock event, if a is active, FSM enters or maintains state S _ ON. Conversely, at each active clock event, if A' is active, the FSM enters or maintains state S _ OFF. The FSM supports normal cycle operation as well as operation in the refresh mode described above.

The FSM provides a synchronization output S. The output S may be a single bit output or may be a bit vector, depending on the requirements of the floating side driver output.

After the floating side fails, the FSM will revert to a safe reset state. The FSM is more robust than asynchronous designs because the states S _ OFF and S _ ON can only be entered after a valid clock edge after being released from reset. In contrast, asynchronous designs (e.g., based on SR latches) may not steadily enter a valid state after being released from reset, and thus are not desirable.

Fig. 14 shows a very simplified circuit implementation of the clock synchronization FSM discussed above. Since FSM states S _ RESET and S _ OFF produce the same output S ═ 0, they have been simplified and combined into one state. In other words, the FSM has been reduced to two valid states, which can be achieved using a single clock sensitive data flip-flop (DFF) 30. The non-inverting output of DFF30 provides output S. The inverted output of DFF30 is not used. Following standard practice, DFF30 also provides an active-low asynchronous clear function through input C, which can be easily driven by the logical complement of the input reset provided by inverter 31. The FSM shown in fig. 14 is very robust because it does not have the capability to maintain illegal states.

The split output driver stage for the floating side of the electrically isolated switching circuit is shown in fig. 15. As previously mentioned, it is advantageous to provide the output driver stage with separate pull-up output OUTPU and pull-down output OUTPD as shown. If the input S is 1, the output OUTPU is pulled to the positive floating supply voltage Vsr using pMOS transistor 37. If the input S is 0, then the output OUTPD is pulled to floating ground using nMOS transistor 38. Inverters 35 and 36 convert the input signal S from the FSM into appropriate gate drive signals for transistors 37 and 38.

Fig. 16 shows an example of an exemplary modulation scheme that may be implemented. As previously described, in this arrangement, the transition (rising/falling edge) of the pulse determines the timing of the switching signal for switching the switch. At the same time, however, Pulse Amplitude Modulation (PAM) is used for transmitting the side information. This auxiliary information is transferred from the primary side of the driver to the floating side in addition to the switch ON/OFF information and power. A demodulator may be employed to demodulate the side information from the PAM pulses. The auxiliary information may for example be used to adjust the drive voltage Vsr for the floating side calibration.

The PAM example scheme shown in fig. 16 is a higher-level version of the double pulse scheme shown in fig. 11, discussed previously. The PAM scheme does not use pulse pairs of fixed amplitude, but uses the second pulse of each pulse pair to transfer one data bit from the primary side (or transmit side) to the floating side (or receive side). In order to maintain a balanced flux in the pulse transformer, the subsequent ON and OFF pulse pairs of each switching cycle transmit the same data. The information pulses are amplitude modulated. In the given example, a pulse of smaller amplitude represents a binary "0" and a pulse of larger amplitude represents a binary "1". Thus, one bit of information is transferred from the primary side to the floating side every switching cycle. Since each switching cycle transmits two pulses of opposite polarity but of the same amplitude, redundancy occurs which can be used for error detection.

The transferred information bits can easily be fed into a parallel-to-serial converter on the pulse generator on the primary side and converted back into parallel data words by using a serial-to-parallel data converter on the floating side of the enhanced FSM. Thus, a bit vector of any word length can be transmitted by packing data. The data packets may be further enhanced to allow error detection and/or error correction using known communication techniques.

The information bits generated and serialized on the primary side by the enhanced pulse generation module are fed into the modified primary side drive bridge using six rather than four bridge devices to achieve PAM. The transmitted bit is referred to as tdata [ x ] in fig. 16 (signal 221). On the floating receiver side, a simple amplitude comparator can be used in an enhanced version of the clock recovery circuit to demodulate the incoming data. The received data is called rdata [ x ] in FIG. 16 (signal 225).

The PAM scheme shown in fig. 16 should be considered as an example. Many variations of this scheme are possible. For example, the simpler single pulse in each of the ON/OFF event schemes shown in FIG. 10 can be modified to include PAM.

In other embodiments, Pulse Duration Modulation (PDM) is preferably used in place of, or in combination with, PAM for the transmission of data.

It will be appreciated from the appended claims that the described arrangements represent a single useful set of approaches which, although recited as separate claims, may be usefully combined in any combination.

In the foregoing specification, the application has been described with reference to specific examples of embodiments. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims. For example, the connection may be any type of connection suitable for transferring signals from or to the respective node, unit or device, e.g. via an intermediate device. Thus, unless implied or stated otherwise, the connections may be, for example, direct connections or indirect connections.

Because the apparatus implementing the present application consists of, for the most part, electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding of the underlying concepts of the present invention and in order not to obscure or distract from the teachings of the present invention. It will be appreciated that although specific polarity devices such as PMOS, NMOS, PNP or NPN may be shown in the figures, alternative polarity devices may be employed with appropriate modifications to the circuitry.

Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. In an abstract, but still definite sense, any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as "associated with" each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being "operably connected," or "operably coupled," to each other to achieve the desired functionality.

Furthermore, those skilled in the art will recognize that boundaries between the functionality of the above described operations merely illustrative. The functionality of multiple operations may be combined into a single operation, and/or the functionality of a single operation may be distributed in other operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments. Also, although the claims are directed to the same isolated gate drive or reset circuit, the application should not be construed as limited thereby, but rather extended to perform the same method. However, other modifications, variations, and alternatives are also possible. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. Furthermore, the terms "a" or "an," as used herein, are defined as one or more. Also, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed to introduce elements of another claim by the indefinite articles "a" or "an" limiting any particular claim containing an element of the introduced claim to inventions containing only one such element, even though the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an". The same holds true for the use of definite articles. Terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe, unless otherwise indicated. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.