阅读说明：本技术 一种光电探测器及其制备方法 (Photoelectric detector and preparation method thereof ) 是由 杜建华 李超 罗超 强朝辉 关峰 王治 于 2020-06-10 设计创作，主要内容包括：一种光电探测器及其制备方法,该光电探测器包括由宽禁带氧化物半导体材料与非晶硅材料形成的半导体异质结,且宽禁带氧化物半导体材料与非晶硅材料的结界面设置有阻挡层,该阻挡层用于阻挡宽禁带氧化物半导体材料中的元素向非晶硅材料扩散。本申请通过采用由宽禁带氧化物半导体材料与非晶硅材料形成的半导体异质结结构,在300纳米至650纳米的波长范围内,都有较高的光吸收和电流转化效率,量子效率高；同时,通过在结界面中加入阻挡层结构,使得光电探测器在较大偏压与较高温度下的暗电流能保持稳定,探测准确性、稳定性远高于非晶硅同质结PIN；并且制备工艺与现有TFT背板兼容,具有制作成本低、易于工艺实现、生产效率高和良品率高等优点。(A photoelectric detector and a preparation method thereof are provided, the photoelectric detector comprises a semiconductor heterojunction formed by a wide bandgap oxide semiconductor material and an amorphous silicon material, a barrier layer is arranged at the junction interface of the wide bandgap oxide semiconductor material and the amorphous silicon material, and the barrier layer is used for blocking elements in the wide bandgap oxide semiconductor material from diffusing to the amorphous silicon material. By adopting the semiconductor heterojunction structure formed by the wide bandgap oxide semiconductor material and the amorphous silicon material, the light absorption and current conversion efficiency is higher in the wavelength range of 300-650 nanometers, and the quantum efficiency is high; meanwhile, a blocking layer structure is added in the junction interface, so that the dark current of the photoelectric detector can be kept stable under larger bias voltage and higher temperature, and the detection accuracy and stability are far higher than those of an amorphous silicon homojunction PIN; and the preparation process is compatible with the existing TFT back plate, and has the advantages of low manufacturing cost, easy process realization, high production efficiency, high yield and the like.)

1. The photoelectric detector is characterized by comprising a semiconductor heterojunction formed by a wide bandgap oxide semiconductor material and an amorphous silicon material, wherein a barrier layer is arranged at the junction interface of the wide bandgap oxide semiconductor material and the amorphous silicon material and is used for blocking elements in the wide bandgap oxide semiconductor material from diffusing to the amorphous silicon material.

2. The photodetector of claim 1, wherein the semiconductor heterojunction comprises: a P-type layer, an intrinsic layer, and an N-type layer, wherein:

the P-type layer is a P-type amorphous silicon layer, and the intrinsic layer is an intrinsic amorphous silicon layer;

the N-type layer is an N-type wide bandgap oxide semiconductor layer;

the blocking layer is disposed between the intrinsic layer and the N-type layer.

3. The photodetector of claim 2, further comprising a substrate, a bottom electrode, a lateral electrode, a protective layer, and a top electrode, wherein:

the substrate, the bottom electrode, the P-type layer, the intrinsic layer, the barrier layer, the N-type layer, the transverse electrode and the top electrode are sequentially stacked from bottom to top;

the protective layer covers the semiconductor heterojunction and first and second sides of the lateral electrode, the first and second sides being opposite and perpendicular to a surface of the substrate to which the bottom electrode is connected.

4. The photodetector of claim 3, wherein the protective layer further covers a surface of the lateral electrode remote from the substrate;

the protective layer is provided with a first through hole, and the top electrode is connected with the transverse electrode through the first through hole.

5. The photodetector of claim 3, further comprising a planarization layer covering third and fourth sides of the protective layer, the third and fourth sides being opposite and parallel to the first and second sides.

6. The photodetector of claim 5, wherein the protective layer further covers a surface of the lateral electrode remote from the substrate; the flat layer also covers the surface of the protective layer far away from the substrate;

the protective layer is provided with a first through hole, the flat layer is provided with a second through hole, the first through hole is communicated with the second through hole, and the top electrode is connected with the transverse electrode through the first through hole and the second through hole.

7. The photodetector of any one of claims 1 to 6, wherein the wide bandgap oxide semiconductor material comprises any one of: indium gallium zinc oxide IGZO, zinc oxide ZnO, titanium dioxide TiO2, indium gallium zinc Y oxide IGZYO and indium gallium zinc X oxide IGZXO, wherein X and Y represent doped tin and the ratio of X and Y doping is different.

8. A method of fabricating a photodetector, comprising:

preparing a bottom electrode on a substrate;

sequentially preparing a P-type layer and an intrinsic layer on the bottom electrode;

preparing a barrier layer on the intrinsic layer;

preparing an N-type layer and a transverse electrode on the barrier layer in sequence, wherein the P-type layer, the intrinsic layer and the N-type layer form a semiconductor heterojunction formed by a wide-bandgap oxide semiconductor material and an amorphous silicon material, and the barrier layer is used for blocking elements in the wide-bandgap oxide semiconductor material from diffusing to the amorphous silicon material;

and preparing a protective layer and a top electrode on the lateral electrode, wherein the protective layer covers the semiconductor heterojunction and the first side and the second side of the lateral electrode, and the first side and the second side are opposite and vertical to the surface of the substrate connected with the bottom electrode.

9. The manufacturing method according to claim 8, wherein the P-type layer is a P-type amorphous silicon layer, and the intrinsic layer is an intrinsic amorphous silicon layer; the N-type layer is an N-type wide bandgap oxide semiconductor layer.

10. The method according to claim 8, wherein the sequentially forming a P-type layer and an intrinsic layer on the bottom electrode and a barrier layer on the intrinsic layer comprises:

depositing a P-type layer on the bottom electrode by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, wherein the deposition process temperature is between 200 and 300 ℃;

replacing the chamber, and keeping the replaced chamber in vacuum;

and continuously depositing the intrinsic layer and the barrier layer in the replaced chamber by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, wherein the deposition process temperature is between 200 and 300 ℃.

Technical Field

The embodiment of the application relates to but is not limited to the technical field of semiconductor optoelectronic devices, in particular to a photoelectric detector and a preparation method thereof.

Background

In recent years, display devices have been fabricated as integrated photodetectors to perform various functions, such as: light sensing, biological information detection, human-computer interaction and the like. Amorphous silicon is commonly used for preparing amorphous silicon homojunction PIN (Positive Intrinsic negative) type thin film photoelectric detectors as a common photoelectric absorption conversion material, the preparation process of the amorphous silicon homojunction PIN (Positive Intrinsic negative) type thin film photoelectric detectors is good in compatibility with a Thin Film Transistor (TFT) process, and the integrated TFT + PIN can be used for optical fingerprint identification and the like.

Since the amorphous silicon material has a strong quantum efficiency in a visible light range of 500 nm to 600 nm, the band is used for detection. When a common detection device works in an environment, besides detected light reflected by a light source, visible light in the environment can be detected, but the visible light in the environment is noise, and the detection accuracy can be reduced, so that multiple detections are needed to improve the accuracy, and the detection efficiency is reduced.

Disclosure of Invention

The embodiment of the application provides a photoelectric detector and a preparation method thereof, which can improve the detection accuracy and detection efficiency of the photoelectric detector.

The embodiment of the application provides a photoelectric detector, which comprises a semiconductor heterojunction formed by a wide bandgap oxide semiconductor material and an amorphous silicon material, wherein a barrier layer is arranged on a junction interface of the wide bandgap oxide semiconductor material and the amorphous silicon material, and the barrier layer is used for blocking elements in the wide bandgap oxide semiconductor material from diffusing to the amorphous silicon material.

In some possible implementations, the semiconductor heterojunction includes: a P-type layer, an intrinsic layer, and an N-type layer, wherein: the P-type layer is a P-type amorphous silicon layer, and the intrinsic layer is an intrinsic amorphous silicon layer; the N-type layer is an N-type wide bandgap oxide semiconductor layer; the blocking layer is disposed between the intrinsic layer and the N-type layer.

In some possible implementations, the photodetector further includes a substrate, a bottom electrode, a lateral electrode, a protective layer, and a top electrode, wherein: the substrate, the bottom electrode, the P-type layer, the intrinsic layer, the barrier layer, the N-type layer, the transverse electrode and the top electrode are sequentially stacked from bottom to top; the protective layer covers the semiconductor heterojunction and the first and second sides of the lateral electrode, which are opposite and perpendicular to the surface of the substrate to which the bottom electrode is connected.

In some possible implementations, the protective layer also covers a surface of the lateral electrode away from the substrate; the protective layer is provided with a first through hole, and the top electrode is connected with the transverse electrode through the first through hole.

In some possible implementations, the photodetector further includes a planarization layer covering third and fourth sides of the protection layer, the third and fourth sides being opposite and parallel to the first and second sides.

In some possible implementations, the protective layer also covers a surface of the lateral electrode away from the substrate; the flat layer also covers the surface of the protective layer far away from the substrate; the protective layer is provided with a first through hole, the flat layer is provided with a second through hole, the first through hole is communicated with the second through hole, and the top electrode is connected with the transverse electrode through the first through hole and the second through hole.

In some possible implementations, the wide bandgap oxide semiconductor material includes any one of: indium gallium zinc oxide IGZO, zinc oxide ZnO, titanium dioxide TiO2, indium gallium zinc Y oxide IGZYO and indium gallium zinc X oxide IGZXO, wherein X and Y represent doped tin and the ratio of X and Y doping is different.

The embodiment of the application also provides a preparation method of the photoelectric detector, which comprises the following steps: preparing a bottom electrode on a substrate; sequentially preparing a P-type layer and an intrinsic layer on the bottom electrode; preparing a barrier layer on the intrinsic layer; preparing an N-type layer and a transverse electrode on the barrier layer in sequence, wherein the P-type layer, the intrinsic layer and the N-type layer form a semiconductor heterojunction formed by a wide-bandgap oxide semiconductor material and an amorphous silicon material, and the barrier layer is used for blocking elements in the wide-bandgap oxide semiconductor material from diffusing to the amorphous silicon material; and preparing a protective layer and a top electrode on the transverse electrode, wherein the protective layer covers the semiconductor heterojunction and the first side and the second side of the transverse electrode, and the first side and the second side are opposite and vertical to the surface of the substrate connected with the bottom electrode.

In some possible implementations, the P-type layer is a P-type amorphous silicon layer, and the intrinsic layer is an intrinsic amorphous silicon layer; the N-type layer is an N-type wide bandgap oxide semiconductor layer.

In some possible implementations, the P-type layer, the intrinsic layer, and the barrier layer are fabricated using a plasma enhanced chemical vapor deposition PECVD process; the method for preparing the P-type layer and the intrinsic layer on the bottom electrode in sequence and preparing the barrier layer on the intrinsic layer comprises the following steps: depositing a P-type layer on the bottom electrode, wherein the deposition process temperature is between 200 and 300 ℃; replacing the chamber, and keeping the replaced chamber in vacuum; and continuously depositing the intrinsic layer and the barrier layer in the replacement chamber, wherein the process temperature of the deposition is between 200 and 300 ℃.

According to the photoelectric detector and the preparation method thereof, the semiconductor heterojunction structure formed by the wide bandgap oxide semiconductor material and the amorphous silicon material is adopted, and the photoelectric detector has high light absorption and current conversion efficiency and high quantum efficiency in the wavelength range of 300-650 nm; meanwhile, a blocking layer structure is added in the junction interface, so that the dark current of the photoelectric detector can be kept stable under larger bias voltage and higher temperature, and the detection accuracy and stability are far higher than those of an amorphous silicon homojunction PIN; the embodiment of the application can be realized by using the existing mature preparation equipment, can be well compatible with the existing preparation process, has the advantages of low manufacturing cost, easy process realization, high production efficiency, high yield and the like, and has good application prospect.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. Other advantages of the present application may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification and the drawings.

Drawings

The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.

FIG. 1 is a schematic structural diagram of an amorphous silicon homojunction PIN;

fig. 2 is a schematic structural diagram of a photodetector according to an embodiment of the present application;

FIG. 3 is a schematic diagram of another embodiment of a photodetector according to the present application;

FIG. 4 is a schematic structural diagram of another photodetector according to an embodiment of the present application;

fig. 5 is a schematic flow chart illustrating a method for fabricating a photodetector according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of the structure after the bottom electrode is prepared;

FIG. 7 is a schematic diagram of the structure after fabrication of the P-type and intrinsic layers;

FIG. 8 is a schematic view of the structure after barrier layer fabrication;

fig. 9 is a schematic view of the structure after the N-type layer and the lateral electrodes are prepared;

FIG. 10 is a schematic view of the structure after the protective layer and top electrode are prepared;

FIG. 11 is a graph showing the results of an External Quantum Efficiency (EQE) test for three photodetectors;

fig. 12 is a graph showing dark current density test results of three types of photodetectors.

Description of reference numerals:

10-a substrate; 11-bottom electrode; 12-P type layer;

13 — an intrinsic layer; 14-a barrier layer; 15-N type layer;

16-a lateral electrode; 17 — a top electrode; 18-a protective layer;

19-a flat layer.

Detailed Description

The present application describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.

The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive concept as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive aspects to form yet another unique inventive aspect, as defined by the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not limited except as by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

Further, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other orders of steps are possible as will be understood by those of ordinary skill in the art. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Further, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.

As shown in fig. 1, in the amorphous silicon homojunction PIN, an Intrinsic (I) layer 13 absorbs an incident light signal to generate a photo-generated electron-hole pair, and under the action of a reverse bias, the photo-generated electron and the photo-generated hole drift to an n (negative) layer 15 and a p (positive) layer 12, respectively, to form a photocurrent. For a short-wavelength optical signal, photon energy is far larger than the forbidden bandwidth of amorphous silicon (a-Si), the short-wavelength optical signal absorbed by valence band electrons jumps to an energy level position with a higher conduction band, the photo-generated electrons interact with crystal lattices in the process of jumping to the bottom of the conduction band, energy is transferred to the crystal lattices, lattice vibration is enhanced, carrier scattering is enhanced, and the contribution of the photo-generated electrons to photocurrent is not as significant as that of photocurrent generated by a long-wavelength optical signal, so that the detection capability of the conventional amorphous silicon homojunction PIN on the short-wavelength optical signal is relatively weak.

The embodiment of the application provides a photoelectric detector, which comprises a semiconductor heterojunction formed by a wide bandgap oxide semiconductor material and an amorphous silicon material, wherein a barrier layer is arranged at the junction interface of the wide bandgap oxide semiconductor material and the amorphous silicon material, and the barrier layer is used for blocking elements in the wide bandgap oxide semiconductor material from diffusing to the amorphous silicon material.

The photoelectric detector of the embodiment of the application adopts a semiconductor Heterojunction (heterjunction) structure formed by a wide-bandgap oxide semiconductor material and an amorphous silicon material, has higher light absorption and current conversion efficiency in a wavelength range of 300 nanometers to 650 nanometers, has high quantum efficiency, and has wide-band absorption characteristics which are beneficial to increasing the signal quantity collected by the photoelectric detector, so that the signal to noise ratio is increased; meanwhile, a blocking layer structure is added in the junction interface, so that the dark current of the photoelectric detector can be kept stable under larger bias voltage and higher temperature, and the detection accuracy and stability are far higher than those of an amorphous silicon homojunction PIN; and the preparation process is compatible with the existing TFT back plate, and the requirement of mass production is met.

In one exemplary embodiment, the material of the wide bandgap oxide semiconductor may include: any one of wide bandgap Oxide semiconductors such as Indium Gallium Zinc Oxide (IGZO), Zinc Oxide (ZnO), titanium dioxide (TiO 2), Indium Gallium Zinc Y Oxide (IGZYO), Indium Gallium Zinc X Oxide (IGZXO), and X and Y represent doped metals: tin (Stannum, Sn) and the doping ratio of the two is different.

In an exemplary embodiment, as shown in fig. 2, the semiconductor heterojunction comprises: a P-type layer 12, an intrinsic layer 13, and an N-type layer 15, wherein: the P-type layer 12 is a P-type amorphous silicon layer, and the intrinsic layer 13 is an intrinsic amorphous silicon layer; the N-type layer 15 is an N-type wide bandgap oxide semiconductor layer; the barrier layer 14 is disposed between the intrinsic layer 13 and the N-type layer 15.

The light facing surface of the semiconductor heterojunction is the N-type wide bandgap oxide semiconductor layer, and the short wavelength optical signal can be converted into an effective optical current, so that the detection capability of the photoelectric detector on the short wavelength optical signal is improved.

In one exemplary embodiment, as shown in fig. 3, the photodetector further includes a substrate 10, a bottom electrode 11, a lateral electrode 16, a protective layer 18, and a top electrode 17, wherein: the substrate 10, the bottom electrode 11, the P-type layer 12, the intrinsic layer 13, the barrier layer 14, the N-type layer 15, the transverse electrode 16 and the top electrode 17 are sequentially stacked from bottom to top; the protective layer 18 covers the semiconductor heterojunction and the first and second sides of the lateral electrode 16, which are opposite and perpendicular to the surface of the substrate 10 to which the bottom electrode 11 is connected.

In one exemplary embodiment, as shown in fig. 3, the photodetector further includes a planarization layer 19, the planarization layer 19 covering third and fourth sides of the protective layer 18, the third and fourth sides being opposite and parallel to the first and second sides.

In another exemplary embodiment, as shown in fig. 4, the protective layer 18 also covers the surface of the lateral electrode 16 remote from the substrate 10; the protective layer 18 is provided with a first through hole through which the top electrode 17 is connected with the lateral electrode 16.

In one exemplary embodiment, as shown in fig. 4, the planarization layer 19 also covers the surface of the protective layer 18 away from the substrate 10; the planarization layer 19 is provided with a second through hole, which is through to the first through hole, and the top electrode 17 is connected to the lateral electrode 16 through the second through hole and the first through hole.

In the photodetector of the present embodiment, the protective layer 19 and the planarization layer 18 are fully covered on the photodetector, and only one electrode hole is left, which is beneficial to stability of device reliability.

In one exemplary embodiment, the photodetector further comprises a buffer layer, wherein: the buffer layer is disposed between the substrate 10 and the bottom electrode 11.

In one exemplary embodiment, the material of the substrate 10 may be sapphire, glass, silicon wafer, or other insulating material; the material of the bottom electrode 11 may be one or more of gold, silver, nickel, titanium, platinum, palladium, Indium Tin Oxide (ITO) electrode.

In one exemplary embodiment, the material of the barrier layer 14 may be silicon nitride (SiNx) or silicon oxide (SiO 2).

In one exemplary embodiment, the material of the lateral electrodes 16 may be ITO electrodes.

In one exemplary embodiment, the top electrode 17 may be an ITO electrode.

In one exemplary embodiment, the protective layer 18 may be provided by one or more stacked layers of silicon oxide, silicon nitride, silicon oxynitride, or the like.

As shown in fig. 5, an embodiment of the present application further provides a method for manufacturing a photodetector, where the method includes:

s1, preparing the bottom electrode 11 on the substrate 10, as shown in fig. 6.

In an exemplary embodiment, before the bottom electrode 11 is prepared, the preparation method further includes: the substrate 10 is cleaned.

In one exemplary embodiment, a bottom electrode 11 is fabricated on a substrate 10, comprising: preparing a buffer layer on the substrate 10; a bottom electrode 11 is prepared on the buffer layer.

In an exemplary embodiment, the material of the substrate 10 may be sapphire, glass, silicon wafer, or other insulating material.

In an exemplary embodiment, the material of the bottom electrode 11 may be one or more of gold, silver, nickel, titanium, platinum, palladium, Indium Tin Oxide (ITO) electrode.

In an exemplary embodiment, the preparation method further comprises: and etching the bottom electrode 11 based on the first mask to form a patterned bottom electrode layer.

S2, the P-type layer 12 and the intrinsic layer 13 are sequentially formed on the bottom electrode 11, as shown in fig. 7.

In one exemplary embodiment, the P-type layer 12 is a P-type amorphous silicon layer, and the intrinsic layer 13 is an intrinsic amorphous silicon layer.

In an exemplary embodiment, the P-type layer 12 and the intrinsic layer 13 are formed by Plasma Enhanced Chemical Vapor Deposition (PECVD), and the intrinsic layer 13 is deposited by changing the chamber after the P-type layer 12 is deposited on the bottom electrode 11, so as to prevent the intrinsic layer 13 from being contaminated by boron (B +) ions doped in the P-type layer 12 during the Deposition of the P-type layer 12 and the intrinsic layer 13.

The preparation sequence of the semiconductor heterojunction is P/I/N sequence preparation, and is opposite to the N/I/P process sequence of the PIN device in the related art. Compared with boron (B +) element doping, the cleaning chamber can be cleaned more thoroughly when phosphorus (P +) element doping is carried out, and in the deposition of PIN devices in the related art, after the deposition of the N-type layer 15, the chamber can be cleaned or replaced, and then the continuous deposition of the intrinsic layer 13 and the P-type layer 12 is carried out; after the P-type layer 12 is deposited, the semiconductor heterojunction of the embodiment of the present application needs to be replaced with a chamber to deposit the intrinsic layer 13 to ensure that the intrinsic layer is not contaminated because B + is difficult to be removed completely.

In one exemplary embodiment, when the P-type layer 12 and the intrinsic layer 13 are fabricated using the PECVD method, the chamber temperature of the PECVD apparatus is set to be between 200 degrees celsius (° c) and 300 ℃.

When the chamber temperature of the PECVD apparatus is set to 250 ℃ (conventional PIN deposition temperature), there is a peeling problem of the P-type layer 12 and the intrinsic layer 13, and thus, in an exemplary embodiment, the problem is solved by setting the chamber temperature of the PECVD apparatus to between 200 ℃ and 230 ℃.

In one exemplary embodiment, the P-type layer 12 may have a thickness of 20 nm to 70 nm, and, for example, the P-type layer 12 may have a thickness of 50 nm.

In one exemplary embodiment, the thickness of the intrinsic layer 13 may be 300 nanometers to 1.2 micrometers (um), and the thickness of the intrinsic layer 13 may be 900 nanometers, for example.

S3, preparing a barrier layer 14 on the intrinsic layer 13, as shown in fig. 8.

In one exemplary embodiment, the material of the barrier layer 14 may be silicon nitride (SiNx) or silicon oxide (SiO 2).

In an exemplary embodiment, the thickness of the barrier layer 14 may be 1 nm to 5 nm, and the thickness of the barrier layer 14 may be 2 nm.

In one exemplary embodiment, the barrier layer 14 is prepared using a PECVD method, and the barrier layer 14 and the intrinsic layer 13 are continuously deposited while a chamber of the PECVD apparatus is maintained under vacuum (firing vacuum).

The barrier layer 14 functions to prevent the diffusion of elements in the wide bandgap oxide semiconductor material in the upper layer (N-type layer 15) toward the intrinsic layer 13, which may cause an increase in leakage current of the device when the elements in the wide bandgap oxide semiconductor material diffuse toward the intrinsic layer 13; the photoelectric detector of the embodiment of the application stabilizes the dark current characteristic of the device by arranging the barrier layer 14, so that the characteristic of the device is kept stable under high temperature and high pressure.

S4, sequentially preparing an N-type layer 15 and a lateral electrode 16 on the barrier layer 14, as shown in fig. 9, the P-type layer 12, the intrinsic layer 13, and the N-type layer 15 form a semiconductor heterojunction formed by a wide-bandgap oxide semiconductor material and an amorphous silicon material, and the barrier layer 14 is used for blocking elements in the wide-bandgap oxide semiconductor material from diffusing to the amorphous silicon material.

In one exemplary embodiment, the N-type layer 15 may be an N-type wide bandgap oxide semiconductor layer.

In one exemplary embodiment, the material of the wide bandgap oxide semiconductor may include: any one of wide bandgap oxide semiconductors such as indium gallium zinc oxide IGZO, zinc oxide ZnO, titanium dioxide TiO2, indium gallium zinc Y oxide IGZYO, indium gallium zinc X oxide IGZXO, and X and Y represent doped metals: tin Sn and the doping ratio of the tin Sn and the Sn is different.

In one exemplary embodiment, the material of the lateral electrodes 16 may be ITO electrodes. Both the bottom electrode 11 and the lateral electrode 16 are used to collect the generated photogenerated carriers.

In one exemplary embodiment, the N-type layer 15 and the lateral electrodes 16 may be prepared using a magnetron sputtering method.

In an exemplary embodiment, the magnetron sputtering process for preparing the N-type layer 15 includes the following process parameters: the working gas is argon (without oxygen, namely the flow of oxygen is 0sccm), the flow of argon is 50-150 sccm, the working pressure is controlled to be 0.1-1 Pa, the sputtering power is controlled to be 4-5 kilowatts, and the scanning frequency of the magnet is 3 times or more than 3 times.

In one exemplary embodiment, the thickness of the N-type layer 15 may be 5 nm to 70 nm. Illustratively, the thickness of the N-type layer 15 may be 30 nm.

In one exemplary embodiment, the thickness of the lateral electrode 16 may be 10 nanometers to 70 nanometers. Illustratively, the thickness of the lateral electrode 16 may be 30 nanometers.

In an exemplary embodiment, the preparation method further comprises:

wet etching is carried out on the N-type layer 15 and the transverse electrode 16 based on a second mask to form a patterned N-type layer 15 and a patterned transverse electrode 16;

and dry etching the intrinsic layer 13 and the P-type layer 12 based on the third mask to form the patterned intrinsic layer 13 and the P-type layer 12.

S5, preparing a protective layer 18 and a top electrode 17 on the lateral electrode 16, as shown in fig. 10, the protective layer 18 covering the semiconductor heterojunction and the first and second sides of the lateral electrode 16, the first and second sides being opposite and perpendicular to the surface of the substrate 10 connected to the bottom electrode 11.

In one exemplary embodiment, the thickness of the protective layer 18 may be 50 nm to 200 nm, and the thickness of the protective layer 18 may be 100 nm. The protective layer 18 may be used to protect the sidewalls of the semiconductor heterojunction.

In one exemplary embodiment, the protective layer 18 may be provided by one or more stacked layers of silicon oxide, silicon nitride, silicon oxynitride, or the like.

In one exemplary embodiment, after preparing the protective layer 18 and before preparing the top electrode 17, the preparation method further includes: a planarization (Resin) layer is prepared on the protective layer 18, and a planarization layer 19 covers third and fourth sides of the protective layer 18, which are opposite and parallel to the first and second sides, so that subsequent electrodes are lapped. The thickness of the planarization layer 19 can be set according to the actual requirements of the device.

In an exemplary embodiment, after preparing the planarization layer 19, the preparation method further includes: based on the fourth mask, the protective layer 18 and the planarization layer 19 are etched together, and the protective layer 18 and the planarization layer 19 of the lateral electrode 16 away from the surface of the substrate 10 are etched away.

In one exemplary embodiment, the top electrode 17 is prepared, including: and depositing a transparent electrode, and etching the transparent electrode based on a fifth mask to form a top electrode wire.

In one exemplary embodiment, the top electrode 17 may be an ITO electrode.

In one exemplary embodiment, the thickness of the top electrode 17 may be 20 nm to 700 nm. Illustratively, the top electrode 17 may have a thickness of 40 nanometers.

In one exemplary embodiment, the protective layer 18 also covers the surface of the lateral electrode 16 remote from the substrate 10; the protective layer 18 is provided with a first through hole through which the top electrode 17 is connected to the lateral electrode 16.

In one exemplary embodiment, the planarization layer 19 also covers the surface of the protective layer 18 away from the substrate 10; the planarization layer 19 is provided with a second through hole, which is through to the first through hole, and the top electrode 17 is connected to the lateral electrode 16 through the second through hole and the first through hole.

As shown in fig. 11 and 12, experimental results show that the photodetector according to the embodiment of the present invention has a higher quantum efficiency in a wavelength range of 300 to 650 nm, and is stable and has no offset when tested under a bias voltage of 10V at 70 ℃ for 2h, which indicates that the photodetector according to the embodiment of the present invention has a very good applicability to a long-time, high-precision, high-temperature, high-pressure environment, and has a comprehensive performance improvement compared with a conventional amorphous silicon PIN device.

In the description of the embodiments of the present application, it should be understood that the terms "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and therefore, should not be construed as limiting the present application.

In the description of the embodiments of the present application, it should be noted that the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected unless explicitly stated or limited otherwise; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

Although the embodiments disclosed in the present application are described above, the descriptions are only for the convenience of understanding the present application, and are not intended to limit the present application. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims.