阅读说明：本技术 一种高增益低噪声的开关电容可调增益放大器 (High-gain low-noise switched capacitor adjustable gain amplifier ) 是由 王磊 于 2020-04-24 设计创作，主要内容包括：本发明提出一种高增益低噪声的开关电容可调增益放大器,包括外部信号源、方波发生器、开关电容积分器和具有信号放大功能的反馈电路,外部信号源、方波发生器接入开关电容积分器,开关电容积分器通过反馈电路输出,开关电容积分器包括7个由正向脉冲开启的COMS开关管、采样电容、可调反馈电容和积分电容,反馈电路包括运算放大器。本发明通过将反馈电容在时间上减少被积分的频率等效为减少了反馈电容的容值,在实现高增益的同时降低了PGA的噪声,同时电路的版图面积没有增加,降低功耗和成本,提高了电路的检测精度和效率,适用于各种传感器接口、信号调理芯片和信号链路,在汽车电子、白色家电、工业自动化和物联网中有很大的市场发展前景。(The invention provides a high-gain low-noise switched capacitor adjustable gain amplifier, which comprises an external signal source, a square wave generator, a switched capacitor integrator and a feedback circuit with a signal amplification function, wherein the external signal source and the square wave generator are connected into the switched capacitor integrator, the switched capacitor integrator outputs through the feedback circuit, the switched capacitor integrator comprises 7 COMS switching tubes which are started by forward pulses, a sampling capacitor, an adjustable feedback capacitor and an integrating capacitor, and the feedback circuit comprises an operational amplifier. The invention reduces the frequency of the integrated feedback capacitor in time to be equivalent to the capacitance value of the feedback capacitor, thereby reducing the noise of PGA while realizing high gain, simultaneously reducing power consumption and cost, improving the detection precision and efficiency of the circuit, being suitable for various sensor interfaces, signal conditioning chips and signal links, and having great market development prospect in automobile electronics, white household appliances, industrial automation and internet of things.)

1. A high-gain low-noise switched capacitor adjustable gain amplifier, comprising: the frequency division control circuit comprises an external signal source, a square wave generator with a frequency division function, a switched capacitor integrator and a feedback circuit with a signal amplification function, wherein the external signal source is connected to the switched capacitor integrator;

the switched capacitor integrator comprises 7 COMS switch tubes started by forward pulses, a sampling capacitor (104), an adjustable feedback capacitor (108) and an integrating capacitor (102), a feedback circuit comprises an operational amplifier (111), the COMS switch tubes started by the forward pulses are all connected with a square wave generator and comprise a first COMS switch tube (103), a second COMS switch tube (105), a third COMS switch tube (106), a fourth COMS switch tube (107), a fifth COMS switch tube (109), a sixth COMS switch tube (110) and a seventh COMS switch tube (209);

one end of the second COMS switch tube (105) is connected with an external signal source to obtain an input signal, the other end of the second COMS switch tube (105) is connected with one end of the sampling capacitor (104) and one end of the third COMS switch tube (106) in common, and the other end of the third COMS switch tube (106) is grounded; the other end of the sampling capacitor (104) is connected with one end of a first COMS switch tube (103), one end of a fourth COMS switch tube (107) and one end of an adjustable feedback capacitor (108) in common, and the other end of the fourth COMS switch tube (107) is grounded; the other end of the first COMS switch tube (103) is connected with the inverting input end of the operational amplifier (111); two ends of the integrating capacitor (102) are respectively connected with the reverse input end and the output end of the operational amplifier (111), and the forward input end of the operational amplifier (111) is grounded; the other end of the adjustable feedback capacitor (108) is connected with one end of a fifth COMS switch tube (109), one end of a seventh COMS switch tube (209) and one end of a sixth COMS switch tube (110) in a common mode, the other end of the fifth COMS switch tube (109) and the other end of the seventh COMS switch tube (209) are grounded, the other end of the sixth COMS switch tube (110) is connected with the output end of an operational amplifier (111), and the output end of the operational amplifier is used for outputting a signal for a total output end;

the square wave generator comprises an oscillator circuit, a phase non-overlapping circuit and a frequency divider which are sequentially connected and used for generating an isochronous-length biphase non-overlapping clock signal, wherein the square wave of the first phase is sampling time, and the square wave of the second phase is integration time.

2. A high-gain low-noise switched capacitor adjustable gain amplifier according to claim 1, wherein the square wave generator outputs a clock signal to the sampling capacitor (104), and the sampling capacitor (104) is controlled to sample and integrate the input signal in two time segments of one clock cycle, where the sampling time segment is the integration time segment.

3. A high-gain low-noise switched capacitor adjustable gain amplifier according to claim 1, wherein the square wave generator outputs a clock signal to the adjustable feedback capacitor (108), and the adjustable feedback capacitor (108) is controlled to sample and integrate the input signal in two time segments of one clock cycle, where the sampling time segment is N times the sampling time segment after frequency division, that is: and in every N cycles, 1 cycle is an effective sampling period, the rest N-1 cycles are null samples, N is a frequency division coefficient and is controlled by a frequency divider, and the integration period of the N is consistent with the integration period of the control sampling capacitor (104).

4. A high gain low noise switched capacitor adjustable gain amplifier according to claim 3, wherein the amount of charge sampled by the feedback capacitor (108) on average every N cycles is: (Q)₁₀₈)_AVE＝Vout·C₁₀₈/N。

5. Use of a high gain, low noise switched capacitor variable gain amplifier according to any of claims 1-4 in switched capacitor variable gain circuits for signal detection, analog to digital conversion, sensor signal amplification and conditioning.

6. A sampling and integration time control method for a switched capacitor adjustable gain amplifier is characterized in that a sampling time period and an integration time period of an adjustable feedback capacitor (108) of the switched capacitor adjustable gain amplifier are respectively controlled:

1) controlling the clock signal of the integration time period of the adjustable feedback capacitor (108) to be consistent with the clock signal of the integration time period of the sampling capacitor (104);

2) the clock signal for controlling the sampling time period of the adjustable feedback capacitor (108) is a clock signal subjected to N times of frequency division, namely the effective sampling time period of the adjustable feedback capacitor (108) in each N periods is 1 period, the samples in other N-1 periods are null samples, the null samples are sampled, namely the voltage of the samples is 0, and N is a frequency division coefficient.

Technical Field

The invention relates to the field of integrated circuit design, in particular to a high-gain low-noise switched capacitor adjustable gain amplifier.

Background

A switched capacitor variable gain amplifier (PGA) is often used in a sensor signal detection, analog-to-digital signal conversion (ADC) and digital-to-analog (DAC) conversion circuit. However, in the conventional PGA circuit with a switched capacitor, when a higher gain is achieved, the ratio of the input capacitor to the feedback capacitor of the switched capacitor amplifier is often increased, or a two-stage PGA circuit is cascaded. The former realizes high gain and simultaneously has much noise amplification of the switch capacitor, and the latter has defects in power consumption and chip area occupation consideration.

As shown in fig. 1, for example, a single-ended output switch capacitor PGA is used, a control clock signal of a CMOS switch is an equal-duration two-phase square wave with non-overlapping characteristics, a pulse square wave of a first phase is a sampling time, a pulse square wave of a second phase is an amplification or integration time, and charges of a sampling capacitor and an adjustable feedback capacitor are integrated by an operational amplifier through a feedback path. In the figure 120, a non-overlapping pulse generator generates the gate control signals for the switching tubes, and φ 1 and φ 2 are sampling and integration periods, respectively.

This achieves sampling and amplification of the signal within the time of one cycle. According to the working principle of the switch capacitor, the amplification factor of the PGA at phi 2 is the ratio of the input capacitor to the feedback capacitor:

Gain＝Vout(n)/Vin(n)＝C₁₀₄/C₁₀₈

where n is the number of pulse cycles.

The noise originated from the switched capacitor is a key index affecting the accuracy of the output signal, and the high amplification factor PGA should be designed to reduce the noise as much as possible. The switched capacitor noise entering the inverting input of the op-amp in fig. 1 is expressed in charge as:

where K is a constant and T is an absolute temperature value.

If translated to the input switched capacitor 104, the equivalent noise voltage at the input is expressed as:

the noise voltage at the output is:

in equation (3), the Gain is a value set by the amplification of the PGA signal, and generally Gain > >1, it can be seen that the reduction of the equivalent output noise of the PGA must increase the capacitance of the tunable capacitor 108 when Gain is a set value. But increasing the capacitance of the capacitor 108 is severely limited,

1. increasing the capacitance value of 108, and correspondingly increasing the capacitance value of 104 in order to keep the Gain unchanged; meanwhile, in order to maintain a certain system bandwidth, noise is filtered, and the reduction of the closed-loop feedback coefficient of the operational amplifier 111 is prevented from influencing the integration precision, the capacitance value of the integrating capacitor 102 must be increased. The result is a significant increase in the area required for the chip and an increase in cost.

2. If the capacitance values of 108 and 104 are increased simultaneously, the power consumption is also increased, because the charging and discharging current required by the operational amplifier 111 to complete integration is increased obviously and the chip power consumption is increased.

In practical application, most of the PGAs are in fully differential structures, and the principle is unchanged. The above formula for switched capacitor noise is the same as the problem encountered.

Disclosure of Invention

The invention solves the technical problem of providing a high-gain low-noise switched capacitor adjustable gain amplifier, which reduces the integrated frequency of a feedback capacitor in time to be equivalent to reducing the capacitance value of the feedback capacitor, reduces the noise of a switched capacitor circuit under the condition of realizing high gain, does not increase the layout area of the circuit, reduces the power consumption and the cost, improves the detection precision and the efficiency of a signal detection circuit, is suitable for various sensor interfaces, signal conditioning chips and signal links, and has great market development prospect in automotive electronics, white household appliances, industrial automation and the Internet of things.

The technical solution for realizing the purpose of the invention is as follows:

a high-gain low-noise switched-capacitor adjustable gain amplifier, comprising: the frequency division control circuit comprises an external signal source, a square wave generator with a frequency division function, a switched capacitor integrator and a feedback circuit with a signal amplification function, wherein the external signal source is connected to the switched capacitor integrator; the switched capacitor integrator comprises 7 COMS switch tubes started by forward pulses, a sampling capacitor, an adjustable feedback capacitor and an integrating capacitor, a feedback circuit comprises an operational amplifier, the COMS switch tubes started by the forward pulses are all connected with a square wave generator and comprise a first COMS switch tube, a second COMS switch tube, a third COMS switch tube, a fourth COMS switch tube, a fifth COMS switch tube, a sixth COMS switch tube and a seventh COMS switch tube; one end of the second COMS switch tube is connected with an external signal source to obtain an input signal, the other end of the second COMS switch tube is connected with one end of the sampling capacitor and one end of the third COMS switch tube in a common mode, and the other end of the third COMS switch tube is grounded; the other end of the sampling capacitor is connected with one end of the first COMS switch tube, one end of the fourth COMS switch tube and one end of the adjustable feedback capacitor in a common mode, and the other end of the fourth COMS switch tube is grounded; the other end of the first COMS switch tube is connected with the inverting input end of the operational amplifier; two ends of the integrating capacitor are respectively connected with the reverse input end and the output end of the operational amplifier, and the forward input end of the operational amplifier is grounded; the other end of the adjustable feedback capacitor is connected with one end of a fifth COMS switch tube, one end of a seventh COMS switch tube and one end of a sixth COMS switch tube, the other end of the fifth COMS switch tube and the other end of the seventh COMS switch tube are both grounded, the other end of the sixth COMS switch tube is connected with the output end of an operational amplifier, and the output end of the operational amplifier is used for outputting a signal for a total output end; the square wave generator comprises an oscillator circuit, a phase non-overlapping circuit and a frequency divider which are sequentially connected and used for generating an isochronous-length biphase non-overlapping clock signal, wherein the square wave of the first phase is sampling time, and the square wave of the second phase is integration time.

Further, in the high-gain low-noise switched capacitor adjustable gain amplifier of the present invention, the square wave generator outputs a clock signal to the sampling capacitor, and the sampling capacitor is controlled to sample and integrate the input signal in two time periods of one clock cycle, where the sampling time period is an integration time period.

Further, in the high-gain low-noise switched capacitor adjustable gain amplifier of the present invention, the square wave generator outputs a clock signal to the adjustable feedback capacitor, and controls the adjustable feedback capacitor to sample and integrate the input signal in two time periods of a clock cycle, where the sampling time period is a sampling time period after N times of frequency division, that is: and in every N cycles, 1 cycle is an effective sampling period, the rest N-1 cycles are null samples, N is a frequency division coefficient and is controlled by a frequency divider, and the integration period of the N is consistent with the integration period of the control sampling capacitor.

Furthermore, in the high-gain low-noise switched capacitor adjustable gain amplifier of the invention, the charge quantity sampled by the feedback capacitor (108) in each N periods is as follows: (Q)₁₀₈)_AVE＝Vout·C₁₀₈/N。

The application of the high-gain low-noise switched capacitor adjustable gain amplifier in a switched capacitor adjustable gain circuit for signal detection, analog-to-digital conversion, sensor signal amplification and conditioning.

A sampling and integration time control method of a switched capacitor adjustable gain amplifier respectively controls a sampling time period and an integration time period of an adjustable feedback capacitor of the switched capacitor adjustable gain amplifier:

1) controlling the clock signal of the integration time period of the adjustable feedback capacitor to be consistent with the clock signal of the integration time period of the sampling capacitor;

2) the clock signal for controlling the sampling time period of the adjustable feedback capacitor is a clock signal subjected to N times of frequency division, namely the effective sampling time period of the adjustable feedback capacitor in each N cycles is 1 cycle, the sampling of other N-1 cycles is null sampling, namely the voltage of the sampling is 0, wherein N is a frequency division coefficient.

Compared with the prior art, the invention adopting the technical scheme has the following technical effects:

the high-gain low-noise switched capacitor adjustable gain amplifier does not reduce the true capacitance value of the adjustable feedback capacitor to increase noise while increasing the amplification factor, does not increase the capacitance value of the adjustable feedback capacitor, and increases the chip area and the charge-discharge current of the operational amplifier due to the synchronous increase of the capacitance value of the integrating capacitor 102, thereby realizing the high amplification factor without increasing the occupied wafer area and power consumption.

Drawings

Fig. 1 is a circuit diagram of a conventional single-ended output switched capacitor PGA.

Fig. 2 is a circuit diagram of the high-gain low-noise switched capacitor adjustable gain amplifier of the present invention.

Fig. 3 is a schematic diagram of a control clock when the frequency division multiple of the high-gain low-noise switched capacitor adjustable gain amplifier of the invention is 4.

Fig. 4 is a schematic diagram of a fully differential architecture of a high-gain low-noise switched capacitor variable gain amplifier of the present invention.

Reference signs mean: 101: signal source, 103, 105, 106, 107, 109, 110, 209: forward pulse-on CMOS switch tube, 102: integration capacitance, 104: sampling capacitance, 108: adjustable feedback capacitor, 111 is an operational amplifier, 301: differential mode input signal, 302: common mode input signal, 303-312: CMOS switch tube, 320, 321: input capacitance pair, 322, 323: feedback capacitance pair, 324, 325: integrating capacitance pair, 331: and (4) fully-differential output operational amplifier.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.

A high-gain low-noise switched capacitor adjustable gain amplifier, as shown in fig. 2, comprising: the frequency division circuit comprises an external signal source, a square wave generator with the frequency division function, a switched capacitor integrator and a feedback circuit with the signal amplification function, wherein the external signal source is connected into the switched capacitor integrator, the square wave generator is used for generating a frequency division control clock signal to the switched capacitor integrator, and the switched capacitor integrator is output through the feedback circuit.

The switched capacitor integrator comprises 7 COMS switching tubes started by forward pulses, a sampling capacitor 104, an adjustable feedback capacitor 108 and an integrating capacitor 102, a feedback circuit comprises an operational amplifier 111, and the COMS switching tubes started by the forward pulses are all connected with a square wave generator and comprise a first COMS switching tube 103, a second COMS switching tube 105, a third COMS switching tube 106, a fourth COMS switching tube 107, a fifth COMS switching tube 109, a sixth COMS switching tube 110 and a seventh COMS switching tube 209; .

One end of the second cmos switch tube 105 is connected to an external signal source to obtain an input signal, the other end of the second cmos switch tube 105 is connected to one end of the sampling capacitor 104 and one end of the third cmos switch tube 106, and the other end of the third cmos switch tube 106 is grounded; the other end of the sampling capacitor 104 is connected with one end of the first cmos switch tube 103, one end of the fourth cmos switch tube 107 and one end of the adjustable feedback capacitor 108 in common, and the other end of the fourth cmos switch tube 107 is grounded; the other end of the first cmos switch tube 103 is connected to the inverting input terminal of the operational amplifier 111; two ends of the integrating capacitor 102 are respectively connected with the reverse input end and the output end of the operational amplifier 111, and the forward input end of the operational amplifier 111 is grounded; the other end of the adjustable feedback capacitor 108 is connected to one end of the fifth cmos switch tube 109, one end of the seventh cmos switch tube 209, and one end of the sixth cmos switch tube 110, the other end of the fifth cmos switch tube 109 and the other end of the seventh cmos switch tube 209 are both grounded, the other end of the sixth cmos switch tube 110 is connected to the output end of the operational amplifier 111, and the output end of the operational amplifier is a total output end output signal.

The square wave generator comprises an oscillator circuit, a phase non-overlapping circuit and a frequency divider which are sequentially connected and used for generating an isochronous-length biphase non-overlapping clock signal, wherein the square wave of the first phase is sampling time, and the square wave of the second phase is integration time.