阅读说明：本技术 太阳能电池的制造方法 (Method for manufacturing solar cell ) 是由 三岛良太 足立大辅 于 2018-09-28 设计创作，主要内容包括：本发明高效地制造背结型太阳能电池。是包含晶体基板(11)的太阳能电池(10)的制造方法,包括第1工序～第5工序,第2工序中,对于p型半导体层(13p),依次层叠形成第1提离层(LF1)和第2提离层(LF2),第4工序中,对于第3工序中残留的第2提离层(LF2)和没有p型半导体层(13p)的非形成区域,层叠形成n型半导体层(13n),第5工序中,使用第1蚀刻溶液,除去第1提离层(LF1)和第2提离层(LF2),也除去在第2提离层(LF2)层叠的n型半导体层(13n)。而且,相对于第1蚀刻溶液的、p型半导体层(13p)、第1提离层(LF1)和第2提离层(LF2)的蚀刻速度满足特定的关系式。(The invention efficiently manufactures a back junction type solar cell. A method for manufacturing a solar cell (10) including a crystal substrate (11) includes a 1 st step to a 5 th step, wherein in the 2 nd step, a 1 st extraction layer (LF1) and a 2 nd extraction layer (LF2) are sequentially laminated on a p-type semiconductor layer (13p), in the 4 th step, an n-type semiconductor layer (13n) is laminated on a 2 nd extraction layer (LF2) remaining in the 3 rd step and a non-formation region where the p-type semiconductor layer (13p) is not formed, and in the 5 th step, the 1 st extraction layer (LF1) and the 2 nd extraction layer (LF2) are removed using a 1 st etching solution, and the n-type semiconductor layer (13n) laminated on the 2 nd extraction layer (LF2) is also removed. The etching rates of the p-type semiconductor layer (13p), the 1 st lift-off layer (LF1), and the 2 nd lift-off layer (LF2) with respect to the 1 st etching solution satisfy a specific relational expression.)

1. A method for manufacturing a solar cell including a crystalline substrate, comprising:

a 1 st step of forming a 1 st conductivity type semiconductor layer on one main surface side of the crystal substrate,

a 2 nd step of forming a 1 st lift-off layer and a 2 nd lift-off layer comprising a silicon-based thin film material in this order on the 1 st conductivity type semiconductor layer,

a 3 rd step of removing the 2 nd lift-off layer, the 1 st lift-off layer and the 1 st conductivity type semiconductor layer from a part of the one main surface to form a non-formation region of the 1 st conductivity type semiconductor layer, while leaving the 1 st conductivity type semiconductor layer, the 1 st lift-off layer and the 2 nd lift-off layer in a remaining part of the one main surface,

a 4 th step of forming a 2 nd conductive semiconductor layer by stacking the remaining 2 nd lift-off layer and the non-formation region, and

a 5 th step of removing the 1 st and 2 nd lift-off layers and the 2 nd conductive type semiconductor layer stacked on the 2 nd lift-off layer by using a 1 st etching solution;

and, with respect to the 1 st etching solution, the etching rates of the 1 st conductivity type semiconductor layer, the 1 st lift-off layer and the 2 nd lift-off layer satisfy the following relational expressions:

the etching rate of the 1 st conductivity type semiconductor layer < the etching rate of the 2 nd lift-off layer < the etching rate of the 1 st lift-off layer … … [ equation 1 ].

2. The method for manufacturing a solar cell according to claim 1, wherein the 1 st and 2 nd extraction layers are layers mainly composed of silicon oxide, and a refractive index measured at a wavelength of 550nm satisfies the following relational expression:

the refractive index of the 2 nd lift-off layer > the refractive index of the 1 st lift-off layer … … [ relation 2 ].

3. The method for manufacturing a solar cell according to claim 1, wherein the 1 st and 2 nd lifting layers are films mainly composed of silicon oxide, and a value of x when the main component is represented by SiOx satisfies the following relational expression:

x of the 1 st lift-off layer > x … … of the 2 nd lift-off layer [ relation 3 ].

4. The method for manufacturing a solar cell according to any one of claims 1 to 3,

the crystalline substrate has a 1 st texture feature,

and a 2 nd texture structure reflecting the 1 st texture structure is included on each of the 1 st conductivity type semiconductor layer and the 2 nd conductivity type semiconductor layer formed on the one principal surface side of the crystal substrate.

5. The method of manufacturing a solar cell according to any one of claims 1 to 4, wherein a part of the one main surface of the crystalline substrate is exposed in the non-formation region.

6. The method for manufacturing a solar cell according to any one of claims 1 to 5,

in the 3 rd step, an opening is formed in the 2 nd lift-off layer, and a 2 nd etching solution is allowed to pass through the opening and adhere to the 1 st lift-off layer, thereby removing the 1 st lift-off layer.

7. The method for manufacturing a solar cell according to claim 6, wherein in the 3 rd step, the 1 st lift-off layer is removed, and the 2 nd etching solution is also allowed to adhere to the 1 st conductive type semiconductor layer, thereby removing the 1 st conductive type semiconductor layer.

8. The method for manufacturing a solar cell according to claim 6 or 7,

the concentration of the etchant contained in the 1 st etching solution is higher than the concentration of the etchant contained in the 2 nd etching solution.

Technical Field

The present invention relates to a method for manufacturing a solar cell.

Background

A general solar cell is a double-sided electrode type in which electrodes are arranged on both main surfaces (light receiving surface and back surface) of a semiconductor substrate, but recently, a back junction (back surface electrode) type solar cell in which an electrode is arranged only on the back surface has been developed as a solar cell having no shielding loss due to an electrode.

The back junction solar cell requires a semiconductor layer pattern such as a p-type semiconductor layer and an n-type semiconductor layer to be formed on the back surface with high accuracy, and the manufacturing method is more complicated than the double-sided electrode type solar cell. As a technique for simplifying the manufacturing method, a technique for forming a semiconductor layer pattern by a lift-off method is exemplified as shown in patent document 1.

That is, a technique has been developed in which silicon oxide (SiOx) or silicon carbide is used as a lift-off layer (also referred to as a mask layer or a replacement layer), and the lift-off layer is removed to remove a semiconductor layer formed thereon, thereby forming a pattern of a semiconductor layer pattern.

Disclosure of Invention

However, in order to form a semiconductor layer pattern with high accuracy by the lift-off method, it is necessary to pattern the lift-off layer itself before removing the lift-off layer, and thus the productivity is naturally low.

The present invention has been made to solve the above problems. Therefore, it is an object to efficiently produce a back junction solar cell.

The method for manufacturing a solar cell including a crystalline substrate according to the present invention includes the steps of:

a 1 st step of forming a 1 st conductivity type semiconductor layer on one main surface side of the crystal substrate,

a 2 nd step of forming a 1 st lift-off layer and a 2 nd lift-off layer comprising a silicon-based thin film material in this order on the 1 st conductivity type semiconductor layer,

a 3 rd step of removing the 2 nd lift-off layer, the 1 st lift-off layer and the 1 st conductivity type semiconductor layer from a part of the one main surface to form a non-formation region of the 1 st conductivity type semiconductor layer, while leaving the 1 st conductivity type semiconductor layer, the 1 st lift-off layer and the 2 nd lift-off layer in a remaining part of the one main surface,

a 4 th step of forming a 2 nd conductive semiconductor layer by stacking the remaining 2 nd lift-off layer and the non-formation region, and

a 5 th step of removing the 1 st and 2 nd lift-off layers and the 2 nd conductive type semiconductor layer stacked on the 2 nd lift-off layer by using a 1 st etching solution;

and, with respect to the 1 st etching solution, the etching rates of the 1 st conductivity type semiconductor layer, the 1 st lift-off layer and the 2 nd lift-off layer satisfy the following relational expressions:

the etching rate of the 1 st conductivity type semiconductor layer < the etching rate of the 2 nd lift-off layer < the etching rate of the 1 st lift-off layer … … [ equation 1 ].

According to the present invention, a back junction solar cell can be efficiently manufactured.

Drawings

Fig. 1A is a sectional view showing a method for manufacturing a solar cell.

Fig. 1B is a sectional view showing a method for manufacturing a solar cell.

Fig. 1C is a sectional view showing a method for manufacturing a solar cell.

Fig. 1D is a sectional view showing a method for manufacturing a solar cell.

Fig. 1E is a sectional view showing a method for manufacturing a solar cell.

Fig. 1F is a sectional view showing a method for manufacturing a solar cell.

Fig. 1G is a sectional view showing a method for manufacturing a solar cell.

Fig. 2 is a sectional view showing a solar cell.

Fig. 3 is a plan view showing an electrode layer of the solar cell.

Detailed Description

The following describes an embodiment of the present invention, but the present invention is not limited to this. For convenience, hatching, reference numerals, and the like may be omitted, and in such a case, reference may be made to other drawings. Further, the dimensions of the various components of the drawings are adjusted to be easily observable dimensions for convenience.

The solar cell 10 will be described in detail below. Fig. 2 is a schematic cross-sectional view showing a structure of a solar cell 10 using a silicon crystal substrate 11. The solar cell 10 has 2 main surfaces 11S (11SU,11SB), and one side of the main surface [ front main surface ]11SU of the crystal substrate 11 corresponding to one side on which light is incident is referred to as a front side, and one side of the other main surface [ back main surface ]11SB located opposite thereto is referred to as a back side. For convenience, the front side is referred to as the side receiving light more actively than the back side (light receiving side), and the back side not receiving light actively is referred to as the non-light receiving side.

The solar cell is a so-called hetero-junction solar cell, and is a back junction (back electrode type) solar cell 10 in which an electrode layer is disposed only on one side (back side) of a main surface.

The solar cell 10 includes a crystal substrate 11, an intrinsic semiconductor layer 12, a conductive semiconductor layer 13 (a p-type semiconductor layer 13p, an n-type semiconductor layer 13n), a low reflection layer 14, and an electrode layer 15 (a transparent electrode layer 17, a metal electrode layer 18).

For convenience, a part corresponding to the p-type semiconductor layer 13p or the n-type semiconductor layer 13n alone is denoted by "p"/"n" at the end of the part number. Further, since the conductivity types are different as p-type and n-type, one conductivity type may be referred to as "1 st conductivity type" and the other conductivity type may be referred to as "2 nd conductivity type".

The crystal substrate 11 may be a substrate made of single crystal silicon or a semiconductor substrate made of polycrystalline silicon. Hereinafter, a single crystal silicon substrate will be exemplified.

The conductivity type of the crystal substrate 11 may be an n-type single crystal silicon substrate containing an impurity (for example, phosphorus atom) for introducing electrons into silicon atoms, or a p-type single crystal silicon substrate having an impurity (for example, boron atom) for introducing holes into silicon atoms, and hereinafter, a so-called n-type crystal substrate having a long carrier lifetime will be described as an example.

In addition, from the viewpoint of trapping received light, the crystal substrate 11 preferably has a Texture (Texture) structure TX [ 1 st Texture structure ] formed of hills (projections) and valleys (depressions) on the surface of the 2 main surfaces 11S. The texture TX (uneven surface) is formed by anisotropic etching using the difference between the etching rate of the (100) surface and the etching rate of the (111) surface of the crystalline substrate, for example.

The thickness of the crystal substrate 11 is preferably 250 μm or less. The measurement direction in the thickness measurement is a direction perpendicular to the average surface of the crystal substrate 11 (the average surface is a surface of the entire substrate that does not depend on the texture TX). Therefore, conventionally, the vertical direction, i.e., the direction in which the thickness is measured, is referred to as the thickness direction.

When the thickness of the crystal substrate 11 is 250 μm or less, the amount of silicon used is reduced, and therefore, the silicon substrate is easily secured, and cost reduction is also achieved. A back junction structure that collects only holes and electrons generated by photoexcitation in the silicon substrate on the back side is preferable from the viewpoint of efficiently collecting each carrier.

On the other hand, when the thickness of the crystal substrate 11 is too thin, the mechanical strength is reduced, or external light (sunlight) is not sufficiently absorbed, and the short-circuit current density is reduced. Therefore, the thickness of the crystal substrate is preferably 50 μm or more, and more preferably 70 μm or more. When the texture structure is formed on the main surface of the crystal substrate, the thickness of the crystal substrate is represented by an average value of distances between straight lines connecting the opposing convex apexes of the concave-convex structures on the light receiving side and the back side.

The intrinsic semiconductor layers 12(12U,12p,12n) cover both main surfaces 11S (11SU,11SB) of the crystal substrate 11, thereby performing surface passivation while suppressing diffusion of impurities into the crystal substrate 11. The term "intrinsic (i-type)" is not limited to completely intrinsic containing no conductive impurity, and includes a substantially intrinsic layer of "weak n-type" or "weak p-type" containing a small amount of n-type impurity or p-type impurity in a range where the silicon-based layer can function as an intrinsic layer.

The material of the intrinsic semiconductor layer 12 is not particularly limited, but is preferably an amorphous silicon-based thin film, and more preferably a hydrogenated amorphous silicon-based thin film (a-Si: H thin film) containing silicon and hydrogen.

The thickness of the intrinsic semiconductor layer 12 is not particularly limited, but is preferably 2nm to 20 nm. This is because: when the thickness is 2nm or more, the effect as a passivation layer is improved, and when the thickness is 20nm or less, the deterioration of conversion characteristics due to the increase in resistance is suppressed.

The method for forming the intrinsic semiconductor layer 12 is not particularly limited, and a plasma cvd (chemical vapor deposition) method is preferable. This is to effectively passivate the substrate surface while suppressing diffusion of impurities into the single crystal silicon. In addition, in the case of the plasma CVD method, by changing the hydrogen concentration in the film of the intrinsic semiconductor layer in the film thickness direction, the carrier recovery is performed and an effective energy gap distribution can be formed.

As the conditions for forming a thin film by the plasma CVD method, for example, the substrate temperature is preferably 100 to 300 ℃, the pressure is preferably 20 to 2600Pa, and the high-frequency power density is preferably 0.003W/cm²～0.5W/cm²。

In the case where the intrinsic semiconductor layer 12 is used as a source gas for forming a thin film, SiH is preferable₄、Si₂H₆Silicon-containing gas, or their gas and H₂The gas formed by mixing.

In addition, the gas may contain CH₄、NH₃、GeH₄Gases of different elements to form silicon calcium carbide, silicon nitrite, or silicon germaniumAnd the like, to appropriately change the energy gap of the thin film.

Examples of the conductive semiconductor layer 13 include a p-type semiconductor layer 13p and an n-type semiconductor layer 13 n. As shown in fig. 2, the p-type semiconductor layer 13p is formed on a part of the back side of the crystal substrate 11 with the intrinsic semiconductor layer 12p interposed therebetween, and the n-type semiconductor layer 13n is formed on another part of the back side of the crystal substrate 11 with the intrinsic semiconductor layer 12n interposed therebetween. That is, the intrinsic semiconductor layer 12 is interposed as an intermediate layer that performs a passivation function between the p-type semiconductor layer 13p and the n-type semiconductor layer 13n and the crystal substrate 11.

The film thicknesses of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are not particularly limited, but are preferably 2nm to 20 nm. This is because the effect as a passivation layer is increased when the thickness is 2nm or more, and the reduction of the conversion characteristics due to the increase in resistance is suppressed when the thickness is 20nm or less.

The p-type semiconductor layer 13p and the n-type semiconductor layer 13n are patterned and arranged on the back side of the crystal substrate 11 so that the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are electrically separated from each other. The width of the conductive semiconductor layer 13 (for example, the length of the short side in the case of a linear pattern) is preferably 50 to 3000. mu.m, more preferably 65 to 1000. mu.m, and still more preferably 80 to 500. mu.m.

In addition, when carriers generated in the crystal substrate 11 are extracted through the conductive semiconductor layer 13, the effective mass of holes is larger than that of electrons, and therefore, from the viewpoint of reducing the transport loss, the p-type semiconductor layer 13p is preferably narrower than the n-type semiconductor layer 13 n. For example, the width of the p-type semiconductor layer 13p is preferably 0.5 to 0.9 times, and more preferably 0.6 to 0.8 times the width of the n-type semiconductor layer 13 n.

The p-type semiconductor layer 13p is a silicon layer to which a p-type doped layer (boron or the like) is added, and is preferably formed of amorphous silicon in terms of suppressing impurity diffusion and suppressing series resistance. On the other hand, the n-type semiconductor layer 13n is a silicon layer to which an n-type dopant (phosphorus or the like) is added, and is also preferably formed of an amorphous silicon layer in the same manner as the p-type semiconductor layer 13 p.

It should be noted that SiH is preferably used as the raw material gas₄Or Si₂H₆A silicon-containing gas, or a silicon-based gas and H₂The mixed gas of (1). As the dopant gas, B is preferably used for formation of the p-type semiconductor layer 13p₂H₆Etc., the formation of the n-type semiconductor layer is preferably carried out using pH₃And the like. Since the amount of impurities such as B or P may be very small, a mixed gas obtained by diluting a dopant gas with a source gas may be used.

In addition, CH may be added to adjust the energy gap of the p-type semiconductor layer 13p or the n-type semiconductor layer 13n₄、CO₂、NH₃Or GeH₄And the gas of a plurality of elements, and the p-type semiconductor layer 13p or the n-type semiconductor layer 13n are alloyed.

The low reflection layer 14 is a layer that suppresses reflection of light received by the solar cell 10. The material of the low reflection layer 14 is not particularly limited as long as it is a light-transmitting material that transmits light, and examples thereof include silicon oxide, silicon carbide, zinc oxide, and titanium oxide. The low reflection layer can be formed by, for example, coating with a resin material in which nanoparticles of an oxide such as zinc oxide or titanium oxide are dispersed.

The electrode layer 15 is formed so as to cover the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, and is electrically connected to these semiconductor layers 13. Thus, the electrode layer 15 functions as a carrier layer for introducing carriers passing through the p-type semiconductor layer 13p or the n-type semiconductor layer 13n to the outside of the solar cell 10.

The electrode layer 15 may be formed of only a metal having high conductivity, and from the viewpoint of electrical connection with the p-type semiconductor layer 13p and the n-type semiconductor layer 13n or the viewpoint of suppressing diffusion of atoms of the metal serving as an electrode material into the semiconductor layers 13p and 13n, the electrode layer 15 formed of a transparent conductive oxide is preferably provided between the metal electrode layer and the p-type semiconductor layer 13p and the n-type semiconductor layer 13 n.

Therefore, in this specification, the electrode layer 15 made of a transparent conductive oxide is referred to as a transparent electrode layer 17, and the electrode layer 15 made of a metal is referred to as a metal electrode layer 18. As shown in the plan view of the back side of the crystal substrate 11 in fig. 3, in the comb-shaped p-type semiconductor layer 13p and n-type semiconductor layer 13n, the electrode layer formed on the comb-back portion may be referred to as a bus bar portion, and the electrode layer formed on the comb-tooth portion may be referred to as a finger portion.

The material of the transparent electrode layer 17 is not particularly limited, and examples thereof include zinc oxide, indium oxide, and a transparent conductive oxide obtained by adding various metal oxides, for example, titanium oxide, tin oxide, tungsten oxide, molybdenum oxide, or the like to indium oxide in an amount of 0.5 to 15 wt%, preferably 1 to 10 wt%.

The thickness of the transparent electrode layer 17 is preferably 20nm to 200nm, and a physical vapor deposition method (PVD) such as a sputtering method, a chemical vapor deposition Method (MOCVD) in which an organic metal compound is reacted with oxygen or water, or the like is used as a method for forming a transparent electrode layer having a suitable film thickness.

The material of the metal electrode layer 18 is not particularly limited, and examples thereof include silver, copper, aluminum, and nickel.

The thickness of the metal electrode layer 18 is preferably 1 μm to 80 μm, and examples of a method for forming the metal electrode layer 18 having a suitable film thickness include a printing method in which ink jet printing or screen printing is performed on a material paste, and a plating method. However, it is not limited thereto, and in the case of using a vacuum process, an evaporation or sputtering method may be used.

The widths of the comb-teeth of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n and the width of the metal electrode layer 18 formed on these layers are preferably the same. However, the width of the metal electrode layer 18 may be made narrower than the width of the comb teeth. Further, if the leakage between the metal electrode layers 18 is prevented, the width of the metal electrode layer 18 can be made larger than the width of the comb teeth.

In the stage where the intrinsic semiconductor layer 12, the conductive semiconductor layer 13, the low reflection layer 14, and the electrode layer 15 are stacked on the crystal substrate 11, annealing is performed for the purpose of passivation of each bonding interface, suppression of generation of defect levels of the semiconductor layer 13 and the interface, reduction in resistance of the transparent electrode layer 17, and the like.

As the annealing treatment, for example, a crystal substrate on which each layer is arranged is put into an oven heated to 150 to 200 ℃. In this case, the atmosphere in the oven may be the atmosphere, but by using hydrogen or nitrogen, more effective annealing treatment can be performed. The annealing treatment may be rta (rapid Thermal annealing) treatment in which the crystal substrate on which each layer is disposed is irradiated with infrared rays using an infrared heater.

Here, a method for manufacturing the back junction solar cell 10 described above will be described in detail with reference to fig. 1A to 1G. The production method comprises the following steps 1 to 5.

First, as shown in fig. 1A, a crystal substrate 11 having a textured structure is prepared. As shown in fig. 1B, for example, an intrinsic semiconductor 12U is formed on the front main surface 11SU of the crystal substrate 11, and an anti-reflection layer 14 is formed on the intrinsic semiconductor 12U. The antireflection layer 14 is formed of a material having an optical absorption coefficient and a refractive index suitable from the viewpoint of light trapping. Examples of such a material include a silicon nitrite, a silicon oxide, and a silicon oxynitride.

Next, as shown in fig. 1C, an intrinsic semiconductor layer 12p is formed on the principal surface 11SB on the back side of the crystal substrate 11, for example, from an i-type amorphous silicon layer. Then, a p-type semiconductor layer 13p is formed on the intrinsic semiconductor layer 12 p. That is, a p-type semiconductor layer 13p is formed on the main surface 11SB side, which is one main surface of the crystal substrate 11 [ step 1 ].

Further, as shown in fig. 1C, a composite layer type lift-off layer LF [ 1 st lift-off layer LF1, 2 nd lift-off layer LF2] is formed on the p-type semiconductor layer 13 p. Specifically, the p-type semiconductor layer 13p is formed by sequentially stacking a 1 st lifting layer LF1 and a 2 nd lifting layer LF2, which are made of, for example, a silicon-based thin film material [ step 2 ]. That is, the 1 st lift-off layer LF1 is formed on the p-type semiconductor layer 13p, and the 2 nd lift-off layer LF2 is formed on the 1 st lift-off layer LF 1.

Thereafter, as shown in fig. 1D, the non-formation region NA where the p-type semiconductor layer 13p is not formed is generated by removing the 2 nd extraction layer LF2, the 1 st extraction layer LF1, and the p-type semiconductor layer 13p from a part of the main surface 11SB of the crystal substrate 11, while at least the p-type semiconductor layer 13p, the 1 st extraction layer LF1, and the 2 nd extraction layer LF2 remain in the remaining part of the main surface 11SB [ step 3 ].

Such a patterning step is realized by forming a resist film (not shown) in a part thereof by photolithography, and etching the part not covered with the resist film. In the case shown in fig. 1D, the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, the 1 st extraction layer LF1, and the 2 nd extraction layer LF2 are patterned, whereby the non-formation region NA is generated in a part of the main surface 11SB of the crystal substrate 11 (details of the non-formation region NA will be described later).

The etching solution [ 2 nd etching solution ] used in the 3 rd step includes, for example, a mixed solution of hydrofluoric acid and an oxidizing solution (for example, nitric acid fluoride), or a solution in which ozone is dissolved in hydrofluoric acid (hereinafter, ozone/hydrofluoric acid solution). In this case, the etchant that contributes to the etching of the lift-off layer LF is hydrogen fluoride.

However, the patterning is not limited to wet etching using a resist film and an etching solution. The patterning may be, for example, dry etching, or pattern printing using an etching paste or the like.

Next, as shown in fig. 1E, the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n (hereinafter, the surface LF2s and the side surfaces SE are also referred to as remaining surfaces) are formed on the intrinsic semiconductor layer 12n so as to cover the non-formation region NA of the main surface 11SB of the crystal substrate 11, the surface LF2s (see fig. 1D) of the 2 nd lift-off layer LF2, and the side surfaces SE of the remaining layers (the 2 nd lift-off layer LF2, the 1 st lift-off layer LF1, the p-type semiconductor layer 13p, and the intrinsic semiconductor layer 12p) stacked one on top of the other. That is, the n-type semiconductor layer 13n is formed by stacking the remaining second isolation layer LF2 and the non-formation region NA of the one main surface 11SB of the crystal substrate 11 [ step 4 ].

Next, as shown in fig. 1F, the composite layer type lift-off layer LF is removed by using an etching solution [ 1 st etching solution ], and the layers (intrinsic semiconductor layer 12n, n-type semiconductor layer 13n) stacked on the layer LF are also removed from the crystal substrate 11. That is, the 1 st and 2 nd lift-off layers LF1 and LF2 and the n-type semiconductor layer 13n stacked on the 2 nd lift-off layer LF2 were also removed using an etching solution [ step 5 ]. As an etching solution used in the 5 th step (patterning), hydrofluoric acid is exemplified.

Further, the etching rates of the p-type semiconductor layer 13p, the 1 st lift-off layer LF1, and the 2 nd lift-off layer LF2 with respect to the etching solution satisfy the following relational expression 1:

etching rate of the p-type semiconductor layer 13p < etching rate of the 2 nd lift-off layer LF2 < etching rate of the 1 st lift-off layer LF1 … … [ equation 1]

Thereafter, as shown in fig. 1G, a transparent electrode layer 17(17p, 17n) is formed on the back side of the crystal substrate 11, for example, by a sputtering method using a mask, so as to form the separation grooves 25. Alternatively, a film made of a transparent conductive oxide may be formed without using a mask, and then the transparent electrode layer 17(17p, 17n) may be formed by etching so that only the film made of a transparent conductive oxide on the p-type semiconductor layer 13p · n-type semiconductor layer 13n remains by photolithography.

The isolation trenches 25 are less likely to cause leakage current. On the transparent electrode layer 17, a wire-shaped metal electrode layer 18(18p, 18n) is formed using, for example, a mesh screen (not shown) having openings. In this way, the formation of each layer of the back-surface-bonded solar cell 10 is completed.

When the above method for manufacturing the solar cell 10 includes the 1 st step to the 5 th step, the following is achieved.

First, the lift-off layer LF is formed of 2 layers or more, and a layer having a high etching rate is provided on the crystal substrate 11 side (see relational expression 1). This is because the difference in etching rate in the lift-off layer LF is used to improve the etching accuracy in the 3 rd step and the 5 th step, thereby simplifying the patterning process.

In order to prevent an undesired short circuit or a leakage current in the solar cell 10, it is important to form the conductive semiconductor layer 13 or the electrode layer 15 with high etching accuracy, that is, with high accuracy. In the 3 rd step, a part of the lift-off layer LF functions as a mask for preventing adhesion of an etching solution to the p-type semiconductor layer [ 1 st conductivity type semiconductor layer ]13p in a desired portion. Therefore, the width of the patterned p-type semiconductor layer 13p depends on the width of the remaining lift-off layer LF.

Therefore, if the etching rate of the lift-off layer LF with respect to the etching solution is too high, the lift-off layer LF is likely to be etched too much in the width direction (the width is narrower than a desired width), and thus the pattern accuracy of the lift-off layer LF is lowered. Therefore, the etching rate of the lift-off layer with respect to the etching solution [ etching solution No. 2] is not good.

On the other hand, in the 5 th step, the n-type semiconductor layer [ the 2 nd conductivity type semiconductor layer ]13n is formed at a desired position (the adjacent non-molding region NA of the remaining p-type semiconductor layer 13p) in addition to covering the lift-off layer LF remaining in the 3 rd step. In order to leave the n-type semiconductor layer 13n at a desired position as a pattern and remove the n-type semiconductor layer 13n on the lift-off layer LF, it is preferable that the etching rate of the lift-off layer LF with respect to the etching solution [ 1 st etching solution ] is high. From the viewpoint of productivity, the etching rate is preferably higher because the processing time is shorter.

Thus, the lift-off layer LF is required to have opposite etching characteristics in the 3 rd step and the 5 th step, and the lift-off layer LF satisfies [ equation 1] to achieve the characteristics.

In the 3 rd step, when the relational expression 1 is satisfied, the 1 st lift-off layer LF1 is dissolved at the earliest in the non-molding region NA, and the 2 nd lift-off layer LF2 thereon is also easily detached from the crystal substrate 11 (of course, the 2 nd lift-off layer LF2 is also dissolved as well as detached), and the p-type semiconductor layer 13p exposed from the 1 st lift-off layer LF1 is also dissolved.

In the 3 rd step, for example, as shown in fig. 1D, it is assumed that even if the 1 st lift-off layer LF1 under the 2 nd lift-off layer LF2 is eroded by etching, the side surface SE of the layers (the 2 nd lift-off layer LF2, the 1 st lift-off layer LF1, the p-type semiconductor layer 13p, and the intrinsic semiconductor layer 12p) remaining by lamination remains the 1 st lift-off layer LF1 which is not eroded, and the 2 nd lift-off layer LF2 connected thereto also remains. Therefore, the remaining 2 nd separation layer LF2 functions as a separation layer LF in the 5 th step. Since the desired portion of the p-type semiconductor layer 13p needs to remain, the etching rate is lower than that of the 1 st lift-off layer LF1 and the 2 nd lift-off layer LF 2.

In the step 5, if the lower layer, i.e., the 1 st lift-off layer LF1 is completely removed, the n-type semiconductor layer 13n can be removed even if the 2 nd lift-off layer LF2 remains on the layer LF 1. That is, the 2 nd conductive type semiconductor layer LF2 and the n-type semiconductor layer 13n thereon are lifted off.

As described above, the composite layer type lift-off layer LF is a layer that needs to be removed almost completely in the 5 th step, but the etching rate is set so that the etching rate of the p-type semiconductor layer 13p < the etching rate of the 2 nd lift-off layer LF2 < the etching rate of the 1 st lift-off layer LF1 [ relational expression 1] so as not to be excessively etched in the steps up to this point (for example, the 3 rd step). In addition, in the 5 th step, since a desired portion of the p-type semiconductor layer 13p needs to remain as in the 3 rd step, the etching rate of the p-type semiconductor layer 13p is lower than the etching rates of the 1 st and 2 nd lift-off layers LF1 and LF 2.

In this way, when the p-type semiconductor layer 13p and the lift-off layer LF satisfying the relational expression 1 are used, the n-type semiconductor layer 13n is patterned without performing etching using a resist film, for example, in the 5 th step. In other words, if the above method for manufacturing the solar cell 10 is used, the patterning process is simplified, and the back junction type solar cell 10 is efficiently manufactured. Further, the pattern accuracy is also improved, and therefore, short circuit or leakage of the solar cell 10 is prevented, and high output can be obtained from the solar cell 10.

In the 2 nd step, a lift-off layer LF of a composite layer is formed on the p-type semiconductor layer 13p formed in the 1 st step. Such a lift-off layer LF is patterned (e.g., etched) in the 3 rd step, and is removed together with the n-type semiconductor layer 13n in the 5 th step. Therefore, the lift-off layer LF is preferably formed so as to include a material that dissolves in the etching solution used in the 3 rd step and the 5 th step, for example, a metal-based thin film material, a metal oxide-based thin film material, or a silicon-based thin film material. Among these materials, a silicon-based thin film material is preferable, and the lift-off layer LF is preferably a composite layer containing silicon oxide as a main component, for example.

In the case where a film containing silicon oxide as a main component is applied to the lift-off layer LF as described above, the etching solution in the 5 th step is preferably hydrofluoric acid. At this time, the etchant for etching the lift-off layer LF is hydrogen fluoride. The number of layers of the isolation layer LF may be 2 or more, but is preferably 2 from the viewpoint of productivity.

However, as one design for the etching rate to satisfy the relational expression 1, it is preferable that the main component of the p-type semiconductor layer 13p is silicon, and the main components of the 1 st and 2 nd lift-off layers LF1 and LF2 are preferably silicon oxide, but in order to control the etching rate, it is preferable to have a difference in density. This is because the lower the density, the higher the etch rate.

Further, since the refractive index of each layer changes in accordance with the density, for example, the following is preferable (the refractive index is high when the density is high, the etching rate is low, and the refractive index is low when the density is low, the etching rate is high).

That is, the 1 st and 2 nd extraction layers LF1 and LF2 are layers containing silicon oxide as a main component, and preferably satisfy the following relational expression in terms of refractive index measured at a wavelength of 550 nm.

Refractive index of the 2 nd lift-off layer LF2 > refractive index … … of the 1 st lift-off layer LF1 [ equation 2]

In the case where the lift-off layer LF is 3 layers or more, the 2 nd lift-off layer LF2 having a higher refractive index than the 1 st lift-off layer LF1 can be formed after the 1 st lift-off layer LF 1.

In addition, from the viewpoint of the composition of the extraction layer LF, in the case where the extraction layer LF is a film containing silicon oxide as a main component, the value of x when the main component is represented by SiOx preferably satisfies the following relational expression.

X of the 1 st lift-off layer LF1 > x … of the 2 nd lift-off layer LF2[ relation 3]

The value of x is preferably in the range of 0.5 to 2.2 or less, and preferably 1.2 to 2.0, and particularly preferably 1.4 to 1.9. The size relationship is preferably designed within each range.

Here, the upper limit of the value of x is larger than the ordinary stoichiometric value (x is 2.0), but this is because oxygen may be excessively contained in the process of forming the thin film of the lift layer LF.

The total film thickness of the isolation layer LF is preferably 50nm to 600nm, and particularly preferably 100nm to 450 nm. In this range, it is preferable that the 2 nd stripping layer LF2 is a film thicker than the 1 st stripping layer LF 1.

In the patterning step using a laser, although it is sometimes difficult to suppress damage caused by light scattering on the laser irradiation surface, the textured structure TX is formed also on the back side of the crystal substrate 11, thereby improving the light input efficiency.

In the 3 rd step, the intrinsic semiconductor layer 12 may be etched to expose a part of the crystal substrate 11. This may suppress a decrease in the lifetime of carriers due to photoelectric conversion.

In the 4 th step, an n-type semiconductor layer 13n is formed. The n-type semiconductor layer 13n is formed on the entire back side of the crystal substrate 11. That is, the p-type semiconductor layer 13p is formed not only on a surface of a part of the crystal substrate 11 but also on the lift-off layer LF. Note that the intrinsic semiconductor layer 12n may be formed between the crystal substrate 11 and the n-type semiconductor layer 13 n.

Before forming the intrinsic semiconductor layer 12 and the n-type semiconductor layer 13n in the 4 th step, a step of cleaning the surface of the crystal substrate 11 exposed in the 3 rd step may be provided. The cleaning step is performed, for example, with hydrofluoric acid to remove defects or impurities generated on the surface of the crystal substrate 11 in the 3 rd step.

Further, the crystal substrate 11 preferably has a texture TX, and a texture [ texture 2] having the texture TX is provided on each of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n formed on the main surface 11SB side of the crystal substrate 11.

If the semiconductor layer 13 includes a texture structure that reflects the above, the etching solution easily penetrates into the semiconductor layer 13 due to the irregularities, and therefore, these layers 13 are easily removed, that is, patterning is easily performed.

In fig. 1D, a part of the main surface 11SB of the crystal substrate 11 is exposed in the non-formation region NA, but the present invention is not limited thereto, and the intrinsic semiconductor layer 12p may remain on a part of the main surface 11 SB. The p-type semiconductor layer 13p may be removed mainly from a part of the main surface 11SB of the crystal substrate 11, and a region where the layer 13p is not present (i.e., disappears) may be the non-formation region NA.

In this way, the number of steps for forming the intrinsic semiconductor layer 12n before the n-type semiconductor layer 13n is stacked can be reduced with respect to the remaining 2 nd lift-off layer LF2 and the non-formation region NA.

In the 3 rd step, an opening may be formed in the 2 nd lift-off layer LF2, and the etching solution [ the 2 nd etching solution ] may be allowed to adhere to the 1 st lift-off layer LF1 through the opening to remove the 1 st lift-off layer LF1, or in the 3 rd step, the 1 st lift-off layer LF1 may be removed as described above, and the etching solution may be allowed to adhere to the p-type semiconductor layer 13p to remove the p-type semiconductor layer 13 p. Examples of a method for forming the opening include using a resist having an opening by photolithography, and removing or cracking the opening by a laser or the like.

In this way, the etching solution reliably adheres to the 2 nd lift-off layer LF2 and further to the 1 st lift-off layer LF1 through the opening, and the entire lift-off layer LF is effectively removed. In addition, by removing the lift-off layer LF, the etching solution is reliably attached to and removed from the p-type semiconductor layer 13p covered with the layer LF. That is, the dissolution residue of the 2 nd extraction layer LF2, the 1 st extraction layer LF1, and the p-type semiconductor layer 13p can be suppressed.

The concentration of the etchant contained in the etching solution [ 1 st etching solution ] used in the 5 th step is preferably higher than the concentration of the etchant contained in the etching solution [ 2 nd etching solution ] used in the 3 rd step.

In this way, the desired patterning can be easily performed by leaving a part of the lift-off layer LF in the 3 rd step and removing the lift-off layer LF in the 5 th step.

The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified in the scope shown in the claims are also included in the technical scope of the present invention.

For example, the semiconductor layer used in the step 1 is a p-type semiconductor layer, but the semiconductor layer is not limited thereto and may be an n-type semiconductor layer. The conductivity type of the crystal substrate is not particularly limited, and may be p-type or n-type.