阅读说明：本技术 在n型接触之间具有改进的电气隔离的光子集成电路 (Photonic integrated circuit with improved electrical isolation between N-type contacts ) 是由 爱德斯 K·彼得 D·鲍德韦因 于 2020-02-13 设计创作，主要内容包括：本公开涉及一种光子集成电路(1),包括装配在具有外延层堆叠(2)的半导体晶圆上的第一光电器件(10)和第二光电器件(12),外延层堆叠(2)包括设置有至少一个选择性p型掺杂管状区域(6)的n型基于磷化铟的接触层(3),区域(6)用于在第一光电器件和第二光电器件的各自的n型接触区域之间提供电气屏障,第一光电器件和第二光电器件通过装配在包含磷化砷铟镓的非故意掺杂波导层(9)中的无源光波导(14)光学互连,非故意掺杂波导层被布置在n型掺杂接触层的顶部上,至少一个选择性p型掺杂管状区域的第一部分(15)布置在第一光电器件与第二光电器件之间的无源光波导的下方。本公开还涉及一种包括该光子集成电路的光电系统(33)。(The present disclosure relates to a photonic integrated circuit (1) comprising a first optoelectronic device (10) and a second optoelectronic device (12) mounted on a semiconductor wafer having an epitaxial layer stack (2), the epitaxial layer stack (2) comprising an n-type indium phosphide-based contact layer (3) provided with at least one selectively p-type doped tubular region (6), the region (6) being for providing an electrical barrier between respective n-type contact regions of the first and second optoelectronic devices, the first and second optoelectronic devices being optically interconnected by a passive optical waveguide (14) mounted in an unintentionally doped waveguide layer (9) comprising indium gallium arsenide phosphide, the unintentionally doped waveguide layer being arranged on top of the n-type doped contact layer, a first portion (15) of the at least one selectively p-type doped tubular region being arranged below the passive optical waveguide between the first and second optoelectronic devices. The disclosure also relates to an optoelectronic system (33) comprising the photonic integrated circuit.)

1. A photonic integrated circuit (1) comprising:

semiconductor wafer having an epitaxial layer stack (2), the epitaxial layer stack (2) comprising:

an n-doped contact layer (3) comprising indium phosphide or an unintentionally doped layer (4) comprising indium phosphide, the unintentionally doped layer comprising at least two selective n-doped contact regions (5a, 5b), wherein the n-doped contact layer (3) or the unintentionally doped layer (4) outside the at least two selective n-doped contact regions (5a, 5b) comprises a first selective p-doped tubular region (6), which first selective p-doped tubular region (6) is configured and arranged to provide a first electrical barrier between a first region (7) of the n-doped contact layer (3) surrounded by the first selective p-doped tubular region (6) and a second region (8) of the n-doped contact layer (3) arranged outside the first selective p-doped tubular region (6), or providing a first electrical barrier between a first selectively n-doped contact region (5a) of the unintentionally doped layer (4) surrounded by the first selectively p-doped tubular region (6) and a second selectively n-doped contact region (5b) of the unintentionally doped layer (4) arranged outside the first selectively p-doped tubular region (6); and

an unintentionally doped waveguide layer (9) comprising indium gallium arsenide phosphide, said unintentionally doped waveguide layer (9) being arranged on top of said n-type doped contact layer (3) or said unintentionally doped layer (4);

a first optoelectronic device (10) arranged in the first region (7) of the n-doped contact layer (3) surrounded by the first selectively p-doped tubular region (6) or in the first selectively n-doped contact region (5a) of the unintentionally doped layer (4) surrounded by the first selectively p-doped tubular region (6), the first optoelectronic device (10) comprising a first n-ohmic metal contact (11), the first n-ohmic metal contact (11) being arranged on the n-doped contact layer (3) at a first location within the first region (7) or on the first selectively n-doped contact region (5 a);

-a second optoelectronic device (12) arranged in said second region (8) of said n-doped contact layer (3) outside said first selective p-doped tubular region (6) or in said second selective n-doped contact region (5b) of said unintentional layer (4) outside said first selective p-doped tubular region (6), said second optoelectronic device (12) comprising a second n-type ohmic metal contact (13), said second n-type ohmic metal contact (13) being arranged on said n-doped contact layer (3) at a second location within said second region (8) or on said second selective n-type doped contact region (5 b); and

a passive optical waveguide (14) comprising the unintentionally doped waveguide layer (9), the passive optical waveguide (14) being arranged to optically interconnect the first optoelectronic device (10) with the second optoelectronic device (12), wherein a first portion (15) of the first selectively p-doped tubular region (6) is arranged below the passive optical waveguide (14) between the first optoelectronic device (10) and the second optoelectronic device (12).

2. The photonic integrated circuit (1) according to claim 1, wherein at least the first portion (15) of the first selectively p-doped tubular region (6) arranged below the unintentionally doped waveguide layer (9) of the passive optical waveguide (14) has a thickness in its radial direction of between 1 μ ι η -100 μ ι η, preferably between 2 μ ι η -10 μ ι η.

3. The photonic integrated circuit (1) according to claim 1 or 2, wherein the first selectively p-type doped tubular region (6) comprises zinc as a p-type dopant.

4. The photonic integrated circuit (1) of claim 1, wherein the first selectively p-doped tubular region (6) comprises an active p-type doping concentration of 1 × 10¹⁶cm^-3–2×10¹⁸cm^-3Preferably less than or equal to 1 × 10¹⁷cm^-3。

5. The photonic integrated circuit (1) according to claim 1, the photonic integrated circuit (1) comprising a substrate (16), the n-doped contact layer (3) or the unintentionally doped layer (4) of the epitaxial layer stack (2) being arranged on top of the substrate (16), the substrate (16) comprising one of semi-insulating indium phosphide, p-doped indium phosphide and n-doped indium phosphide, the substrate (16) being compensated with iron atoms to provide at least a semi-insulating surface layer on top of which the n-doped contact layer (3) or the unintentionally doped layer (4) is arranged, wherein the first selectively p-doped tubular region (6) is arranged to extend axially along its axis at least from a first boundary (17) between the substrate (16) and the n-doped contact layer (3) or the unintentionally doped layer (4) to the n-doped contact layer (3) or the unintentionally doped layer (4) A second boundary (18) between the unintentionally doped layer (4) and the unintentionally doped waveguide layer (9).

6. The photonic integrated circuit (1) according to claim 1, wherein the first selectively p-doped tubular region (6) is provided with a first p-ohmic metal contact (19).

7. The photonic integrated circuit (1) according to claim 6, wherein a short circuit is arranged between the first p-type ohmic metal contact (19) and one of the first n-type ohmic metal contact (11) of the first optoelectronic device (10) and the second n-type ohmic metal contact (13) of the second optoelectronic device (12).

8. The photonic integrated circuit (1) according to claim 1, wherein the n-doped contact layer (3) or the unintentionally doped layer (4) outside the at least two selectively n-doped contact regions (5a, 5b) comprises a second selectively p-doped tubular region (20), the second selectively p-doped tubular region (20) being arranged at a preset distance from the first selectively p-doped tubular region (6) and being configured to surround the first selectively p-doped tubular region (6) to electrically connect the first region (7) of the n-doped contact layer (3) surrounded by both the first selectively p-doped tubular region (6) and the second selectively p-doped tubular region (20) with the second region (7) arranged outside both the first selectively p-doped tubular region (6) and the second selectively p-doped tubular region (20) Or between the first selective n-doped contact region (5a) of the unintentionally doped layer (4) surrounded by both the first selective p-doped tubular region (6) and the second selective p-doped tubular region (20) and the second selective n-doped contact region (5b) of the unintentionally doped layer (4) arranged outside both the first selective p-doped tubular region (6) and the second selective p-doped tubular region (20);

wherein a second portion (21) of the second selectively p-doped tubular region (20) is arranged below the passive optical waveguide (14) between the first (10) and second (12) optoelectronic devices, wherein at least one of the first (6) and second (20) selectively p-doped tubular regions comprises zinc as a p-type dopant, and wherein each of the first (6) and second (20) selectively p-doped tubular regions comprises an active p-type doping concentration of 1 × 10¹⁶cm^-3–2×10¹⁸cm^-3Preferably less than or equal to 1 × 10¹⁷cm^-3。

9. The photonic integrated circuit (1) according to claim 8, wherein at least the first portion (15) of the first selectively p-doped tubular region (6) and at least the second portion (21) of the second selectively p-doped tubular region (20) are arranged below the unintentionally doped waveguide layer (9) of the passive optical waveguide (14), each of the first portion (15) and the second portion (21) having a thickness in a radial direction thereof of between 1 μ ι η -100 μ ι η, preferably between 2 μ ι η -10 μ ι η.

10. The photonic integrated circuit (1) according to claim 8 or 9, the photonic integrated circuit (1) comprising a substrate (16), the n-doped contact layer (3) or the unintentionally doped layer (4) of the epitaxial layer stack (2) being arranged on top of the substrate (16), the substrate (16) comprising one of semi-insulating indium phosphide, p-doped indium phosphide and n-doped indium phosphide, the substrate (16) being compensated using iron atoms to provide at least a semi-insulating surface layer on top of which the n-doped contact layer (3) or the unintentionally doped layer (4) is arranged, wherein at least one of the first selectively p-doped tubular region (6) and the second selectively p-doped tubular region (20) is arranged at least from the substrate (16) to a second layer between the n-doped contact layer (3) or the unintentionally doped layer (4) A boundary (17) extends in its axial direction to a second boundary (18) between the n-doped contact layer (3) or the unintentionally doped layer (4) and the unintentionally doped waveguide layer (9).

11. The photonic integrated circuit (1) according to claim 8, wherein the first selectively p-doped tubular region (6) is provided with a first p-ohmic metal contact (19) and/or the second selectively p-doped tubular region (20) is provided with a second p-ohmic metal contact (22).

12. The photonic integrated circuit (1) according to claim 11, wherein a third region (23) of the n-doped contact layer (3) arranged between the first selectively p-doped tubular region (6) and the second selectively p-doped tubular region (20), or a third selectively n-doped contact region of the unintentionally doped layer (4) arranged between the first selectively p-doped tubular region (6) and the second selectively p-doped tubular region (20) is provided with a third n-ohmic metal contact (25), wherein a short circuit is arranged between the first p-type ohmic metal contact (19) and one of the first n-type ohmic metal contact (11) of the first optoelectronic device (10), the second n-type ohmic metal contact (13) of the second optoelectronic device (12), and the third n-type ohmic metal contact (25); and/or arranging a short circuit between one of said first n-type ohmic metal contact (11) of said first opto-electronic device (10), said second n-type ohmic metal contact (13) of said second opto-electronic device (12) and said third n-type ohmic metal contact (25) and said second p-type ohmic metal contact (22).

13. The photonic integrated circuit (1) according to claim 1, wherein the epitaxial layer stack (2) further comprises:

a p-type doped cladding layer (26) comprising indium phosphide, the p-type doped cladding layer (26) being arranged over the top of the unintentionally doped waveguide layer (9); and

a p-doped contact layer (27) comprising indium gallium arsenide, the p-doped contact layer (27) being arranged on top of the p-doped cladding layer (26), the p-doped contact layer (27) having a higher active p-type doping concentration than the p-doped cladding layer (26); and

wherein the p-doped contact layer (27) is provided with a recess (28), which recess (28) is configured and arranged such that the p-doped contact layer (27) is interrupted, and the p-doped contact layer (27) is provided with a first p-doped contact region (29) and a second p-doped contact region (30), the width of the recess (28) seen in a direction parallel to a third boundary (31) between the p-doped contact layer (27) and the p-doped cladding layer (26) being in the range of 5 μm to 200 μm, preferably 30 μm.

14. The photonic integrated circuit according to claim 13, wherein the groove (28) is configured and arranged to extend into the p-doped cladding layer (26) until a predetermined distance from a fourth boundary (32) between the p-doped cladding layer (26) and the unintentionally doped waveguide layer (9), the predetermined distance from the fourth boundary being in the range of 0.5 μ ι η to 5 μ ι η, preferably in the range of 1 μ ι η to 2 μ ι η.

15. An optoelectronic system (33) comprising a photonic integrated circuit (1) according to claim 1.

Technical Field

The present disclosure relates to a photonic integrated circuit having improved electrical isolation between an n-type contact of a first optoelectronic device and an n-type contact of a second optoelectronic device of the photonic integrated circuit. The present disclosure also relates to an optoelectronic system comprising the photonic integrated circuit.

Background

Modern Photonic Integrated Circuits (PICs) are becoming more and more complex due to the increasing number of optoelectronic functions integrated on a single photonic chip. The most common technology platform for PIC uses semiconductor wafers containing indium phosphide (InP) based materials. Indium phosphide-based technology offers the possibility of integrating all active elements (e.g., light emitting optoelectronic devices and/or light absorbing optoelectronic devices) as well as passive elements (e.g., light guiding optoelectronic devices and/or light converting optoelectronic devices) into one PIC on a single photonic chip.

Exemplary PICs known in the art include, for example, light emitting elements, light absorbing elements, and light converting elements optically interconnected by passive optical waveguides. Each of the light emitting element, the light absorbing element and the light converting element requires an n-type ohmic metal contact and/or a p-type ohmic metal contact to their respective n-type doped contact region or p-type doped contact region. A disadvantage of such existing PICs in the art is that the reduction of the PIC footprint (footprint) is limited due to insufficient electrical isolation between the n-doped contact regions of the different light emitting, light absorbing and light converting elements when these elements are arranged too close to each other. This is due to the fact that: while it is possible to etch away excess n-doped InP-based semiconductor material between the various optoelectronic devices to increase the electrical isolation between their respective n-doped contact regions, the n-doped InP-based semiconductor material underlying a passive optical waveguide disposed to optically interconnect the various optoelectronic devices cannot be removed. Another disadvantage of such prior PICs in the art is that excess n-doped InP-based semiconductor material between individual optoelectronic devices is etched away in order to increase the electrical isolation between the respective n-doped contact regions of the individual optoelectronic devices, but the etching step described above adds additional topology to the surface of the photonic chip that includes the PIC. This additional surface topology can negatively impact subsequent photolithography steps during, for example, photonic chip processing.

Based on the foregoing, there is a need to provide a PIC with improved electrical isolation between n-type doped contact regions of different optoelectronic devices of the PIC that are optically interconnected by a passive optical waveguide without interfering with the optical light path provided by the passive optical waveguide, so that the footprint of the photonic chip can be further reduced.

Disclosure of Invention

It is an object of the present disclosure to provide a Photonic Integrated Circuit (PIC) that may forego or at least reduce at least one of the above disadvantages and/or other disadvantages associated with PICs existing in the art.

It is another object of the present disclosure to provide an optoelectronic system including the PIC.

Aspects of the present disclosure are set forth in the accompanying independent and dependent claims. Features from dependent aspects may be combined with features from independent aspects as appropriate and not merely as explicitly set out. Furthermore, all the features may be replaced by other technically equivalent features.

At least one of the above objects is achieved by a Photonic Integrated Circuit (PIC) comprising:

a semiconductor wafer having an epitaxial layer stack, the epitaxial layer stack comprising:

an n-doped contact layer comprising indium phosphide or an unintentionally doped layer comprising indium phosphide, the unintentionally doped layer comprising at least two selective n-doped contact regions, wherein the n-doped contact layer or the unintentionally doped layer outside the at least two selective n-doped contact regions comprises a first selective p-doped tubular region configured and arranged to provide a first electrical barrier between a first region of the n-doped contact layer surrounded by the first selective p-doped tubular region and a second region of the n-doped contact layer arranged outside the first selective p-doped tubular region, or a first selective n-doped contact region of the unintentionally doped layer surrounded by the first selective p-doped tubular region and the unintentionally doped layer arranged outside the first selective p-doped tubular region Providing a first electrical barrier between the second selectively n-doped contact regions of the impurity layer; and

an unintentionally doped waveguide layer comprising arsenic indium gallium phosphide, the unintentionally doped waveguide layer being disposed over the n-type doped contact layer or the top of the unintentionally doped layer;

a first optoelectronic device disposed in the first region of the n-doped contact layer surrounded by the first selectively p-doped tubular region or disposed in the first selectively n-doped contact region of the unintentionally doped layer surrounded by the first selectively p-doped tubular region, the first optoelectronic device comprising a first n-type ohmic metal contact disposed at a first location on the n-doped contact layer within the first region or disposed at a first location on the first selectively n-doped contact region;

a second optoelectronic device disposed in the second region of the n-doped contact layer outside the first selectively p-doped tubular region or disposed in the second selectively n-doped contact region of the unintentionally doped layer outside the first selectively p-doped tubular region, the second optoelectronic device comprising a second n-type ohmic metal contact disposed at a second location on the n-doped contact layer within the second region or disposed at a second location on the second selectively n-doped contact region; and

a passive optical waveguide comprising the unintentionally doped waveguide layer, the passive optical waveguide being arranged to optically interconnect the first optoelectronic device with the second optoelectronic device, wherein a first portion of the first selectively p-doped tubular region is arranged below the passive optical waveguide between the first and second optoelectronic devices.

It will be appreciated by those skilled in the art that an n-doped contact layer comprising indium phosphide or an unintentionally doped layer comprising indium phosphide of a PIC according to the present disclosure is provided with an n-p-n barrier comprising a first selectively p-doped tubular region, the first selectively p-doped tubular region being configured and arranged to prevent charge carriers from being leaked between an n-doped contact region comprising a first n-type ohmic metal contact of the first optoelectronic device and an n-doped contact region comprising a second n-type ohmic metal contact of the second optoelectronic device via the n-doped InP-based contact layer or a portion of the unintentionally doped InP-based layer arranged below the passive optical waveguide, wherein the passive optical waveguide is disposed between the first optoelectronic device and the second optoelectronic device to optically interconnect the first optoelectronic device and the second optoelectronic device. As such, PICs according to the present disclosure have the beneficial effect of improved so-called electrical n-isolation between n-type doped contact regions of different optoelectronic devices provided with n-type ohmic metal contacts. Further, the first portion of the first selectively p-doped tubular region is configured to minimize optical loss in the passive optical waveguide optically interconnecting the first optoelectronic device with the second optoelectronic device.

Based on the foregoing, those skilled in the art will recognize that optoelectronic devices of PICs according to the present disclosure may be arranged closer to one another than optoelectronic devices of PICs existing in the art. Thus, the footprint of a photonic chip including a PIC according to the present disclosure may be reduced as compared to a photonic chip including a PIC existing in the art. Furthermore, by providing a first selectively p-type doped tubular region, no undesired additional topology is added to the surface of the photonic chip including the PIC.

In an embodiment of the photonic integrated circuit according to the present disclosure, at least the first portion of the first selectively p-doped tubular region arranged below the unintentionally doped waveguide layer of the passive optical waveguide has a thickness in its radial direction comprised between 1 μm and 100 μm, preferably between 2 μm and 10 μm. It is known in the art that p-doped regions should be far from the passive optical waveguide, since they cause additional optical loss. However, it has surprisingly been found that by keeping said thickness of the first portion of the first selectively p-doped tubular region between 1 μm and 100 μm, preferably between 2 μm and 10 μm, the additional optical losses can be kept to a minimum.

In one embodiment of a photonic integrated circuit according to the present disclosure, the first selectively p-type doped tubular region comprises zinc as a p-type dopant. Zinc is the most commonly used p-type dopant in InP based semiconductor materials. Zinc is typically added to the MOCVD process to grow p-type doped InP based layers. It is known in the art that zinc can diffuse through InP based materials at temperatures close to 500-600 c, or at typical growth temperatures of 500-600 c. Therefore, zinc diffusion may also be used after the growth of the InP-based layer is completed. Zinc diffusion is a well known process step in the art for the manufacture of photodetectors. The diffusion depth can be well controlled and a high doping concentration can be achieved.

In one embodiment of a photonic integrated circuit according to the present disclosure, the first selectively p-doped tubular region comprises an active p-type doping concentration of 1 × 10¹⁶cm^-3–2×10¹⁸cm^-3Preferably less than or equal to 1 × 10¹⁷cm^-3To obtain optimal electrical isolation performance, the activated p-type doping concentration is maintained at 1 × 10¹⁶cm^-3–2×10¹⁸cm^-3Preferably less than or equal to 1 × 10¹⁷cm^-3However, in the case of a semiconductor wafer having an epitaxial layer stack including an n-doped InP-based contact layer in accordance with the PIC of the present disclosure, the p-type doping concentration must compensate for the initial n-type doping concentration to create the first selectively p-doped tubular region¹⁸cm^-3To achieve a low resistance n-type ohmic contact. Therefore, achieving a reproducible low p-type doping concentration while compensating for the high n-type doping concentration can be a problem.

Alternatively, a semiconductor wafer of a PIC according to the present disclosure may have an epitaxial layer stack comprising an unintentionally doped InP-based layer comprising at least two selective n-doped contact regions obtained by ion implantation of n-type dopants. In this case, it is not soThe p-type doping concentration in the intentionally doped InP-based layer need not be as high as in the case of an n-doped InP-based layer, since the p-type dopant need only compensate for any unintentional n-type dopants that may have been introduced during the growth of the unintentionally doped InP-based layer¹⁷cm^-3。

In one embodiment of a photonic integrated circuit according to the present disclosure, the photonic integrated circuit includes a substrate, the n-doped contact layer or the unintentionally doped layer of the epitaxial layer stack is arranged on top of the substrate, the substrate comprising one of semi-insulating indium phosphide, p-type doped indium phosphide and n-type doped indium phosphide, the substrate being compensated with iron atoms to provide at least a semi-insulating surface layer, -said n-doped contact layer or said unintentionally doped layer is arranged on top of said semi-insulating surface layer, wherein the first selectively p-doped tubular region is arranged to extend at least from a first boundary between the substrate and the n-doped contact layer or the unintentionally doped layer along its axial direction to a second boundary between the n-doped contact layer or the unintentionally doped layer and the unintentionally doped waveguide layer. Depending on the penetration depth of the selected p-type dopant, the first selectively p-type doped tubular region may be configured and arranged to start at the first boundary or at a position in the substrate a predetermined distance beyond the first boundary and end at the second boundary.

In one embodiment of a photonic integrated circuit according to the present disclosure, the first selectively p-doped tubular region is provided with a first p-ohmic metal contact. Thus, it is possible to electrically contact the first selectively p-doped tubular region, for example for biasing purposes.

In one embodiment of a photonic integrated circuit according to the present disclosure, a short circuit is arranged between the first p-type ohmic metal contact and one of the first n-type ohmic metal contact of the first optoelectronic device and the second n-type ohmic metal contact of the second optoelectronic device. Thus, the n-isolation can be electrically controlled when the PIC is operating. It will be appreciated by those skilled in the art that a metal layer in the back-end metal layer may be used to establish a short between one of the first and second n-type ohmic metal contacts and the first p-type ohmic metal contact. The n-isolation is floating (float) in the absence of a short between one of the first and second n-type ohmic metal contacts and the first p-type ohmic metal contact.

In an embodiment of the photonic integrated circuit according to the present disclosure, the n-doped contact layer or the unintentionally doped layer outside the at least two selectively n-doped contact regions comprises a second selectively p-doped tubular region arranged at a preset distance from the first selectively p-doped tubular region and configured to surround the first selectively p-doped tubular region to provide a second electrical barrier between the first region of the n-doped contact layer surrounded by both the first and second selectively p-doped tubular regions and the second region of the n-doped contact layer arranged outside both the first and second selectively p-doped tubular regions, or providing a second electrical barrier between the first selective n-doped contact region of the unintentionally doped layer surrounded by both the first and second selective p-doped tubular regions and the second selective n-doped contact region of the unintentionally doped layer arranged outside both the first and second selective p-doped tubular regions;

wherein a second portion of the second selectively p-type doped tubular region is disposed below the passive optical waveguide between the first and second optoelectronic devices, wherein at least one of the first and second selectively p-type doped tubular regions comprises zinc as a p-type dopant, andwherein each of the first and second selectively p-type doped tubular regions comprises an activated p-type doping concentration at 1 × 10¹⁶cm^-3–2×10¹⁸cm^-3Preferably less than or equal to 1 × 10¹⁷cm^-3。

By providing said second selectively p-doped tubular region, an additional electrical barrier may be achieved and, thus, a further improved n-isolation may be achieved between an n-doped contact region of a first opto-electronic device and an n-doped contact region of a second opto-electronic device, wherein both the first opto-electronic device and the second opto-electronic device are provided with an n-ohmic metal contact.

In an embodiment of the photonic integrated circuit according to the present disclosure, at least the first portion of the first selectively p-doped tubular region and at least the second portion of the second selectively p-doped tubular region are arranged below an unintentionally doped waveguide layer of the passive optical waveguide, each of the first portion and the second portion having a thickness in a radial direction thereof between 1 μm-100 μm, preferably between 2 μm-10 μm. It has surprisingly been found that by keeping the thickness of at least the first part of the first selectively p-doped tubular region and at least the second part of the second selectively p-doped tubular region between 1 μm and 100 μm, preferably between 2 μm and 10 μm, the additional optical losses in the passive optical waveguide can be kept to a minimum.

In one embodiment of a photonic integrated circuit according to the present disclosure, the photonic integrated circuit includes a substrate, the n-doped contact layer or the unintentionally doped layer of the epitaxial layer stack is arranged on top of the substrate, the substrate comprising one of semi-insulating indium phosphide, p-type doped indium phosphide and n-type doped indium phosphide, the substrate being compensated with iron atoms to provide at least a semi-insulating surface layer, -said n-doped contact layer or said unintentionally doped layer is arranged on top of said semi-insulating surface layer, wherein at least one of the first selectively p-doped tubular region and the second selectively p-doped tubular region is arranged to extend at least from a first boundary between the substrate and the n-doped contact layer or the unintentionally doped layer axially therealong to a second boundary between the n-doped contact layer or the unintentionally doped layer and the unintentionally doped waveguide layer. Depending on the penetration depth of the selected p-type dopant, at least one of the first selectively p-type doped tubular region and the second selectively p-type doped tubular region may be configured and arranged to start at the first boundary or at a location in the substrate that exceeds the first boundary by a predetermined distance and to end at the second boundary.

In an embodiment of the photonic integrated circuit according to the present disclosure, the first selectively p-doped tubular region is provided with a first p-ohmic metal contact and/or the second selectively p-doped tubular region is provided with a second p-ohmic metal contact. In this way, it is possible to electrically contact at least one of the first and second selectively p-type doped tubular regions, for example for biasing purposes.

In an embodiment of the photonic integrated circuit according to the present disclosure, a third region of the n-doped contact layer arranged between the first and second selective p-doped tubular regions or a third selective n-doped contact region of the unintentional layer arranged between the first and second selective p-doped tubular regions is provided with a third n-ohmic metal contact, wherein a short circuit is arranged between the first p-ohmic metal contact and one of the first, second and third n-ohmic metal contacts of the first and second optoelectronic devices; and/or arranging a short circuit between the second p-type ohmic metal contact and one of the first n-type ohmic metal contact of the first optoelectronic device, the second n-type ohmic metal contact of the second optoelectronic device, and the third n-type ohmic metal contact.

In this way, the n-isolation provided by the first selectively p-doped tubular region and/or the n-isolation provided by the second selectively p-doped tubular region may be electrically controlled when the PIC is in operation. It will be appreciated by those skilled in the art that at least one of the back end metal layers may be used to establish a corresponding short. The n-isolation provided by the first selectively p-doped tubular region is floating in the absence of a short circuit between one of the first, second and third n-type ohmic metal contacts and the first p-type ohmic metal contact. Similarly, if there is no short circuit between one of the first, second and third n-type ohmic metal contacts and the second p-type ohmic metal contact, the n-isolation provided by the second selectively p-type doped tubular region is floating. Thus, each n-isolation can be electrically controlled, or floating.

In an embodiment of the photonic integrated circuit according to the present disclosure, the epitaxial layer stack further comprises:

a p-type doped cladding layer comprising indium phosphide, the p-type doped cladding layer disposed over a top portion of the unintentionally doped waveguide layer; and

a p-doped contact layer comprising indium gallium arsenide, the p-doped contact layer being disposed on top of the p-doped cladding layer, the p-doped contact layer having a higher active p-type doping concentration than the p-doped cladding layer; and

wherein the p-doped contact layer is provided with a recess configured and arranged such that the p-doped contact layer is interrupted, and the p-doped contact layer is provided with a first p-doped contact region and a second p-doped contact region, the width of the recess, seen in a direction parallel to a third boundary between the p-doped contact layer and the p-doped cladding layer, being in the range of 5 μm to 200 μm, preferably 30 μm. The recess may be provided by etching away a predetermined portion of the p-type doped contact layer having a width in the above range. The p-doped contact layer within the predetermined portion is etched away to a depth, as seen in a direction transverse to the width of the predetermined portion, which corresponds to the entire thickness of the p-doped contact layer. In this way, a PIC according to the present disclosure is provided with so-called electrical p-isolation, i.e. electrical isolation between p-type doped contact regions, and/or electrical isolation between different optoelectronic devices of the PIC that are provided with p-type ohmic metal contacts.

In an embodiment of the photonic integrated circuit according to the present disclosure, the groove is configured and arranged to extend into the p-doped cladding layer until a predetermined distance from a fourth boundary between the p-doped cladding layer and the unintentionally doped waveguide layer, the predetermined distance from the fourth boundary being in the range of 0.5 μm to 5 μm, preferably in the range of 1 μm to 2 μm. In this case, the recess is provided by etching away a predetermined portion having a width in the range of 5 μm to 200 μm, preferably 30 μm, comprising the complete p-doped contact layer and a part of the p-doped cladding layer, as seen in a direction transverse to the width of the predetermined portion, up to said predetermined distance from said fourth boundary. In this way, a PIC according to the present disclosure may be provided with improved electrical p-isolation.

According to another aspect of the present disclosure, there is provided an optoelectronic assembly comprising a photonic integrated circuit according to the present disclosure. Examples of PICs according to the present disclosure are balanced photodetectors, laser MZI modulators. These PICs may be advantageously implemented in optoelectronic systems such as tunable optical transceivers or optical coherent transceivers.

Drawings

Other features and advantages of the present disclosure will become more apparent from the description of exemplary and non-limiting embodiments of a Photonic Integrated Circuit (PIC) and a optoelectronic system including the PIC in the present disclosure.

Those skilled in the art will appreciate that the described embodiments of the PIC and optoelectronic system are merely exemplary in nature and should not be construed as limiting the scope in any way. It will be appreciated by those skilled in the art that alternative and equivalent embodiments of the PIC and optoelectronic system may be devised and simplified to practice without departing from the scope of the present disclosure.

Reference will be made to the figures on the drawing sheet. The figures are schematic in nature and, thus, are not necessarily drawn to scale. Further, the same reference numerals denote the same or similar parts. In the drawings:

fig. 1 shows a schematic cross-section of a typical waveguide structure for an indium phosphide (InP) -based Photonic Integrated Circuit (PIC) as is known in the art.

Fig. 2 shows a schematic top view of a PIC as known in the art, wherein a Distributed Bragg Reflector (DBR) laser, a mach-zehnder modulator (MZM), and an output monitoring Photodiode (PD) are operatively connected to each other by a passive optical waveguide. The DBR laser, MZM and output monitoring PD comprise a waveguide structure having a cross-section as shown in fig. 1.

Fig. 3 shows a schematic perspective view of a first exemplary, non-limiting embodiment of a PIC according to the present disclosure.

Fig. 4 shows a schematic top view of a second exemplary, non-limiting embodiment of a PIC according to the present disclosure in which the DBR laser, MZM and output monitoring PD are operatively connected to each other through a passive optical waveguide.

Fig. 5A shows a schematic cross-sectional view of a first exemplary, non-limiting embodiment of an epitaxial layer stack of a portion of a PIC according to the present disclosure.

Fig. 5B shows a schematic cross-sectional view of a second exemplary, non-limiting embodiment of an epitaxial layer stack of a portion of a PIC according to the present disclosure.

Fig. 6 shows a schematic perspective view of a third exemplary, non-limiting embodiment of a PIC according to the present disclosure.

Fig. 7 shows a schematic cross-sectional view of a third exemplary, non-limiting embodiment of an epitaxial layer stack of a portion of a PIC according to the present disclosure.

Fig. 8A-8D show schematic cross-sectional views of a first exemplary, non-limiting embodiment of a semiconductor wafer fabricated using a first exemplary, non-limiting embodiment of a method according to the present disclosure.

Fig. 9A-9E show schematic cross-sectional views of a second exemplary, non-limiting embodiment of a semiconductor wafer fabricated using a second exemplary, non-limiting embodiment of a method according to the present disclosure. And the number of the first and second groups,

fig. 10 shows a schematic diagram of an optoelectronic system including a PIC according to the present disclosure.

Description of the reference numerals

1 Photonic Integrated Circuit (PIC)

2 epitaxial layer Stack

3 n-type doped contact layer

4 unintentionally doped layer

5a first selectively n-doped contact region of an unintentionally doped layer

5b second selectively n-doped contact region of the unintentionally doped layer

6 first selectively p-doped tubular region

First region of 7 n-type doped contact layer

Second region of 8 n-type doped contact layer

9 unintentionally doping the waveguide layer

10 first photovoltaic device

11 first n-type ohmic metal contact

12 second opto-electronic device

13 second n-type ohmic metal contact

14 passive optical waveguide

15 first portion of the first selectively p-doped tubular region

16 substrate

17 first boundary between substrate and n-type doped contact layer or unintentionally doped layer

A second boundary between the 18 n-type doped contact layer or the unintentionally doped layer and the unintentionally doped waveguide layer

19 first p-type ohmic metal contact

20 second selectively p-doped tubular region

21 second part of the second selectively p-doped tubular region

22 second p-type ohmic metal contact

Third region of 23 n-type doped contact layer

25 third n-type ohmic metal contact

26 p-type doped cladding layer

27 p-type doped contact layer

Recess in 28 p-type doped contact layer

29 first p-type doped contact region

30 second p-type doped contact region

A third boundary between the 31 p-type doped contact layer and the p-type doped cladding layer

Fourth boundary between 32 p-type doped cladding layer and unintentionally doped waveguide layer

33 optoelectronic system

34 mask layer

35 first part of a tubular recess in a masking layer

Exposed surface region of 36 n-type doped contact layer

37 remaining portions of the masking layer

38 first mask layer

41 exposed first surface region of the unintentionally doped layer

42 exposed second surface region of the unintentionally doped layer

44 second mask layer

45 first part of the tubular recess in the second masking layer

46 exposed surface region of the unintentionally doped layer

47 remaining portions of the second mask layer

48 waveguide structure

49 PIN diode

50 p-type ohmic metal contact

51 n type ohmic metal contact

52 Distributed Bragg Reflector (DBR) laser

Mach-Zehnder modulator (MZM)

54 output monitor Photodiode (PD)

Relatively high resistance portion of 55 p-type doped cladding layer

56 semiconductor wafer

Detailed Description

Fig. 1 shows a schematic cross-section of a typical waveguide structure 48 for an indium phosphide (InP) based Photonic Integrated Circuit (PIC) as known in the art. The exemplary waveguide structure 48 comprises an epitaxial layer stack 2, the epitaxial layer stack 2 comprising an intrinsically or unintentionally doped arsenic indium phosphide (InGaAsP) waveguide layer 9, the waveguide layer 9 being sandwiched between a p-type doped InP cladding layer 26 and an n-type doped InP contact layer 3. The waveguide structure 48 essentially forms a PIN diode 49, which PIN diode 49 is schematically shown between the top and the bottom of the waveguide structure 48. The waveguide structure 48 is configured to achieve light emission due to recombination of electrons and holes in the inherently or unintentionally doped InGaAsP layer 9 when the PIN diode 49 is operated in forward bias. In the case where the PIN diode 49 operates in reverse bias, the waveguide structure 48 operates in a so-called photodiode mode in which electrons and holes generated due to absorption of light impinging on the PIN diode 49 need to be extracted. The waveguide structure 48 may also be used, for example, in electro-optic modulators in which the refractive index of an intrinsically or unintentionally doped InGaAsP waveguide layer varies in accordance with the electric field across a reverse biased PIN diode 49.

The different semiconductor layers described above may each be epitaxially grown on a substrate 16 comprising one of semi-insulating indium phosphide, p-type doped indium phosphide and n-type doped indium phosphide, the substrate 16 being compensated with iron atoms to provide at least a semi-insulating surface layer. On top of any of the above substrates, the n-type doped contact layer 3 may be grown using one of Metal Organic Chemical Vapor Deposition (MOCVD), Metal Organic Vapor Phase Epitaxy (MOVPE) and Molecular Beam Epitaxy (MBE).

After successive growth of the n-doped InP contact layer 3, the intrinsic or unintentionally doped InGaAsP waveguide layer 9, the p-doped InP cladding layer 26 and the p-doped indium gallium arsenide (InGaAs) contact layer 27, the waveguide structure 48 is fabricated using a photolithography and etching process in which the p-doped InGaAs contact layer 27 has a higher active p-type doping concentration than the p-doped InP cladding layer 26 on the substrate 16. The p-type doped InGaAs contact layer 27 is provided with a p-type ohmic metal contact 50 and the n-type doped InP contact layer 3 is provided with an n-type ohmic metal contact 51, the p-type ohmic metal contact 50 and the n-type ohmic metal contact 51 being formed using a metal deposition process.

As shown in fig. 1, the n-doped InP contact layer 3 outside the waveguide structure 48 has been removed using a subsequent etching process, thereby exposing the surface of the substrate 16. Thus, the n-type ohmic metal contact 11 has been electrically isolated from the n-type ohmic metal contacts of other components (not shown) disposed on the same substrate 16.

Fig. 2 shows a schematic top view of a prior art PIC including a Distributed Bragg Reflector (DBR) laser 52 as a non-limiting example of a first optoelectronic device, a mach-zehnder modulator (MZM)53 as a non-limiting example of a second optoelectronic device, and an output monitoring Photodiode (PD)54 as a non-limiting example of a third optoelectronic device. The DBR laser 52, MZM53 and output monitor PD54 are optically interconnected via a passive optical waveguide 14. The DBR laser 52, MZM53 and output monitoring PD54 include a waveguide structure 48, the cross-section of which waveguide structure 48 is shown in fig. 1. It will be appreciated by those skilled in the art that complete electrical isolation of the n-type ohmic metal contacts 51 of the DBR laser 52, MZM53 and output monitoring PD54 cannot be achieved by etching away the n-doped InP contact layer 3 between these elements, since the portion of the n-doped InP contact layer 3 that underlies the intrinsic or the extrinsic doped InGaAsP waveguide layer 9 of the passive optical waveguide 14 cannot be removed. In order to establish sufficient electrical isolation between the DBR laser 52, the MZM53 and the n-type ohmic metal contact of the output monitor PD54, sufficient distances are required between these optoelectronic devices, respectively. Therefore, it is difficult to reduce the occupied space of the conventional PIC shown in fig. 2.

In addition, the additional etching step to remove the n-doped InP contact layer 3 between the DBR laser 52, MZM53 and the output monitor PD54 results in additional undesirable surface topology. The additional surface topology can negatively impact subsequent photolithography steps during processing of, for example, the PIC.

Furthermore, it should be noted that when operating the PIC as shown in fig. 2, the p-type ohmic metal contact 50 and the n-type ohmic metal contact 51 of the DBR laser 52 operate at a forward bias, i.e., a typical voltage drop across the p-type ohmic metal contact and the n-type ohmic metal contact is about 0.7V-2.0V. The simplest way to operate the DBR laser 52, MZM53, and output monitoring PD54 is to connect the n-type ohmic metal contact to 0V and generate a variable bias voltage at the p-type ohmic metal contact, although in some cases it may be beneficial to connect the p-type ohmic metal contact to a fixed supply voltage (e.g., 3.3V) and adjust the bias voltage of the n-type ohmic metal contact.

Typically, MZM53 is operated by applying a differential Radio Frequency (RF) voltage between the p-type ohmic metal contacts 50 of the two arms of MZM 53. This differential bias always needs to be lower than the bias of the n-type ohmic metal contact, otherwise the PIN diode 49 of the waveguide structure 48 cannot operate with a reverse bias. In practice, for high speed operation, the DC bias on each arm of MZM53 should be in the range of-5V to-10V. This can be achieved by applying a negative DC bias to the RF voltage driver, or applying a positive bias on the n-type ohmic metal contact. The latter is preferred from an electrical point of view, since it not only eliminates the requirement for bias voltage T, but also makes high speed contacting RF terminals simpler since no DC blocking capacitor is required.

Based on the foregoing, it will be appreciated by those skilled in the art that it is beneficial to electrically isolate at least the n-type ohmic metal contacts 51 of each of the DBR laser 52 and the MZM53 of the PIC shown in fig. 2. Accordingly, there is a need to provide a PIC with improved and desirable complete electrical isolation between n-type ohmic metal contacts of different optoelectronic devices optically interconnected by passive optical waveguides. In the context of the present patent application, the electrical isolation between n-type ohmic metal contacts of different optoelectronic devices of a PIC is referred to as n-isolation. It will be appreciated by those skilled in the art that improved n-isolation according to the present disclosure will have the following effect: for example, in terms of attenuation, the optical signal in a passive optical waveguide interconnecting different optoelectronic devices is as little as possible, and preferably, not at all. Thus, the improved n-isolation according to the present disclosure enables the footprint of the PIC to be further reduced.

Fig. 3 shows a schematic perspective view of a first exemplary, non-limiting embodiment of a PIC1 according to the present disclosure, the PIC1 comprising a semiconductor wafer having an epitaxial layer stack 2, the epitaxial layer stack 2 comprising an n-type doped contact layer 3 comprising indium phosphide (InP). The n-doped contact layer 3 is provided with a first selectively p-doped tubular current blocking region 6. The fact that the first selective p-type doped region 6 has a tubular shape when viewed in three dimensions will be understood by those skilled in the art with reference to fig. 5A and 5B.

The first selectively p-doped tubular region 6 is configured and arranged to provide a first electrical barrier between a first region 7 of the n-doped contact layer 3 surrounded by the first selectively p-doped tubular region 6 and a second region 8 of the n-doped contact layer 3 arranged outside the first selectively p-doped tubular region 6. The epitaxial layer stack 2 further comprises an unintentionally doped waveguide layer 9 comprising indium gallium arsenide phosphide (InGaAsP), which waveguide layer 9 is arranged on top of said n-type doped contact layer 3. The PIC1 comprises a first optoelectronic device 10, which first optoelectronic device 10 is arranged in said first region 7 of said n-doped contact layer 3 surrounded by said first selectively p-doped tubular region 6. The first opto-electronic device 10 comprises a first n-type ohmic metal contact 11, which first n-type ohmic metal contact 11 is arranged at a first location on said n-type doped contact layer 3 within said first region 7. The PIC1 further comprises a second optoelectronic device 12, which second optoelectronic device 12 is arranged in said second region 8 of said n-doped contact layer 3 outside said first selectively p-doped tubular region 6. The second opto-electronic device 12 comprises a second n-type ohmic metal contact 13, which second n-type ohmic metal contact 13 is arranged at a second location on said n-type doped contact layer 3 within said second region 8. The PIC1 also includes a passive optical waveguide 14, which passive optical waveguide 14 includes the unintentionally doped waveguide layer 9. A passive optical waveguide 14 is arranged to optically interconnect the first opto-electronic device 10 with the second opto-electronic device 12. As shown in fig. 3, a first portion 15 of the first selectively p-doped tubular region 6 is disposed beneath the passive optical waveguide 14 between the first optoelectronic device 10 and the second optoelectronic device 12.

It will be appreciated by those skilled in the art that the PIC1 shown in fig. 3 has improved n isolation compared to the n isolation implemented in the prior art PIC shown in fig. 2. In particular, a first portion 15 of the first selectively p-doped tubular region 6 arranged below the passive optical waveguide 14 prevents charge carriers from being leaked between the first n-type ohmic metal contact 11 of the first optoelectronic device 10 and the second n-type ohmic metal contact 13 of the second optoelectronic device 12 via the portion of the n-type doped contact layer 3 arranged below the passive optical waveguide 14 between the first optoelectronic device 10 and the second optoelectronic device 12.

Furthermore, the PIC1 according to the present disclosure having the above-described improved n-isolation is not affected by any undesirable additional surface topology due to the less than ideal n-isolation using conventional etching techniques.

Fig. 4 shows a schematic top view of a second exemplary, non-limiting embodiment of a PIC1 according to the present disclosure, wherein a DBR laser 52, as a non-limiting example of a first optoelectronic device 10, a MZM53, as a non-limiting example of a second optoelectronic device 12, and an output monitoring PD54 are operatively connected to each other via a passive optical waveguide 14. Instead of etching away the n-doped InP contact layer 3 between the DBR laser 52, MZM53 and the output monitor PD54 to establish the best possible n-isolation, the present disclosure proposes to provide the n-doped InP contact layer 3 with a selective p-doped region 6, which selective p-doped region 6 has a tubular shape when viewed in three dimensions. A selectively p-doped tubular region 6 is disposed around the DBR laser 52, MZM53 and output monitoring PD54 to electrically isolate the respective n-type ohmic metal contacts of the DBR laser 52, MZM53 and output monitoring PD54 from each other by preventing charge carriers from leaking between the n-type ohmic metal contacts of the DBR laser 52, MZM53 and output monitoring PD54, respectively, via the portion of the n-doped InP contact layer 3 disposed below the passive optical waveguide 14. As such, the PIC1 shown in fig. 4 has significantly improved n-isolation compared to the n-isolation implemented in the prior PIC shown in fig. 2. It should be noted that the portion of each selectively p-doped tubular region 6 below passive optical waveguide 14 is configured to minimize optical losses in passive optical waveguide 14. Furthermore, the PIC1 according to the present disclosure shown in fig. 4 is not affected by any undesirable additional surface topology that results from the less than ideal n-isolation using conventional etching techniques.

Although not evident from a comparison of fig. 2 and 4, it will be appreciated by those skilled in the art that the DBR laser 52, MZM53 and output monitoring PD54 of the PIC1 shown in fig. 4 may be arranged closer to each other due to the improved n-isolation resulting from the introduction of the selectively p-doped tubular region 6. Thus, the footprint of the PIC1 according to the present disclosure shown in fig. 4 may be reduced as compared to the footprint of the prior art PIC shown in fig. 2.

Further details of the epitaxial layer stack 2 of the PIC1 according to the present disclosure, particularly with respect to the selective p-type doped region 6, will be described in conjunction with fig. 5A, 5B, 6, and 7. Fig. 5A shows a schematic cross-sectional view of a first exemplary, non-limiting embodiment of an epitaxial layer stack 2 of a portion of a PIC1 according to the present disclosure. The epitaxial layer stack 2 shown in fig. 5A is grown on a substrate 16, the substrate 16 comprising one of semi-insulating indium phosphide (s.i. -InP), p-doped indium phosphide (p-InP) and n-doped indium phosphide (n-InP), the substrate 16 being compensated with iron (Fe) atoms to provide at least a semi-insulating surface layer on top of which an n-doped contact layer 3 is grown using one of the above mentioned conventional epitaxial techniques MOCVD, MOVPE or MBE. The n-doped contact layer 3 is provided with said first selectively p-doped tubular region 6 as shown in fig. 3. It should be noted that fig. 5A shows only a cross-section of a first portion 15 of one branch of the first selectively p-doped tubular region 6, which first portion 15, considering fig. 3, is arranged below the unintentionally doped waveguide layer 9 of the passive optical waveguide 14, between the first opto-electronic device 10 and the second opto-electronic device 12 of the PIC1 as shown in fig. 3.

Fig. 5A shows that the first portion 15 of said branch of the first selectively p-doped tubular region 6 extends from the second boundary 18 between the n-doped contact layer 3 and the unintentionally doped waveguide layer 9 through the n-doped contact layer 3 into the substrate 16 until a position beyond the first boundary 17 between the substrate 16 and the n-doped contact layer 3 by a predetermined distance. It will be appreciated by those skilled in the art that, depending on the penetration depth of the selected p-type dopant, the first portion 15 of said branch of the selectively p-doped tubular region 6 may alternatively be configured and arranged to start at said first boundary 17 and end at said second boundary 18.

It is known in the art that p-type doped regions should be far from the passive optical waveguide because they cause additional optical loss. However, it has surprisingly been found that by keeping the thickness t of the first portion 15 of said branch of the first selectively p-doped tubular region 6 between 1 μm and 100 μm, preferably between 2 μm and 10 μm, the additional optical losses can be kept to a minimum.

The first selectively p-doped tubular region 6 comprises zinc (Zn) as a p-type dopant. After the n-doped InP contact layer 3 has been grown and before the growth of the unintentionally doped waveguide layer 9, zinc atoms are arranged in predetermined regions of the n-doped contact layer 3 using a diffusion process at a temperature in the range of 500-600 ℃.

For optimal electrical isolation performance, the first selectively p-doped tubular region 6 of the PIC according to the present disclosure comprises an active p-type doping concentration of 1 × 10¹⁶cm^-3-2×10¹⁸cm^-3Preferably less than or equal to 1 × 10¹⁷cm^-3In the case of an n-doped InP contact layer 3, the p-type doping concentration must be compensated for the initial n-type doping concentration to create said first selective p-doped tubular region 6. the active n-type doping concentration of the n-doped InP contact layer 3 may be about 5 × 10¹⁸cm^-3To achieve a low resistance n-type ohmic metal contact. Thus, achieving a reproducible low p-type doping concentration while compensating for the high n-type doping concentration can be a problem. A solution to this problem will be discussed in more detail in connection with fig. 5B.

The epitaxial layer stack 2 of the PIC1 shown in fig. 5A further comprises a p-doped cladding layer 26 comprising indium phosphide arranged on top of the unintentionally doped waveguide layer 9 and a p-doped contact layer 27 comprising indium gallium arsenide arranged on top of the p-doped cladding layer 26. The p-doped contact layer 27 has a higher active p-type doping concentration than the p-doped cladding layer 26 to allow the formation of a low resistance p-type ohmic metal contact.

Fig. 5A shows that the p-doped contact layer 27 is provided with a recess 28, which recess 28 interrupts the p-doped contact layer 27 and extends into the p-doped cladding layer 26 slightly beyond a third boundary 31 between the p-doped contact layer 27 and the p-doped cladding layer 26. Thus, the recess 28 provides the p-doped contact layer 27 with a first p-doped contact region 29 and a second p-doped contact region 30. The width of the groove 28, seen in a direction parallel to the third boundary 31, is in the range of 5 μm to 200 μm, preferably 30 μm. The recess 28 may be formed by etching away a predetermined portion of the p-type doped contact layer 27 and the underlying p-type doped cladding layer 26, the predetermined portion having a width within the above-described range. In this way, the PIC1 according to the present disclosure is provided with a so-called electrical p-isolation, i.e. an electrical isolation between a first p-doped contact region 29 and a second p-doped contact region 30, which first and second p-doped contact regions 29, 30 may be part of different optoelectronic devices of the PIC 1. The first and second p-doped contact regions 29, 30 may be provided with respective p-type ohmic metal contacts.

As can be seen in fig. 5A, the n-doped contact layer 3 is divided into a first region 7 and a second region 8, which first region 7 and second region 8 are electrically separated by a first portion 15 of said branch of the first selectively p-doped tubular region 6. The p-doped contact layer 27 is divided into said first 29 and said second 30 p-doped contact regions, the first 29 and the second 30 p-doped contact regions being electrically isolated by the recess 28 and the relatively high resistance portion 55 of the p-doped cladding layer 26 below the recess 28. The first region 7 of the n-doped contact layer 3 and the first p-doped contact region 29 of the p-doped contact layer 27 form a first diode, which may belong to a first opto-electronic device of the PIC 1. The second region 8 of the n-doped contact layer 3 and the second p-doped contact region 30 of the p-doped contact layer 27 form a second diode, which may belong to a second optoelectronic device of the PIC 1. It will be appreciated by those skilled in the art that the first diode and the second diode may be electrically operated in forward bias or reverse bias independently of each other. Furthermore, although the first diode of the first opto-electronic device and the second diode of the second opto-electronic device are electrically isolated from each other, they are optically interconnected by an optical waveguide layer 9.

The first portion 15 of said branch of said first selectively p-doped tubular region 6 may be provided with a first p-ohmic metal contact 19, which is only schematically shown in fig. 5A. Likewise, a first n-type ohmic metal contact 11 is applied to the first region 7 of the n-type doped contact layer 3 and a second n-type ohmic metal contact 13 is applied to the second region 8 of the n-type doped contact layer 3. It will be appreciated by the person skilled in the art that the first n-type ohmic metal contact 11 applied to the first region 7 of the n-type doped contact layer 3, the second n-type ohmic metal contact 13 applied to the second region 8 of the n-type doped contact layer 3 and the first p-type ohmic metal contact 19 applied to the first portion 15 of said branch of said first selectively p-type doped tubular region 6 fall outside the cross-section shown in fig. 5A. In the plane shown, they will of course pass beyond the passive optical waveguide layer 9.

Although a first p-type ohmic metal contact 19 applied to the first part 15 of said branch of said first selectively p-type doped tubular region 6 is schematically shown, it is understood by a person skilled in the art that it is possible to electrically contact the first part 15 of said branch of said first selectively p-type doped tubular region 6 in this way, for example for the purpose of biasing.

For example, a short circuit may be arranged between the first p-type ohmic metal contact 19 and the first n-type ohmic metal contact 11, or between the first p-type ohmic metal contact 19 and the second n-type ohmic metal contact 13. Thus, the n-isolation can be electrically controlled when PIC1 is in operation. It will be appreciated by those skilled in the art that a metal layer of a back-end metal layer may be used to establish a short between one of the first and second n-type ohmic metal contacts 11, 13 and the first p-type ohmic metal contact 19. Such an external short-circuit between the first n-type ohmic metal contact 11 applied to the first region 7 of the n-type doped contact layer 3 of the first diode and the first p-type ohmic metal contact 19 applied to the first portion 15 of the branch of the first selectively p-type doped tubular region 6 is particularly advantageous when the second diode comprising the second region 8 of the n-type doped contact layer 3 and the second p-type doped contact region 30 of the p-type doped contact layer 27 is reverse biased with the p-type ohmic metal contact applied to the second p-type doped contact region 30, which is grounded. The above n-isolation is floating in the absence of a short circuit between one of the first and second n-type ohmic metal contacts 11, 13 and the first p-type ohmic metal contact 19.

Fig. 5B shows a schematic cross-sectional view of a second exemplary, non-limiting embodiment of an epitaxial layer stack 2 of a portion of a PIC1 according to the present disclosure. The epitaxial layer stack 2 shown in fig. 5B is grown on a substrate 16, the substrate 16 comprising one of semi-insulating indium phosphide (s.i. -InP), p-doped indium phosphide (p-InP) and n-doped indium phosphide (n-InP), the substrate 16 being compensated with iron (Fe) atoms to provide at least a semi-insulating surface layer on top of which an unintentionally doped InP layer 4 is grown using one of the conventional epitaxial techniques MOCVD, MOVPE or MBE described above. After the growth of the unintentionally doped InP layer 4, a first selective n-doped contact region 5a and a second selective n-doped contact region 5b are provided by ion implantation of n-type dopants. The two selectively n-doped contact regions 5a, 5b allow the formation of a low resistance n-type ohmic metal contact.

After the ion implantation process, the first selectively p-doped tubular region 6 is provided at the portion of the unintentionally doped InP layer 4 between the two selectively n-doped contact regions 5a, 5b, using the zinc diffusion process described above. Since the zinc atoms are diffused into the unintentionally doped InP layer, the p-type doping concentration does not need to be as high as in the case of the n-type doped InP layer 3 described in connection with fig. 5A. Unintentional epitaxial layer Stack 2 as shown in FIG. 5BIn the case of doped layer 4, the p-type dopant need only compensate for any unintentional n-type dopant that may have been introduced during the growth of the unintentionally doped InP layer 4. typical background doping levels for the unintentionally doped InP layer 4 are less than 1 × 10¹⁷cm^-3。

It should also be noted that fig. 5B shows only a cross-section of a first portion 15 of one branch of the first selectively p-doped tubular region 6, which first portion 15, considering fig. 3, is arranged below the unintentionally doped waveguide layer 9 of the passive optical waveguide 14, between the first opto-electronic device 10 and the second opto-electronic device 12 of the PIC1 as shown in fig. 3. It will be appreciated by those skilled in the art that the same statements (observation) as described above in connection with fig. 5A can be made with respect to the branched first portion 15 of the first selectively p-doped tubular region 6.

For the sake of clarity, it should be noted that the first selective p-doped tubular region 6 is configured and arranged to provide a first electrical barrier between said first selective n-doped contact region 5a and said second selective n-doped contact region 5b, which first selective n-doped contact region 5a will be surrounded by said first selective p-doped tubular region 6 and which second selective n-doped contact region 5b will be arranged outside said first selective p-doped tubular region 6, in view of fig. 3.

As can be seen from fig. 5B, an unintentionally doped waveguide layer 9 comprising indium gallium arsenide phosphide (InGaAsP) is arranged on top of said unintentionally doped layer 4. Referring to fig. 3, a first optoelectronic device 10 may be arranged in said first selectively n-doped contact region 5a surrounded by said first selectively p-doped tubular region 6. The first opto-electronic device 10 comprises a first n-type ohmic metal contact 11, which first n-type ohmic metal contact 11 may be arranged at a first location on the first selectively n-type doped contact region 5 a. A second opto-electronic device 12 may be arranged in said second selectively n-doped contact region 5b, which second selectively n-doped contact region 5b is arranged outside said first selectively p-doped tubular region 6. The second opto-electronic device 12 comprises a second n-type ohmic metal contact 13, which second n-type ohmic metal contact 13 is arranged at a second location on the second selectively n-type doped contact region 5 b.

Similar to fig. 5A, it is noted that in fig. 5B only the first p-type ohmic metal contact 19 applied to the first portion 15 of said branch of said first selectively p-type doped tubular region 6, the first n-type ohmic metal contact 11 applied to the first selectively n-type doped contact region 5A, and the second n-type ohmic metal contact 13 applied to the second selectively n-type doped contact region 5B are schematically illustrated. Those skilled in the art will appreciate that these contacts are located outside of the cross-section shown in fig. 5B. In the plane shown, they will of course pass beyond the passive optical waveguide layer 9.

In a similar manner as described in connection with fig. 5A, a first p-ohmic metal contact 19 applied to the first portion 15 of the branch of the first selectively p-doped tubular region 6 may be used for electrically controlling the above-mentioned n-isolation.

As can be seen from fig. 5B, the first selective n-doped contact region 5a of the unintentionally doped layer 4 and the second selective n-doped contact region 5B of the unintentionally doped layer 4 are electrically separated by the first portion 15 of said branch of the first selective p-doped tubular region 6. The p-doped contact layer 27 is divided into said first p-doped contact region 29 and said second p-doped contact region 30, which are electrically isolated from each other by the recess 28 and the relatively high-resistance portion 55 of the p-doped cladding layer 26 located below the recess 28. In order to improve the electrical isolation between said first p-doped contact region 29 and said second p-doped contact region 30, the groove 28 is extended further into the p-doped cladding layer 26 until a predetermined distance from a fourth boundary 32 between the p-doped cladding layer 26 and the unintentionally doped waveguide layer 9, compared to the PIC shown in fig. 5A. The predetermined distance from said fourth boundary 32 may be in the range of 0.5 μm to 5 μm, preferably in the range of 1 μm to 2 μm in order not to disturb the optical waveguide capabilities of the passive optical waveguide layer 9, e.g. in order not to introduce any undesired optical losses due to etching to realize the grooves 28.

In this case, the recess 28 is provided by etching away a predetermined portion having a width in the range of 5 μm to 200 μm, preferably 30 μm, as seen in a direction transverse to the width of the predetermined portion, which includes the complete p-doped contact layer 27 and a part of the p-doped cladding layer 26 up to said predetermined distance from said fourth boundary 32. As such, the PIC1 shown in fig. 5B has improved electrical p-isolation compared to the PIC1 shown in fig. 5A.

Fig. 6 shows a schematic perspective view of a third exemplary, non-limiting embodiment of a PIC1 according to the present disclosure. Similar to fig. 3, the PIC1 shown in fig. 6 comprises a semiconductor wafer with an epitaxial layer stack 2, which epitaxial layer stack 2 comprises an n-doped contact layer 3 comprising indium phosphide (InP). The n-doped contact layer 3 is provided with a first selectively p-doped tubular current blocking region 6 and a second selectively p-doped tubular current blocking region 20, the second selectively p-doped tubular current blocking region 20 being arranged around the first selectively p-doped tubular region 6 and at a preset distance from the first selectively p-doped tubular region 6. A second selectively p-doped tubular region 20 comprises a branch, a second portion 21 of which is arranged below said passive optical waveguide 14 between said first optoelectronic device 10 and said second optoelectronic device 12. It will be appreciated by those skilled in the art that considerations regarding the technical features of a PIC as shown in fig. 6 are the same as for a PIC as shown in fig. 3. For the sake of clarity, these considerations will not be repeated. With reference to fig. 7, further details regarding the second selectively p-doped tubular region 20 will be described.

Fig. 7 shows a schematic cross-sectional view of a third exemplary, non-limiting embodiment of an epitaxial layer stack 2 of a portion of a PIC1 (e.g., the PIC shown in fig. 6) according to the present disclosure. In the cross-sectional view of fig. 7, a second portion 21 of the second selectively p-doped tubular region 20 is arranged in the n-doped contact layer 3 below the unintentionally doped waveguide layer 9 of the passive optical waveguide 14 at a preset distance from the first portion 15 of the first selectively p-doped tubular region 6. The third region 23 of the n-doped contact layer 3 is arranged between the first portion 15 of the first selective p-doped region 6 and the second portion 21 of the second selective p-doped region 20. It will be appreciated by the person skilled in the art that the second selectively p-doped tubular region 20 provides a second electrical barrier between a first region 7 of the n-doped contact layer 3, which first region 7 is surrounded by both the first selectively p-doped tubular region 6 and the second selectively p-doped tubular region 20, and a second region 8 of the n-doped contact layer 3, which second region 8 is arranged outside both the first selectively p-doped tubular region 6 and the second selectively p-doped tubular region 20. The above-mentioned n-isolation between the n-doped contact region of the first opto-electronic device provided with the n-type ohmic metal contact and the n-doped contact region of the second opto-electronic device provided with the n-type ohmic metal contact can be further improved by providing said second selectively p-doped tubular region 20. Those skilled in the art will appreciate that a PIC comprising more than two selectively p-type doped tubular current blocking regions arranged around each other also falls within the scope of the present disclosure. More than two selectively p-doped tubular regions arranged around each other may be required depending on the level of isolation required for a particular application.

In the embodiment shown in fig. 7, the first selectively p-doped tubular region 6 and the second selectively p-doped tubular region 20 both comprise zinc as p-type dopant and both have an active p-type doping concentration of 1 × 10¹⁶cm^-3-2×10¹⁸cm^-3Preferably less than or equal to 1 × 10¹⁷cm^-3. According to other exemplary embodiments falling within the scope of the present disclosure, the type of p-type dopant atoms used for the first and second selectively p-type doped tubular regions 6, 20 may be different. The active p-type doping concentration may also be different. One skilled in the art will know the appropriate p-type dopant atoms and active p-type doping concentrations.

It should be noted that the thickness t of each of the at least first portion 15 of the first selectively p-doped tubular region 6 and the at least second portion 21 of the second selectively p-doped tubular region 20 is between 1 μm and 100 μm, preferably between 2 μm and 10 μm, wherein the first portion 15 and the second portion 21 are arranged below the unintentionally doped waveguide layer 9 of the passive optical waveguide 14. It has been surprisingly found that by keeping the thickness t of at least the first portion 15 of the first selectively p-doped tubular region 6 and at least the second portion 21 of the second selectively p-doped tubular region 20 between 1 μm and 100 μm, preferably between 2 μm and 10 μm, undesired additional optical losses in the passive optical waveguide 14 can be kept to a minimum.

It will be appreciated by those skilled in the art that the first and second selectively p-doped tubular regions 6, 20 may also be provided between selectively n-doped contact regions of an unintentionally doped InP layer grown on the substrate 16, according to another exemplary embodiment of the epitaxial layer stack 2 falling within the scope of the present disclosure.

Furthermore, fig. 7 shows that both the first portion 15 of the first selectively p-doped tubular region 6 and the second portion 21 of the second selectively p-doped tubular region 20 extend from the second boundary 18 between the n-doped contact layer 3 and the unintentionally doped waveguide layer 9 beyond the first boundary 17 between the substrate 16 and the n-doped contact layer 3 until a predetermined distance into the substrate 16. According to other exemplary embodiments falling within the scope of the present disclosure, it is also possible to arrange one of said first and second selectively p-doped tubular regions 6, 20 to extend from said second boundary 18 to said first boundary 17, while the other is arranged to extend beyond said first boundary 17.

As described above in connection with fig. 5A and 5B, fig. 7 schematically shows that the first portion 15 of the selectively p-doped tubular region 6 is provided with a first p-ohmic metal contact 19 and the second portion 21 of the second selectively p-doped tubular region 20 is provided with a second p-ohmic metal contact 22. In this way it is possible to electrically contact the first portion 15 of the first selectively p-doped tubular region 6 and the second portion 21 of the second selectively p-doped tubular region 20, for example for the purpose of biasing. As described above, electrically contacting the first and second selective p-type doped regions enables electrical control of the n-isolation.

Furthermore, fig. 7 schematically shows that a third region 23 of the n-doped contact layer 3 arranged between the first portion 15 of the selectively p-doped tubular region 6 and the second portion 21 of the second selectively p-type tubular region 20 is provided with a third n-type ohmic metal contact 25. It will be appreciated by those skilled in the art that a short circuit may be disposed between one of the first, second and third n-type ohmic metal contacts 11, 13, 25 and the first p-type ohmic metal contact 19 and/or between one of the first, second and third n-type ohmic metal contacts 11, 13, 25 and the second p-type ohmic metal contact 22.

As described in connection with fig. 5A and 5B, it will be understood by those skilled in the art that the respective n-type and p-type ohmic metal contacts schematically illustrated in fig. 7 lie outside the cross-section shown. A corresponding short circuit that may be established between these contacts may be achieved using at least one of the back end metal layers. In the absence of a short circuit between one of the first, second and third n-type ohmic metal contacts 11, 13, 25 and the first p-type ohmic metal contact 19, the n-isolation provided by the first selectively p-type doped tubular region 6 is floating. Similarly, in the absence of a short circuit between one of the first 11, second 13 and third 25 n-type ohmic metal contacts and the second p-type ohmic metal contact 22, the n-isolation provided by the second selectively p-type doped tubular region 20 is floating. Thus, each n-isolation can be electrically controlled, or floating.

Fig. 8A-8D show schematic cross-sectional views of a first exemplary, non-limiting embodiment of a semiconductor wafer 56 fabricated using a first exemplary, non-limiting embodiment of a method according to the present disclosure. The semiconductor wafer 56 enables fabrication of a PIC according to the present disclosure.

Fig. 8A shows the result of the first and second processing steps of the first embodiment of the method. In a first processing step, a substrate 16 is provided, the substrate 16 comprising one of semi-insulating indium phosphide (s.i. -InP), p-doped indium phosphide (p-InP) and n-doped indium phosphide (n-InP), the substrate 16 being compensated with iron (Fe) atoms to provide at least a semi-insulating surface layer. In a second processing step, an n-type doped contact layer 3 comprising indium phosphide is grown on top of the substrate 16 using any of the conventional epitaxial growth techniques MOCVD, MOVPE and MBE.

Fig. 8B shows the results of the third, fourth and fifth processing steps of the first embodiment of the method. In a third process step a mask layer 34 is deposited on top of the n-doped contact layer 3. The mask layer 34 contains silicon oxide (SiO)_x) And silicon nitride (SiN)_x) In a fourth processing step, after a lithographic process, a tubular recess is provided in a mask layer 34 using a first selective etching process to expose a surface region 36 of the n-doped contact layer 3. in the cross-sectional view of fig. 8B, only a first portion 35 of the tubular recess is shown. in a fifth processing step, a p-type dopant, such as zinc (Zn) atoms, is diffused into the n-doped contact layer 3 via the exposed surface region 36 using a diffusion process, in this way a first selective p-doped tubular current blocking region 6 is provided in the n-doped contact layer 3, as described for example in connection with fig. 3 and 5A. the active p-type doping concentration of the first selective p-doped tubular current blocking region 6 is at 1 × 10¹⁶cm^-3-2×10¹⁸cm^-3Preferably less than or equal to 1 × 10¹⁷cm^-3. By providing a first selectively p-doped tubular current blocking region 6, a first region 7 of the n-doped contact layer 3 is created, which is surrounded by the first selectively p-doped tubular current blocking region 6, and a second region 8 of the n-doped contact layer 3, which is arranged outside said first selectively p-doped tubular current blocking region 6. In the cross-sectional view of fig. 8B, only the first portion 15 of the first selectively p-doped tubular region 6 is shown. It will be appreciated by those skilled in the art that a plurality may be arranged depending on the degree of current blocking required for a particular applicationSelectively p-doped tubular current blocking regions surrounding each other as described in connection with fig. 6 and 7.

Fig. 8C shows the result of the sixth processing step of the first embodiment of the method. In a sixth processing step, the remaining part 37 of the mask layer 34 is selectively removed from the n-doped contact layer 3 using a second selective etching process.

Fig. 8D shows the results of the seventh, eighth and ninth processing steps of the first embodiment of the method. In a seventh processing step an unintentionally doped waveguide layer 9 comprising indium gallium arsenide phosphide (InGaAsP) is epitaxially grown on top of the n-type doped contact layer 3 comprising the first selectively p-type doped tubular region 6. The unintentional doping of the waveguide layer 9 enables the fabrication of a passive optical waveguide that enables optical communication between the first and second optoelectronic devices mounted on the semiconductor wafer 56. The n-type ohmic metal contact of the first opto-electronic device is electrically isolated from the n-type ohmic metal contact of the second opto-electronic device by the first selective p-type doped tubular current blocking region 6.

In an eighth processing step a p-type doped cladding layer 26 comprising indium phosphide (InP) is epitaxially grown on top of the unintentionally doped waveguide layer 9. In a ninth process step, a p-type doped contact layer 27 comprising indium gallium arsenide (InGaAs) is epitaxially grown over the top of the p-type doped cladding layer 26. The p-doped contact layer 27 has a higher active p-type doping concentration than the p-doped cladding layer 26 to allow the formation of a low resistance p-type ohmic metal contact.

Fig. 9A-9E show schematic cross-sectional views of a second exemplary, non-limiting embodiment of a semiconductor wafer 56 fabricated using a second exemplary, non-limiting embodiment of a method according to the present disclosure. The semiconductor wafer 56 enables fabrication of a PIC according to the present disclosure.

Fig. 9A shows the result of the first and second processing steps of the second embodiment of the method. In a first processing step, a substrate 16 is provided, the substrate 16 comprising one of semi-insulating indium phosphide (s.i. -InP), p-doped indium phosphide (p-InP) and n-doped indium phosphide (n-InP), the substrate 16 being compensated with iron (Fe) atoms to provide at least a semi-insulating surface layer. In a second processing step, an unintentionally doped layer 4 comprising indium phosphide is grown over the top of the substrate 16 using any of the conventional epitaxial growth techniques MOCVD, MOVPE and MBE.

Fig. 9B shows the results of the third, fourth and fifth processing steps of the second embodiment of the method. In a third process step, a first masking layer 38 is deposited on top of the unintentionally doped layer 4 and completely covers the unintentionally doped layer 4. First masking layer 38 comprises silicon oxide (SiO)_x) And silicon nitride (SiN)_x) At least one of (1). In a fourth processing step, after the first lithography process, a first selective etching process is used to selectively remove a portion of first masking layer 38 to expose first surface region 41 and second surface region 42 of unintentionally doped layer 4. In a fifth processing step, ions of n-type dopants are implanted into the unintentionally doped layer 4 via the first surface region 41 and the second surface region 42, respectively, using an ion implantation process to provide the unintentionally doped layer 4 with a first selective n-type doped contact region 5a and a second selective n-type doped contact region 5b, respectively. In a sixth processing step (not shown), a second selective etching process is used to selectively remove remaining portions of first masking layer 38 covering the portions of unintentional doped layer 4 between first selective n-type doped contact region 5a and second selective n-type doped contact region 5 b. In a seventh processing step (not shown) the substrate 16 and the unintentionally doped layer 4 comprising the first and second selective n-doped contact regions 5a, 5b are annealed to repair any crystalline damage caused by the ion implantation process.

Fig. 9C shows the results of the eighth, ninth and tenth processing steps of the second embodiment of the method. In an eighth processing step a second masking layer 44 is deposited on top of the unintentionally doped layer 4 comprising the first and second selective n-doped contact regions 5a, 5 b. The second mask layer 44 includes silicon oxide (SiO)_x) And silicon nitride (SiN)_x) At least one of (a).

In a ninth processing step, after the second lithography process, a tubular recess is provided in the second mask layer 44 using a third selective etching process to expose a surface region 46 of the portion of the unintentional doped layer 4 between the first selective n-type doped contact region 5a and the second selective n-type doped contact region 5 b. The exposed surface region 46 is arranged to surround, for example, the first selective n-type doped contact region 5 a. In the cross-sectional view of fig. 9C, only the first portion 45 of the tubular groove is shown.

In a tenth processing step, a p-type dopant, such as zinc (Zn) atoms, is diffused via said surface region 46 to a portion of the unintentionally doped layer 4 between the first and second selective n-doped contact regions 5a, 5B using a diffusion process to define a first selective p-doped tubular current blocking region 6, which first selective p-doped tubular current blocking region 6 is according to the example arranged to surround the first selective n-doped contact region 5 a-such that, as described for example in connection with fig. 3 and 5B, a first selective p-doped tubular current blocking region 6 is provided in the unintentionally doped layer 4, which first selective p-doped tubular current blocking region 6 has an active p-type doping concentration of 1 × 10¹⁶cm^-3-2×10¹⁸cm^-3Preferably less than or equal to 1 × 10¹⁷cm^-3The p-type doping concentration need not be as high as in the case of the n-doped InP layer 3 described in connection with, for example, fig. 5A and 8B, since the zinc atoms are diffused into the unintentionally doped layer in the case of the unintentionally doped layer 4 shown in fig. 9C, the p-type dopant need only compensate for any unintentional n-type dopant that may have been introduced during the growth of the unintentionally doped InP layer 4 a typical background doping level of the unintentionally doped InP layer 4 is less than 1 × 10¹⁷cm^-3. It should be noted that in the cross-sectional view of fig. 9C, only the first portion 15 of the first selectively p-doped tubular region 6 is shown. It will be appreciated by those skilled in the art that a plurality of selectively p-doped tubular current blocking regions surrounding each other may be arranged, as described in connection with fig. 6 and 7, depending on the degree of current blocking required for a particular application.

Fig. 9D shows the result of the eleventh processing step of the second embodiment of the method. In an eleventh processing step, the remaining portions 47 of the second mask layer 44 are selectively removed from the unintentionally doped layer 4 comprising the first selective n-doped contact region 5a, the second selective n-doped contact region 5b and the first selective p-doped tubular region 6 using a fourth selective etch process.

Fig. 9E shows the results of the twelfth, thirteenth and fourteenth processing steps of the second embodiment of the method. In a twelfth process step an unintentionally doped waveguide layer 9 comprising arsenic indium gallium phosphide (InGaAsP) is epitaxially grown on top of the unintentionally doped layer 4 comprising the first selective n-doped contact region 5a, the second selective n-doped contact region 5b and the first selective p-doped tubular region 6. This unintentional doping of the waveguide layer 9 enables the fabrication of a passive optical waveguide that enables optical communication between the first and second optoelectronic devices mounted on the semiconductor wafer 56. The n-type ohmic metal contact of the first opto-electronic device is electrically isolated from the n-type ohmic metal contact of the second opto-electronic device by the first selective p-type doped tubular current blocking region 6.

In a thirteenth processing step a p-type doped cladding layer 26 comprising indium phosphide (InP) is epitaxially grown on top of the unintentionally doped waveguide layer 9. In a fourteenth processing step, a p-type doped contact layer 27 comprising indium gallium arsenide (InGaAs) is epitaxially grown over the top of the p-type doped cladding layer 26. The p-doped contact layer 27 has a higher active p-type doping concentration than the p-doped cladding layer 26 to allow the formation of a low resistance p-type ohmic metal contact.

Fig. 10 shows a schematic diagram of an optoelectronic assembly 33 including a PIC1 in accordance with the present disclosure. The optoelectronic assembly 33 according to the present disclosure may be advantageously applied, for example, in telecommunications applications.

The present disclosure may generally relate to a photonic integrated circuit 1, the photonic integrated circuit 1 comprising a first optoelectronic device 10 and a second optoelectronic device 12 mounted on a semiconductor wafer having an epitaxial layer stack 2, the epitaxial layer stack 2 comprising an n-type indium phosphide-based contact layer 3, the n-type indium phosphide-based contact layer 3 being provided with at least one selective p-type doped tubular region 6, the selective p-type doped tubular region 6 serving to provide an electrical barrier between respective n-type contact regions of the first and second optoelectronic devices, wherein the first and second optoelectronic devices are optically interconnected by a passive optical waveguide 14 mounted in an unintentionally doped waveguide layer 9 comprising arsenic indium gallium phosphide, the unintentionally doped waveguide layer being arranged on top of the n-type contact layer, wherein a first portion 15 of the at least one selectively p-doped tubular region is disposed below the passive optical waveguide between the first optoelectronic device and the second optoelectronic device. The present disclosure also relates to an optoelectronic system 33 comprising said photonic integrated circuit.

It should be clear to a person skilled in the art that the scope of the present disclosure is not limited to the examples discussed in the foregoing, but that several amendments and modifications thereof are possible without deviating from the scope of the present disclosure as defined in the attached claims. In particular, certain features of the various aspects of the disclosure may be combined. One aspect of the present disclosure may be further advantageously enhanced by adding features described in connection with another aspect of the present disclosure. While the disclosure has been illustrated in detail in the drawings and described in detail in the specification, the same is to be considered as illustrative or exemplary only, and not restrictive in character.

The present disclosure is not limited to the disclosed embodiments. Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other steps or elements, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims shall not be construed as limiting the scope of the present disclosure.