阅读说明：本技术 降升电压转换装置的控制电路及其模式切换方法 (Control circuit of buck-boost conversion device and mode switching method thereof ) 是由 林恒立 曾荣泓 陈信豪 于 2019-04-11 设计创作，主要内容包括：本发明公开了一种降升电压转换装置的控制电路及其模式切换方法。控制电路包括电流感测电路及模式判断电路。电流感测电路感测降升电压转换装置的输出电流,且提供电流感测信号。模式判断电路耦接电流感测电路,且接收电流感测信号。模式判断电路依据电流感测信号与预设电流产生预设电压,且模式判断电路依据预设电压与电流感测信号产生切换控制信号,以控制降升电压转换装置操作于降压模式、升压模式或降升压模式。本发明的降升电压转换装置能一直维持操作于正确的操作模式下,以发挥最佳的电压转换效能。(The invention discloses a control circuit of a buck-boost conversion device and a mode switching method thereof. The control circuit comprises a current sensing circuit and a mode judging circuit. The current sensing circuit senses the output current of the buck-boost conversion device and provides a current sensing signal. The mode determining circuit is coupled to the current sensing circuit and receives the current sensing signal. The mode judging circuit generates a preset voltage according to the current sensing signal and the preset current, and the mode judging circuit generates a switching control signal according to the preset voltage and the current sensing signal so as to control the buck-boost voltage conversion device to operate in a buck mode, a boost mode or a buck-boost mode. The buck-boost voltage conversion device can always maintain to operate in a correct operation mode so as to exert the optimal voltage conversion efficiency.)

1. A control circuit for a buck-boost converter, said control circuit comprising:

a current sensing circuit for sensing an output current of the buck-boost converter and providing a current sensing signal; and

a mode decision circuit coupled to the current sensing circuit and receiving the current sensing signal,

the mode determining circuit generates a preset voltage according to the current sensing signal and a preset current, and the mode determining circuit generates a switching control signal according to the preset voltage and the current sensing signal to control the buck-boost voltage conversion device to operate in a buck mode, a boost mode or a buck-boost mode.

2. The control circuit of a buck-boost converter according to claim 1, further comprising:

a pulse width modulation generating circuit coupled to the mode judging circuit and generating a pulse width modulation signal according to the switching control signal.

3. The control circuit of a buck-boost converter according to claim 1, wherein said mode determining circuit comprises:

a first determining circuit for determining the switching between the buck mode and the buck-boost mode according to the preset voltage and the current sensing signal; and

a second determining circuit for determining the switching between the buck-boost mode and the boost mode according to the predetermined voltage and the current sensing signal.

4. The control circuit of claim 3, wherein the current sensing signal is equal to the predetermined voltage at a first time, and the first determining circuit compares the current sensing signal with the predetermined voltage at a second time, the second time being later than the first time, to generate the switching control signal to control the buck-boost converter to operate in the buck mode or the buck-boost mode.

5. The control circuit of claim 3, wherein the current sense signal is equal to the predetermined voltage at a first time, and the second determining circuit compares the current sense signal with the predetermined voltage at a second time, the second time being later than the first time, to generate the switching control signal to control the buck-boost converter to operate in the buck-boost mode or the boost mode.

6. A buck-boost mode switching method is applied to a buck-boost conversion device and is characterized by comprising the following steps:

sensing an output current of the buck-boost conversion device and providing a current sensing signal;

generating a preset voltage according to the current sensing signal and a preset current; and

and generating a switching control signal according to the preset voltage and the current sensing signal to control the buck-boost voltage conversion device to operate in a buck mode, a boost mode or a buck-boost mode.

7. The buck-boost mode switching method according to claim 6, further comprising:

generating a pulse width modulation signal according to the switching control signal; and

generating a plurality of switch control signals to an output stage of the buck-boost voltage conversion device according to the pulse width modulation signal.

8. The buck-boost mode switching method according to claim 6, further comprising:

judging the switching between the voltage reduction mode and the voltage reduction and boost mode according to the preset voltage and the current sensing signal; and

and judging the switching between the voltage reduction and boost modes according to the preset voltage and the current sensing signal.

9. The buck-boost mode switching method according to claim 8, further comprising:

comparing the current sensing signal with the preset voltage at a second time after the current sensing signal is equal to the preset voltage at a first time to generate the switching control signal, wherein the second time is later than the first time;

if the current sensing signal is greater than the preset voltage, controlling the buck-boost voltage conversion device to operate in the buck mode; and

and if the current sensing signal is smaller than the preset voltage, controlling the buck-boost voltage conversion device to operate in the buck-boost mode.

10. The buck-boost mode switching method according to claim 8, further comprising:

comparing the current sensing signal with the preset voltage at a second time after the current sensing signal is equal to the preset voltage at a first time to generate the switching control signal, wherein the second time is later than the first time;

if the current sensing signal is smaller than the preset voltage, controlling the buck-boost voltage conversion device to operate in the buck-boost mode; and

and if the current sensing signal is greater than the preset voltage, controlling the buck-boost voltage conversion device to operate in the boost mode.

Technical Field

The present invention relates to voltage conversion, and more particularly, to a control circuit of a buck-boost converter and a method for determining switching of a buck-boost mode.

Background

Referring to fig. 1, fig. 1 is a schematic diagram of an output stage of a DC-DC buck-boost converter (DC-DC buck-boost converter).

As shown in fig. 1, the switches SWA and SWB are connected in series between the input voltage VIN and the ground GND. The gates of the switches SWA and SWB are controlled by the switch control signals UG1 and LG1, respectively, and the switches SWA and SWB are not turned on simultaneously. The switches SWD and SWC are connected in series between the output voltage VOUT and the ground GND. The gates of the switches SWD and SWC are controlled by the switch control signals UG2 and LG2, respectively, and the switches SWD and SWC are not turned on simultaneously. The output inductor L has one end coupled to a node LX1 between the switches SWA and SWB and the other end coupled to a node LX2 between the switches SWD and SWC.

The conventional Buck-Boost mode switching method compares the input voltage VIN with the output voltage VOUT to determine whether the dc-dc Buck-Boost converter 1 should operate in a Buck mode, a Boost mode or a Buck-Boost mode, and correspondingly switches the operation modes.

However, once the input voltage VIN is close to the output voltage VOUT, the operation mode may be misjudged, and even the dc-dc buck-boost converter 1 is repeatedly switched between different operation modes.

Disclosure of Invention

The present invention provides a control circuit of a buck-boost converter and a mode switching method thereof, so as to effectively solve the above problems encountered in the prior art.

An embodiment of the present invention is a control circuit for a buck-boost converter. In this embodiment, the control circuit of the buck-boost converter includes a current sensing circuit and a mode determining circuit. The current sensing circuit senses the output current of the buck-boost conversion device and provides a current sensing signal. The mode determining circuit is coupled to the current sensing circuit and receives the current sensing signal. The mode judging circuit generates a preset voltage according to the current sensing signal and the preset current, and the mode judging circuit generates a switching control signal according to the preset voltage and the current sensing signal so as to control the buck-boost voltage conversion device to operate in a buck mode, a boost mode or a buck-boost mode.

In an embodiment, the control circuit further includes a pwm generating circuit coupled to the mode determining circuit and generating the pwm signal according to the switching control signal.

In one embodiment, the mode determining circuit includes a first determining circuit and a second determining circuit. The first judging circuit is used for judging the switching between the voltage reduction mode and the voltage reduction and boost mode according to the preset voltage and the current sensing signal. The second judgment circuit is used for judging the switching between the buck-boost mode and the boost mode according to the preset voltage and current sensing signal.

In one embodiment, the current sensing signal is equal to the predetermined voltage at a first time, and the first determining circuit compares the current sensing signal with the predetermined voltage at a second time, which is later than the first time, to generate the switching control signal to control the buck-boost conversion device to operate in the buck mode or the buck-boost mode.

In one embodiment, the current sensing signal is equal to the predetermined voltage at a first time, and the second determining circuit compares the current sensing signal with the predetermined voltage at a second time, which is later than the first time, to generate the switching control signal to control the buck-boost converter to operate in the buck-boost mode or the boost mode.

Another embodiment according to the present invention is a buck-boost mode switching method. In this embodiment, the buck-boost mode switching method is applied to the buck-boost converter. The switching judgment method of the buck-boost mode comprises the following steps: sensing the output current of the buck-boost conversion device and providing a current sensing signal; generating a preset voltage according to the current sensing signal and a preset current; and generating a switching control signal according to the preset voltage and current sensing signal to control the buck-boost voltage conversion device to operate in a buck mode, a boost mode or a buck-boost mode.

In an embodiment, the buck-boost mode switching method further includes: generating a pulse width modulation signal according to the switching control signal; and generating a plurality of switch control signals to an output stage of the buck-boost voltage conversion device according to the pulse width modulation signal.

In an embodiment, the buck-boost mode switching method further includes: judging the switching between the voltage reduction mode and the voltage reduction and boost mode according to the preset voltage and the current sensing signal; and judging the switching between the voltage reduction and boost modes according to the preset voltage and the current sensing signal.

In an embodiment, the buck-boost mode switching method further includes: after the current sensing signal is equal to the preset voltage in a first time, comparing the current sensing signal with the preset voltage in a second time to generate the switching control signal, wherein the second time is later than the first time; if the current sensing signal is greater than the preset voltage, controlling the buck-boost voltage conversion device to operate in the buck mode; and if the current sensing signal is smaller than the preset voltage, controlling the buck-boost voltage conversion device to operate in the buck-boost mode.

In an embodiment, the buck-boost mode switching method further includes: after the current sensing signal is equal to the preset voltage in a first time, comparing the current sensing signal with the preset voltage in a second time to generate the switching control signal, wherein the second time is later than the first time; if the current sensing signal is smaller than the preset voltage, controlling the buck-boost voltage conversion device to operate in the buck-boost mode; and if the current sensing signal is greater than the preset voltage, controlling the buck-boost voltage conversion device to operate in the boost mode.

Compared with the prior art, the control circuit of the buck-boost conversion device and the buck-boost mode switching method can judge whether the operation mode of the buck-boost conversion device needs to be switched or not according to the output current sensing result of the buck-boost conversion device, so that the problem that the buck-boost conversion device is continuously and repeatedly switched among different operation modes because a comparator cannot accurately judge according to the comparison result of the input voltage and the output voltage in the prior art can be effectively solved, and the buck-boost conversion device can be ensured to be always kept operating in a correct operation mode to exert the optimal voltage conversion efficiency.

The advantages and spirit of the present invention can be further understood by the following detailed description of the invention and the accompanying drawings.

Drawings

Fig. 1 is a schematic diagram of an output stage of a dc-dc buck-boost converter.

Fig. 2 is a schematic diagram of a buck-boost converter according to an embodiment of the invention.

Fig. 3 is a detailed schematic diagram of the buck-boost converter.

Fig. 4 is a schematic diagram of the pwm generating circuit including a mode switching circuit.

FIG. 5 shows an embodiment of the first determining circuit and the current sensing circuit.

Fig. 6 is a timing diagram of the switch control signal, the output current, the current sensing signal, the preset voltage, the enable signal and the latch signal when the first determining circuit operates.

FIG. 7 shows an embodiment of a second determination circuit and a current sensing circuit.

Fig. 8 is a timing diagram of the switch control signal, the output current, the current sensing signal, the preset voltage, the enable signal and the latch signal when the second determination circuit operates.

Fig. 9 is a timing diagram of the switch control signal, the output current, the current sensing signal, the preset voltage, the enable signal and the latch signal when the first determining circuit and the second determining circuit operate simultaneously.

Fig. 10 is a flowchart of a switching determination method for a buck-boost mode according to another embodiment of the invention.

Description of the main element symbols:

VIN: input voltage

VOUT: output voltage

IOUT: output current

GND: grounding terminal

L: output inductor

C: capacitor with a capacitor element

R: resistance (RC)

R1-R2: voltage dividing resistor

SWA to SWD: switch with a switch body

UG 1-UG 2: switch control signal

LG 1-LG 2: switch control signal

LX 1-LX 2: node point

2: step-down/step-up voltage conversion device

20: control circuit

22: driver

24: output stage

200: current sensing circuit

202: mode judging circuit

204: pulse width modulation generating circuit

202A: first judging circuit

202B: second judging circuit

204A: mode switching circuit

204B: pulse width modulation generator

VSEN: current sensing signal

S1: switching control signal

PWM: pulse width modulation signal

206: addition unit

208: error amplifier

210: comparator with a comparator circuit

VRAMP: ramp signal

VSAW: adding signals

VFB: feedback voltage

VREF: reference voltage

COMP: error amplified signal

S2: comparing signals

A1-A2: output end

B1-B2: output end

LA 1-LA 3: latch unit

OR 1-OR 2: OR gate

S, R: input terminal

Q: output end

S3(M1), S3(M2), S3 (M3): mode switching signal

PWM (M1), PWM (M2), PWM (M3): pulse width modulation signal

VSENV: preset voltage

VSENP: preset voltage

I: preset current

M1-M2: switch with a switch body

EN 1: enabling signal

EN 1': inverted enable signal

EN 2: enabling signal

EN 2': inverted enable signal

COM: comparator with a comparator circuit

LA: latch signal

T0-T5: time of day

S10-S14: step (ii) of

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. The same or similar numbered elements/components used in the drawings and the embodiments are used to represent the same or similar parts.

In the present invention, the output current refers to the current flowing through the inductor L in fig. 1, or the current flowing through the switch SWD when the switch SWD is turned on.

An embodiment of the present invention is a control circuit for a buck-boost converter. In this embodiment, the Buck-Boost converter may be a dc-dc Buck-Boost converter having four switching output stages, and the control circuit may determine, according to the output current sensing result of the Buck-Boost converter, that the Buck-Boost converter should operate in a Buck mode (Buck mode), a Boost mode (Boost mode), or a Buck-Boost mode (Buck-Boost mode), but not limited thereto.

Referring to fig. 2, fig. 2 is a schematic diagram of the buck-boost converter in this embodiment. As shown in fig. 2, the buck-boost converter 2 includes a control circuit 20, a driver 22 and an output stage 24. The control circuit 20 is coupled to the driver 22 and the output stage 24, respectively. The driver 22 is coupled to the control circuit 20 and the output stage 24, respectively. The output stage 24 is coupled to the driver 22 and the control circuit 20, respectively.

The control circuit 20 includes a current sensing circuit 200, a mode determining circuit 202 and a pwm generating circuit 204. The current sensing circuit 200 is coupled to the output stage 24 and the mode determining circuit 202, respectively. The mode determining circuit 202 is coupled to the current sensing circuit 200 and the pwm generating circuit 204, respectively. The pwm generating circuit 204 is coupled to the mode determining circuit 202 and the driver 22 respectively.

The current sensing circuit 200 is used for sensing the output current IOUT of the output stage 24 and accordingly generating a current sensing signal VSEN to the current sensing circuit 200. In practical applications, the current sensing signal VSEN provided by the current sensing circuit 200 can be in the form of a voltage or a current, and is not limited in particular.

The mode determining circuit 202 receives the current sensing signal VSEN provided by the current sensing circuit 200 and accordingly generates the switching control signal S1 to the pwm generating circuit 204. The mode determination circuit 202 includes a first determination circuit 202A and a second determination circuit 202B.

The first determining circuit 202A is coupled to the current sensing circuit 200 and the pwm generating circuit 204, respectively, for determining the switching of the buck-boost converter 2 between the buck mode and the buck-boost mode according to the current sensing signal VSEN and the preset voltage, and generating a switching control signal S1 according to the determination result to control the buck-boost converter 2 to operate in the buck mode or the buck-boost mode.

That is, when the buck-boost converter 2 operates in the buck mode, the first determining circuit 202A may determine that the buck-boost converter 2 should remain operating in the buck mode or should switch from the buck mode to the buck-boost mode according to a comparison result of the current sensing signal VSEN and the preset voltage.

Similarly, when the buck-boost converter 2 operates in the buck-boost mode, the first determining circuit 202A may also determine that the buck-boost converter 2 should remain operating in the buck-boost mode or should switch from the buck-boost mode to the buck mode according to a comparison result of the current sensing signal VSEN and the preset voltage.

The second determining circuit 202B is coupled to the current sensing circuit 200 and the pwm generating circuit 204, respectively, for determining the switching of the buck-boost converter 2 between the buck-boost mode and the boost mode according to the current sensing signal VSEN and the preset voltage, and generating a switching control signal S1 according to the determination result to control the buck-boost converter 2 to operate in the boost mode or the buck-boost mode.

That is, when the buck-boost converter 2 operates in the boost mode, the second determining circuit 202B may determine that the buck-boost converter 2 should remain operating in the boost mode or should switch from the boost mode to the buck-boost mode according to the comparison result of the current sensing signal VSEN and the predetermined voltage.

Similarly, when the buck-boost converter 2 operates in the buck-boost mode, the second determining circuit 202B may also determine that the buck-boost converter 2 should remain operating in the buck-boost mode or should switch from the buck-boost mode to the boost mode according to a comparison result of the current sensing signal VSEN and the preset voltage.

When the PWM generating circuit 204 receives the switching control signal S1 provided by the mode determining circuit 202, the PWM generating circuit 204 generates a corresponding PWM signal PWM to the driver 22 according to the switching control signal S1, and the driver 22 correspondingly generates a plurality of switch control signals UG1, LG1, UG2 and LG2 to the output stage 24 according to the received PWM signal PWM, so as to control the operations of the switches in the output stage 24.

Referring to fig. 3, fig. 3 is a detailed schematic diagram of the buck-boost converter 2. As shown in fig. 3, the control circuit 20 includes an adding unit 206, an error amplifier 208, a comparator 210, voltage dividing resistors R1-R2, a resistor R, and a capacitor C, in addition to the current sensing circuit 200, the mode determining circuit 202, and the pwm generating circuit 204.

The current sensing circuit 200 is coupled to the mode determining circuit 202 and the adding unit 206, respectively, for providing the current sensing signal VSEN to the mode determining circuit 202 and the adding unit 206, respectively. The adding unit 206 is coupled to the negative input terminals of the current sensing circuit 200 and the comparator 210, respectively, for receiving the current sensing signal VSEN and the ramp signal VRAMP, respectively, and adding them to generate an added signal VSAW to the negative input terminal of the comparator 210.

The voltage dividing resistors R1 and R2 are connected in series between the output voltage VOUT and the ground GND. The feedback voltage VFB is provided between the voltage dividing resistors R1 and R2, and is a divided voltage of the output voltage VOUT. The positive input + and the negative input-of the error amplifier 208 respectively receive the reference voltage VREF and the feedback voltage VFB, and accordingly generate an error amplification signal COMP to the positive input + of the comparator 210. The resistor R and the capacitor C are connected in series between the output terminal of the error amplifier 208 and the ground GND.

When the positive input terminal + and the negative input terminal of the comparator 210 receive the error amplification signal COMP and the addition signal VSAW, respectively, the comparator 210 compares the error amplification signal COMP with the addition signal VSAW, and generates a comparison signal S2 to the pwm generating circuit 204 according to the comparison result.

When the PWM generating circuit 204 receives the switching control signal S1 provided by the mode determining circuit 202 and the comparison signal S2 provided by the comparator 210, respectively, the PWM generating circuit 204 generates a corresponding PWM signal PWM to the driver 22 according to the switching control signal S1 and the comparison signal S2, and the driver 22 correspondingly generates a plurality of switching control signals UG1, LG1, UG2 and LG2 to the output stage 24 according to the PWM signal PWM.

The output stage 24 includes four switches SWA to SWD, an output inductor L, and an output capacitor C. The switches SWA and SWB are connected in series between the input voltage VIN and the ground GND. The gates of the switches SWA and SWB are controlled by the switch control signals UG1 and LG1, respectively, and the switches SWA and SWB are not turned on simultaneously. The switches SWD and SWC are connected in series between the output voltage VOUT and the ground GND. The gates of the switches SWD and SWC are controlled by the switch control signals UG2 and LG2, respectively, and the switches SWD and SWC are not turned on simultaneously. The output inductor L has one end coupled to a node LX1 between the switches SWA and SWB and the other end coupled to a node LX2 between the switches SWD and SWC. The current sensing circuit 200 is coupled to the node LX1 for sensing the output current IOUT and accordingly generating a current sensing signal VSEN.

Referring to fig. 4, fig. 4 is a schematic diagram of the pwm generation circuit 204 including a mode switching circuit 204A. As shown in fig. 4, the mode determining circuit 202 includes a first determining circuit 202A and a second determining circuit 202B. The pwm generation circuit 204 includes a mode switching circuit 204A and a pwm generator 204B. The first determining circuit 202A and the second determining circuit 202B are both coupled to the mode switching circuit 204A. The mode switching circuit 204A is coupled to the pwm generator 204B.

In this embodiment, the mode switching circuit 204A includes latch cells LA 1-LA 3 and OR gates OR 1-OR 2. The output terminal a1 of the first judgment circuit 202A is coupled to the input terminal S of the latch unit LA1 and an input terminal of the OR gate OR2, respectively. The output terminal a2 of the first judgment circuit 202A is coupled to the input terminal R of the latch unit LA1 and an input terminal of the OR gate OR1, respectively. The output terminal B1 of the second decision circuit 202B is coupled to the input terminal S of the latch unit LA3 and another input terminal of the OR gate OR2, respectively. The output terminal B2 of the second decision circuit 202B is coupled to the input terminal R of the latch unit LA3 and another input terminal of the OR gate OR1, respectively. The output of OR gate OR1 is coupled to input S of latch LA2 and the output of OR gate OR2 is coupled to input R of latch LA 2. The output Q of the latch units LA 1-LA 3 are coupled to the PWM generator 204B.

When the first determining circuit 202A determines that the buck-boost converter 2 should operate in the buck mode, the first determining circuit 202A outputs the switching control signal S1 to the input terminal S of the latch unit LA1 and an input terminal of the OR gate OR2 through the output terminal a 1; when the first determining circuit 202A determines that the buck-boost converter 2 should operate in the buck-boost mode, the first determining circuit 202A outputs the switching control signal S1 to the input terminal R of the latch LA1 and an input terminal of the OR gate OR1 through the output terminal a 2.

Similarly, when the second determining circuit 202B determines that the buck-boost converter 2 should operate in the boost mode, the second determining circuit 202B outputs the switching control signal S1 to the input terminal S of the latch LA3 and the other input terminal of the OR gate OR2 through the output terminal B1; when the second determining circuit 202B determines that the buck-boost converter 2 should operate in the buck-boost mode, the second determining circuit 202B outputs the switching control signal S1 to the input terminal R of the latch LA3 and the other input terminal of the OR gate OR1 through the output terminal B2.

The latch units LA 1-LA 3 in the mode switching circuit 204A correspondingly generate a mode switching signal S3 corresponding to the buck mode, the buck-boost mode or the boost mode to the PWM generator 204B according to the switching control signal S1 provided by the first determining circuit 202A or the second determining circuit 202B, and the PWM generator 204B generates a PWM signal PWM corresponding to the buck mode, the buck-boost mode or the boost mode according to the mode switching signal S3.

For example, when the input terminal S of the latch unit LA1 in the mode switching circuit 204A receives the switching control signal S1, it indicates that the buck-boost converter 2 should operate in the buck mode, and therefore, the latch unit LA1 correspondingly generates the mode switching signal S3(M1) corresponding to the buck mode to the PWM generator 204B, and the PWM generator 204B generates the PWM signal PWM (M1) corresponding to the buck mode according to the mode switching signal S3 (M1).

Similarly, when the input terminal S of the latch unit LA3 in the mode switching circuit 204A receives the switching control signal S1, it indicates that the buck-boost voltage conversion device 2 should operate in the boost mode, and therefore, the latch unit LA3 correspondingly generates the mode switching signal S3(M2) corresponding to the boost mode to the PWM generator 204B, and the PWM generator 204B generates the PWM signal PWM (M2) corresponding to the buck mode according to the mode switching signal S3 (M2).

Similarly, when any input terminal of the OR gate OR1 in the mode switching circuit 204A receives the switching control signal S1, it indicates that the buck-boost voltage conversion device 2 should operate in the buck-boost mode, and therefore, the latch unit LA2 correspondingly generates the mode switching signal S3(M3) corresponding to the buck-boost mode to the PWM generator 204B, and the PWM generator 204B generates the PWM signal PWM (M3) corresponding to the buck-boost mode according to the mode switching signal S3 (M3).

Referring to fig. 5, fig. 5 shows an embodiment of the first determining circuit 202A and the current sensing circuit 200. As shown in fig. 5, the first determining circuit 202A includes a predetermined current I, switches M1-M2, a capacitor C, and a comparator COM. The predetermined current I is coupled between the switch M1 and the ground GND. The switch M1 is coupled between the preset current I and the switch M2, and the gate of the switch M1 is controlled by the inverted enable signal EN 1'. One end of the capacitor C is coupled between the switches M1 and M2 and the other end of the capacitor C is coupled to the ground GND. The switch M2 is coupled between the switch M1 and the resistor R, and the gate of the switch M2 is controlled by the enable signal EN 1.

The current sensing circuit 200 includes a resistor R for sensing the output current IOUT to generate a current sensing signal VSEN between the switch M2 and the resistor R. The first determining circuit 202A generates a predetermined voltage VSENV between the switches M1 and M2 according to the current sensing signal VSEN and the predetermined current I.

The positive input terminal + of the comparator COM is coupled between the switch M2 and the resistor R and the negative input terminal-of the comparator COM is coupled between the switches M1 and M2. The positive input terminal + and the negative input terminal of the comparator COM respectively receive the current sensing signal VSEN and the preset voltage VSENV, and generate the switching control signal S1 according to a comparison result between the current sensing signal VSEN and the preset voltage VSENV.

For example, as shown in fig. 6, when the buck-boost converter 2 operates in the buck mode, the switch control signal UG1 controlling the switch SWA in the output stage 24 is at a high level at time T0 to T2 and at a low level at time T2 to T3, i.e., the switch SWA in the output stage 24 is turned on and the switch SWB is turned off during time T0 to T2; during the period from T2 to T3, the switch SWA in the output stage 24 is turned off and the switch SWB is turned on.

During the period from T0 to T2, the output current IOUT increases linearly with time, and its slope is [ (input voltage VIN-output voltage VOUT)/output inductance L ]; during the time period from T2 to T3, the output current IOUT decreases linearly with time, and its slope is [ (-output voltage VOUT)/output inductor L ]. The curve of the current sense signal VSEN is also consistent with the output current IOUT, and therefore, will not be described herein.

During the period from T0 to T1, the enable signal EN1 is high, so that the switch M2 is controlled by the enable signal EN1 to be turned on, and the switch M1 is controlled by the inverted enable signal EN 1' to be turned off; during the period from T1 to T3, the enable signal EN1 is low, so that the switch M2 is turned off by the enable signal EN1, and the switch M1 is turned on by the inverted enable signal EN 1'.

At time T1, the current sense signal VSEN is equal to the predetermined voltage VSENV. Next, since the preset current I makes the rising slopes of the preset voltage VSENV and the current sensing signal VSEN different, a difference occurs between the preset voltage VSENV and the current sensing signal VSEN.

At time T2, the latch signal LA triggers the first determining circuit 202A to compare the current sensing signal VSEN with the predetermined voltage VSENV, which indicates that the buck-boost converter 2 should maintain the buck mode, so the first determining circuit 202A correspondingly generates the switching control signal S1 to control the buck-boost converter 2 to maintain the buck mode.

In other words, in the period from time T1 to time T2, if the absolute value of the current change slope of the output current IUOT is smaller than the absolute value of the current change slope of the preset current I, the buck-boost voltage conversion device 2 enters the buck-boost mode; conversely, the buck-boost converter 2 is disengaged from the buck-boost mode.

When the buck-boost converter 2 operates in the buck-boost mode, the first determining circuit 202A determines that the buck-boost converter 2 should remain operating in the buck-boost mode or switch to the buck mode, and so on, which is not described herein again.

Referring to fig. 7, fig. 7 shows an embodiment of the second determination circuit 202B and the current sensing circuit 200. As shown in fig. 7, the second determining circuit 202B includes a predetermined current I, switches M1-M2, a capacitor C, and a comparator COM. The predetermined current I is coupled between the switch M1 and the ground GND. The switch M1 is coupled between the preset current I and the switch M2, and the gate of the switch M1 is controlled by the inverted enable signal EN 2'. One end of the capacitor C is coupled between the switches M1 and M2 and the other end of the capacitor C is coupled to the ground GND. The switch M2 is coupled between the switch M1 and the resistor R, and the gate of the switch M2 is controlled by the enable signal EN 2.

The current sensing circuit 200 includes a resistor R for sensing the output current IOUT to generate a current sensing signal VSEN between the switch M2 and the resistor R. The second determining circuit 202B generates a predetermined voltage VSENP between the switches M1 and M2 according to the current sensing signal VSEN and the predetermined current I.

The positive input terminal + of the comparator COM is coupled between the switch M2 and the resistor R and the negative input terminal-of the comparator COM is coupled between the switches M1 and M2. The positive input terminal + and the negative input terminal of the comparator COM respectively receive the current sensing signal VSEN and the preset voltage VSENP, and generate the switching control signal S1 according to the comparison result between the current sensing signal VSEN and the preset voltage VSENP.

For example, as shown in fig. 8, when the buck-boost converter 2 operates in the buck-boost mode, the switch control signal UG2 controlling the switch SWC in the output stage 24 is at a high level at time T0 to T1 and at a low level at time T1 to T3, i.e., the switch SWC in the output stage 24 is turned on and the switch SWD is turned off during time T0 to T1; during the period from T1 to T3, the switch SWC in the output stage 24 is turned off and the switch SWD is turned on.

During the period from T0 to T1, the output current IOUT rises linearly with time, with a slope (input voltage VIN/output inductance L) and the current sense signal VSEN is zero; during the period from T1 to T3, the output current IOUT decreases linearly with time, and the slope thereof is [ (input voltage VIN-output voltage VOUT)/output inductor L ], and the curve of the current sensing signal VSEN is consistent with the output current IOUT.

During the period from T0 to T2, the enable signal EN2 is high, so that the switch M2 is controlled by the enable signal EN2 to be turned on, and the switch M1 is controlled by the inverted enable signal EN 2' to be turned off; during the period from T2 to T3, the enable signal EN2 is low, so that the switch M2 is turned off by the enable signal EN2, and the switch M1 is turned on by the inverted enable signal EN 2'.

At time T2, the second determining circuit 202B determines that the current sensing signal VSEN is equal to the predetermined voltage VSENP. Next, since the slope of the preset voltage VSENP is different from that of the current sense signal VSEN, a difference occurs between the preset voltage VSENP and the current sense signal VSEN.

At time T3, the second determining circuit 202B determines that the current sensing signal VSEN is greater than the predetermined voltage VSENP, indicating that the buck-boost converter 2 should maintain the operation in the buck-boost mode, and accordingly the second determining circuit 202B generates the switching control signal S1 to control the buck-boost converter 2 to maintain the operation in the buck-boost mode.

Similarly, if the second determining circuit 202B determines that the current sensing signal VSEN is less than the predetermined voltage VSENP, it indicates that the buck-boost converter 2 should be switched to the boost mode, and therefore the second determining circuit 202B correspondingly generates the switching control signal S1 to control the buck-boost converter 2 to switch from the buck-boost mode to the boost mode.

When the buck-boost converter 2 operates in the buck-boost mode, the second determining circuit 202B determines whether the buck-boost converter 2 should remain operating in the buck-boost mode or switch to the boost mode, and so on, which is not described herein again.

Next, referring to fig. 9, fig. 9 is a timing diagram of the switch control signals UG1 and LG2, the output current IOUT, the current sensing signal VSEN, the preset voltages VSENV to VSENP, the enable signals EN1 to EN2, and the latch signal LA when the first determining circuit 202A and the second determining circuit 202B operate simultaneously.

As shown in fig. 9, it is assumed that the buck-boost converter 2 operates in the boost mode during the time T0 to T3 and operates in the buck mode during the time T3 to T5.

When the buck-boost converter 2 operates in the boost mode during the time period T0 to T3, the switch SWC in the output stage 24 is turned on and the switch SWD is turned off during the time period T0 to T1; during the period from T1 to T3, the switch SWC in the output stage 24 is turned off and the switch SWD is turned on.

During the period from T0 to T1, the output current IOUT rises linearly with time, with a slope (input voltage VIN/output inductance L) and the current sense signal VSEN is zero; during the period from T1 to T3, the output current IOUT is kept constant, the slope thereof is [ (input voltage VIN-output voltage VOUT)/output inductor L ], and the current sensing signal VSEN is consistent with the output current IOUT.

During the period from T0 to T2, the enable signals EN1 and EN2 are both high, so that the switch M2 in the first determining circuit 202A and the second determining circuit 202B is controlled by the enable signals EN1 and EN2 to be turned on, and the switch M1 in the first determining circuit 202A and the second determining circuit 202B is controlled by the inverted enable signals EN1 'and EN 2' to be turned off; during the period from T2 to T5, the enable signals EN1 and EN2 are both low, so that the switch M2 in the first determining circuit 202A and the second determining circuit 202B is controlled by the enable signals EN1 and EN2 to be turned off, and the switch M1 in the first determining circuit 202A and the second determining circuit 202B is controlled by the inverted enable signals EN1 'and EN 2' to be turned on.

At time T2, the first determining circuit 202A determines that the current sense signal VSEN is equal to the predetermined voltage VSENV and the second determining circuit 202B determines that the current sense signal VSEN is equal to the predetermined voltage VSENP. Next, since the predetermined current I causes the predetermined voltages VSENV and VSENP to have different slopes from the current sense signal VSEN, the last three voltages at time T2 will have different slopes.

At time T4, the buck-boost converter 2 operates in the buck-boost mode, and the first determining circuit 202A determines that the current sensing signal VSEN is less than the predetermined voltage VSENV, indicating that the buck-boost converter 2 should maintain the buck-boost mode, so the first determining circuit 202A generates the switching control signal S1 to control the buck-boost converter 2 to maintain the buck-boost mode. The rest can be analogized, so that the description is omitted.

Another embodiment of the present invention is a method for determining switching between buck-boost modes. In this embodiment, the method for determining switching of the buck-boost mode is applied to the buck-boost converter for determining whether the buck-boost converter should operate in the buck mode, the boost mode or the buck-boost mode, but not limited thereto.

Referring to fig. 10, fig. 10 is a flowchart of a buck-boost mode switching method in this embodiment. As shown in fig. 10, the buck-boost mode switching method includes the following steps:

step S10: sensing the output current of the buck-boost conversion device and providing a current sensing signal;

step S12: generating a preset voltage according to the current sensing signal and a preset current; and

step S14: and generating a switching control signal according to the preset voltage and current sensing signal so as to control the buck-boost voltage conversion device to operate in a buck mode, a boost mode or a buck-boost mode.

For other detailed implementation manners of the buck-boost mode switching method, reference may be made to the related descriptions of the above embodiments, and further description is not repeated herein.

Compared with the prior art, the control circuit of the buck-boost conversion device and the buck-boost mode switching method can judge whether the operation mode of the buck-boost conversion device needs to be switched or not according to the output current sensing result of the buck-boost conversion device, so that the problem that the buck-boost conversion device is continuously and repeatedly switched among different operation modes because a comparator cannot accurately judge according to the comparison result of the input voltage and the output voltage in the prior art can be effectively solved, and the buck-boost conversion device can be ensured to be always kept operating in a correct operation mode to exert the optimal voltage conversion efficiency.