阅读说明：本技术 泄漏补偿电路及相应方法、具有泄漏补偿电路的集成电路 (Leakage compensation circuit and corresponding method, integrated circuit with leakage compensation circuit ) 是由 J·C·J·杰森斯 于 2020-01-10 设计创作，主要内容包括：本发明涉及泄漏补偿电路及用于泄漏补偿的方法、以及具有该泄漏补偿电路的集成电路。在一种形式中,泄漏补偿电路包括缓冲放大器、链路耦合元件和泄漏补偿元件。缓冲放大器具有输出和耦合到感测节点的输入。链路耦合元件具有输出和耦合到缓冲放大器的输出的输入,其中链路耦合元件在从输入到其输出的方向上是单向的。泄漏补偿元件具有耦合到感测节点的第一电流端子、耦合到链路耦合元件的输出的控制端子、以及耦合到参考电压端子的第二电流端子。(The invention relates to a leakage compensation circuit and a method for leakage compensation, and an integrated circuit having the leakage compensation circuit. In one form the leakage compensation circuit includes a buffer amplifier, a link coupling element, and a leakage compensation element. The buffer amplifier has an output and an input coupled to the sensing node. The link coupling element has an output and an input coupled to the output of the buffer amplifier, wherein the link coupling element is unidirectional in a direction from the input to the output thereof. The leakage compensation element has a first current terminal coupled to the sense node, a control terminal coupled to an output of the link coupling element, and a second current terminal coupled to a reference voltage terminal.)

1. A leakage compensation circuit, comprising:

a buffer amplifier having an input coupled to a sensing node and an output;

a link coupling element having an output and an input coupled to the output of the buffer amplifier, wherein the link coupling element is unidirectional in a direction from the input thereof to the output thereof; and

a leakage compensation element having a first current terminal coupled to the sense node, a control terminal coupled to the output of the link coupling element, and a second current terminal coupled to a reference voltage terminal.

2. The leakage compensation circuit of claim 1, wherein the buffer amplifier comprises:

a differential amplifier having a positive input coupled to the sense node, a negative input, and an output coupled to the negative input, the output forming the output of the buffer amplifier.

3. The leakage compensation circuit of claim 1, wherein the buffer amplifier comprises:

a single-ended non-inverting amplifier having a positive input coupled to the sense node, and an output coupled to the output of the buffer amplifier.

4. The leakage compensation circuit of claim 1, wherein the link coupling element comprises:

a diode having an anode coupled to the output of the buffer amplifier and a cathode coupled to the control terminal of the leakage compensation element.

5. The leakage compensation circuit of claim 1, wherein the leakage compensation element comprises:

an anti-series diode having a first current terminal coupled to the sense node, a second current terminal coupled to the reference voltage terminal, and an intermediate terminal serving as the control terminal of the leakage compensation element, the intermediate terminal coupled to the output of the link coupling element.

6. An integrated circuit having a leakage compensation circuit, the leakage compensation circuit comprising:

a buffer amplifier having an input coupled to a sensing node and an output;

a link coupling element having an output and an input coupled to the output of the buffer amplifier, wherein the link coupling element is unidirectional in a direction from the input thereof to the output thereof; and

a leakage compensation element having a first current terminal coupled to the sense node, a control terminal coupled to the output of the link coupling element, and a second current terminal coupled to a reference voltage terminal.

7. The integrated circuit of claim 6, wherein the leakage compensation element comprises:

an anti-series diode having a first current terminal coupled to the sense node, a second current terminal coupled to the reference voltage terminal, and an intermediate terminal forming the control terminal of the leakage compensation element, the intermediate terminal coupled to the output of the link coupling element.

8. The integrated circuit of claim 7, wherein:

the intermediate terminal of the anti-series diode and the output of the link-coupling element are formed in a common semiconductor region.

9. The integrated circuit of claim 8, wherein:

the common semiconductor region is a common floating buried layer and the input of the link coupling element is isolated from the first current terminal of the anti-series diode by a trench partially penetrating the common semiconductor region.

10. A method of performing leakage compensation for leakage current flowing into or out of a sensing node, the method comprising:

buffering the voltage on the sense node and providing a buffered voltage to an intermediate node in response to the buffering;

unidirectionally coupling the buffered voltage to a control node; and

biasing a leakage compensation element having a first current terminal coupled to the sense node and a second current terminal coupled to a reference voltage terminal by coupling a control terminal of the leakage compensation element to the control node.

Technical Field

The present disclosure relates generally to integrated circuits, and more particularly to leakage compensation circuits for use in integrated circuits, and methods for leakage compensation.

Background

Certain environmental sensors, such as rain and light sensors, ambient light sensors, laser ranging and ranging (LiDAR) sensors, etc., require very high dynamic range at their input. For example, they may generate a sensing current of about 50 picoamperes (pA) or less. Although integrated circuit and Radio Frequency (RF) noise can be reduced by selecting an appropriate circuit topology or by increasing the current consumption of the sensor, Direct Current (DC) offset caused by leakage current generated on the integrated circuit is still very difficult to compensate. For example, integrated circuit input terminals are typically protected by diodes that inject leakage current onto various circuit nodes. These DC offset currents significantly limit the achievable gain, thus limiting the input range, and may actually completely prevent some small signals from being detectable.

Although the DC offset voltage may be removed by a chopping mechanism having a differential circuit structure, the DC leakage current is typically single-ended. In addition, although the DC offset voltage can be removed by storing the offset voltage using a switched capacitor mechanism, current cannot be stored. Furthermore, the leakage current is typically very small and practically impossible to compensate by any known current digital-to-analog converter (DAC) because the current is too low to be handled using a current mirror. Bidirectional current DACs based on reference leakage currents and single-ended current DACs with selectable current mirrors have proven insufficient to compensate for these small leakage currents. Thus, leakage current, an inherent feature of integrated circuit design, limits the dynamic range of the sensor.

Disclosure of Invention

In one aspect, the present invention provides a leakage compensation circuit comprising: a buffer amplifier having an output and an input coupled to the sensing node; a link coupling element having an output and an input coupled to the output of the buffer amplifier, wherein the link coupling element is unidirectional in a direction from the input to the output thereof; and a leakage compensation element having a first current terminal coupled to the sense node, a control terminal coupled to an output of the link coupling element, and a second current terminal coupled to the reference voltage terminal.

In another aspect, the present invention provides an integrated circuit having a leakage compensation circuit, the leakage compensation circuit comprising: a buffer amplifier having an output and an input coupled to the sensing node; a link coupling element having an output and an input coupled to the output of the buffer amplifier, wherein the link coupling element is unidirectional in a direction from the input to the output thereof; and a leakage compensation element having a first current terminal coupled to the sense node, a control terminal coupled to an output of the link coupling element, and a second current terminal coupled to the reference voltage terminal.

In another aspect, the present invention provides a method of performing leakage compensation for leakage current flowing into or out of a sensing node, comprising: buffering the voltage on the sensing node and providing a buffered voltage to the intermediate node in response to the buffering; unidirectionally coupling the buffered voltage to a control node; and biasing a leakage compensation element having a first current terminal coupled to the sense node and a second current terminal coupled to the reference voltage terminal by coupling a control terminal of the leakage compensation element to the control node.

Drawings

The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings, wherein:

FIG. 1 illustrates, in block diagram form, a sensor circuit susceptible to leakage;

FIG. 2 illustrates, in partial block diagram and partial schematic form, a leakage compensation circuit in accordance with various embodiments;

FIG. 3 illustrates, in partial block diagram and partial schematic form, a buffer amplifier according to another embodiment of the buffer amplifier of FIG. 2;

FIG. 4 shows, in partial block diagram and partial schematic form, a buffer amplifier according to yet another embodiment of the buffer amplifier of FIG. 2;

FIG. 5 shows, in partial block diagram and partial schematic form, a buffer amplifier according to yet another embodiment of the buffer amplifier of FIG. 2;

FIG. 6 schematically illustrates a link coupling element according to another embodiment of the link coupling element of FIG. 2;

FIG. 7 schematically illustrates another embodiment of a link coupling element according to another embodiment of the link coupling element of FIG. 2;

FIG. 8 illustrates, in partial block diagram and partial schematic form, portions of a leakage compensation circuit in accordance with other embodiments;

FIG. 9 shows a set of correlation graphs showing the relationship of signals related to the operation of the leakage compensation circuit of FIG. 2;

FIG. 10 illustrates a cross-section of an integrated circuit that may be used to implement a portion of the leakage compensation circuit of FIG. 2;

FIG. 11 illustrates a cross-section of another integrated circuit that may be used to implement a portion of the leakage compensation circuit of FIG. 2;

FIG. 12 illustrates a cross-section of yet another integrated circuit that may be used to implement a portion of the leakage compensation circuit of FIG. 2;

FIG. 13 illustrates a cross-section of yet another integrated circuit that may be used to implement a portion of the leakage compensation circuit of FIG. 2; and

fig. 14 illustrates a cross-section of yet another integrated circuit that may be used to implement a portion of the leakage compensation circuit of fig. 2.

The use of the same reference symbols in different drawings indicates the same or similar elements. Unless otherwise stated, the word "coupled" and its associated verb forms include both direct and indirect electrical connections by means known in the art; and unless otherwise indicated, any description of a direct connection also implies an alternative implementation using an indirect electrical connection of suitable form.

Detailed Description

FIG. 1 illustrates, in block diagram form, a sensor circuit 100 that is susceptible to leakage. The sensor circuit 100 includes a sensor 110, a SENSE node 120 labeled "SENSE", a transimpedance amplifier 130, and an integrated circuit terminal 140. The sensor 110 has a sensor for sensing in response to sensing one of a plurality of environmental conditions (such as rain, light, ambient light, etc.)The sense node 120 provides an output of current. The transimpedance amplifier 120 has an input connected to the sensing node 120 and a terminal 140 connected to the integrated circuit for providing thereto a signal labeled "V_OUT"and the output of the associated transimpedance labeled" 1/gm ".

Certain non-ideal factors can distort the operation of the sensor 110 and reduce its dynamic range. For example, Direct Current (DC) offset caused by relatively small leakage currents of unknown marks is still very difficult to compensate. Fig. 1 shows two possible leakage currents that may affect the operation of sensor 110. One possible leakage current labeled "ILEAK _ PUSH" represents a positive current injected (or "pushed") onto the sense node 120. Another possible leakage current labeled "ILEAK _ PULL" represents a positive current drawn (or "pulled") from the sense node 120. In many integrated circuits, these small currents cannot be easily estimated or measured in advance, and even the direction of the leakage current is not easily predicted, making them very difficult to compensate.

The DC offset voltage may be removed by a chopping mechanism. However, the chopping mechanism cannot be used to compensate for DC leakage current, as it typically involves a differential structure, whereas DC leakage current is single-ended. In addition, although the DC offset voltage can be removed by storing the offset voltage using the switched capacitor circuit, the leakage current cannot be stored. Furthermore, since leakage currents are typically very small, they are practically impossible to compensate by any other known circuit, such as a current digital-to-analog converter (DAC).

Fig. 2 illustrates, in partial block diagram and partial schematic form, a leakage compensation circuit 200 in accordance with various embodiments. Leakage compensation circuit 200 generally includes a buffer amplifier 210, a link coupling element 220, and a leakage compensation element 230. The buffer amplifier 210 has an input connected to the SENSE node and an output connected to a node labeled "CTRL". The link coupling element 220 has an input connected to the output of the buffer amplifier 210 and an output connected to a node labeled "MID". Leakage compensation element 230 has a first current terminal connected to the SENSE node, a control terminal connected to the MID node, and a second current terminal connected to a reference voltage terminal labeled "REF".

In the embodiment shown in fig. 2, the buffer amplifier 210 includes a differential amplifier 212, a variable offset generator 214, and an offset circuit 216. The differential amplifier 212 has a positive input labeled "+", a negative input labeled "-", and an output connected to its negative input for providing an output voltage to the CTRL node. The variable offset generator 214 has a negative terminal connected to the SENSE node, a digital control input, and a positive terminal connected to the positive input of the differential amplifier 212. The offset circuit 216 has an output connected to the digital control input of the variable offset generator 214 for providing a multi-bit digital signal labeled "TRIM". The link coupling element 220 includes a PN junction diode 222 having an anode forming an input of the link coupling element 220 and a cathode forming an output of the link coupling element 220. Leakage compensation element 230 includes an anti-series diode having a PN junction diode 232 and a PN junction diode 234. The PN junction diode 232 is a "top" diode having an anode connected to the SENSE node and a cathode connected to the MID node. The PN junction diode 232 is a "bottom" diode having a cathode connected to the MID node and an anode connected to the REF terminal.

In operation, the leakage compensation circuit 200 flows out or in the SENSE node by subtracting (pulling) or adding (pushing) the name "I_COMP"to compensate for leakage current on the SENSE node. As will be further explained below, due to I_COMPIs also node leakage current, so I is expected_COMPThe general behavior above temperature is similar to existing leakage currents. In addition, the leakage compensation circuit 200 controls the exact amount of compensation current and its signature by the voltage applied to the leakage compensation element 230.

In the leakage compensation circuit 200, the buffer amplifier 210 is connected in a voltage follower configuration, where the output provided to the CTRL node is equal to the voltage on the SENSE node plus an offset voltage V_OS. Offset voltage V_OSAnd then set by the digital correction signal TRIM provided by the offset circuit 216. The link coupling element 220 is at the input to the output when the voltage across the PN junction is forward biasedA diode conducting current in the direction of (a). Because the magnitude of the forward current around the turn-on voltage is substantially greater than the magnitude of the reverse saturation current, e.g., greater than three orders of magnitude, the link coupling element 220 is considered a unidirectional element. Thus, the PN junction diode 222 is a link-coupled element capable of conducting more current in one direction (forward) than in the other direction (reverse) and setting a voltage on the MID node. The leakage compensation circuit 200 provides a compensation current I to be pulled or pushed from the SENSE node through a feedback control loop formed by the buffer amplifier 210, the link coupling element 220 and the leakage compensation element 230_COMPWhich exactly matches the leakage current.

More details of various implementations of the components of the leakage compensation circuit 200 will now be presented.

Implementation of buffer amplifier 210

Fig. 3 illustrates, in partial block diagram and partial schematic form, a buffer amplifier 300 in accordance with another embodiment of the buffer amplifier 210 of fig. 2. The buffer amplifier 300 includes the differential amplifier 212 and the offset circuit 216 as previously described with respect to fig. 2. However, unlike buffer amplifier 210, buffer amplifier 300 includes a variable offset generator 314 that is configured differently than variable offset generator 214 of fig. 2. The variable offset generator 314 has a positive terminal connected to the output of the differential amplifier 212, a digital control input connected to the output of the offset circuit 216 for receiving the TRIM signal therefrom, and a negative terminal connected to the negative input of the differential amplifier 212. Thus, the variable offset generator, 214 of fig. 2 or 314 of fig. 3, may achieve the same result by being connected to either the positive input of the differential amplifier 212 or the negative input of the differential amplifier 212.

Fig. 4 shows, in partial block diagram and partial schematic form, a buffer amplifier 400 according to a further embodiment of the buffer amplifier 210 of fig. 2. The buffer amplifier 400 includes the differential amplifier 212 and the offset circuit 216 as previously described with respect to fig. 2. However, unlike buffer amplifier 210, buffer amplifier 400 includes a variable offset generator 414 that is configured differently than variable offset generator 214 of fig. 2. The variable offset generator 414 has a negative terminal connected to the output of the differential amplifier 212, a control input connected to the output of the offset circuit 216 for receiving the TRIM signal therefrom, and a positive terminal connected to the CTRL node. Buffer amplifier 400 shows that the same result can be achieved by connecting a variable offset generator 414 to the output of differential amplifier 212.

Fig. 5 shows, in partial block diagram and partial schematic form, a buffer amplifier 500 according to a further embodiment of the buffer amplifier 210 of fig. 2. The buffer amplifier 500 includes the differential amplifier 212 and the offset circuit 216 as previously described with respect to fig. 2. However, unlike buffer amplifier 210, buffer amplifier 500 includes a variable offset generator 514 that is configured differently than variable offset generator 214 of fig. 2. Variable offset generator 514 includes resistor 510, and current DAC520 and current DAC530, each labeled "IDAC". The resistor 510 has a first terminal connected to the output of the differential amplifier 212, and a second terminal connected to the CTRL node. The current DAC520 has a first current terminal connected to the supply voltage terminal, a control input connected to the output of the offset circuit 216 for receiving the TRIM signal, and a second current terminal connected to the CTRL node for supplying current to the CTRL node. The current DAC530 has a first terminal connected to the CTRL node for sinking current from the CTRL node, a control input connected to the output of the offset circuit 216 for receiving the TRIM signal, and a second current terminal connected to ground. Since the control terminal of leakage compensation element 230 is a high impedance node, the current through resistor 510 provided by current DACs 520 and 530 produces the desired voltage offset, the magnitude of which is determined by the TRIM signal.

From the various examples shown in fig. 2-5, it should be apparent that the offset voltage may be generated in various ways and that various circuits may be used. The offset circuit 216 may also determine the value of the TRIM signal in various ways. For example, the value of the TRIM signal may be calibrated for each chip at manufacturing test, and the offset circuit 216 may include non-volatile memory to store calibration values for use during operation. In another example, the offset circuit 216 may determine the TRIM bits in part by using manufacturing process measurements from an on-chip process control device, or measurements of process control parameters in a wafer on which the chips are contained.

Implementation of the Link coupling element 220

Fig. 6 shows in schematic form a link coupling element 600 according to another embodiment of the link coupling element 220 of fig. 2. The link coupling element 600 includes a transistor 610, which in the illustrated embodiment is an N-channel MOS transistor having a connection labeled "V" to a transistor_DD"a drain of the positive power supply terminal, a gate connected to the CTRL node, and a source connected to the MID node. V_DDIs a more positive supply voltage terminal with respect to the ground of the integrated circuit, whose voltage is higher than the highest desired voltage of the MID node, so that the transistor 610 operates as a source follower and the voltage of the MID node follows the voltage of the CTRL node minus the threshold voltage drop. Similar to the PN junction diode 222 of fig. 2, the transistor 610 is biased unidirectional and allows current to flow into the MID node, but does not allow any substantial DC current to flow out of the MID node.

Fig. 7 shows in schematic form a link coupling element 700 according to another embodiment of the link coupling element 220 of fig. 2. The link coupling element 700 includes a transistor 710, which in the illustrated embodiment is an NPN bipolar transistor having a connection labeled "V_CC"a collector of the positive power supply terminal, a base connected to the CTRL node, and an emitter connected to the MID node. V_CCIs a more positive supply voltage terminal with respect to the ground of the integrated circuit, whose voltage is higher than the highest desired voltage of the MID node, so that the transistor 710 operates as an emitter follower and the voltage of the MID node follows the voltage of the CTRL node minus the diode turn-on voltage of the base-emitter diode. Similar to the PN junction diode 222 of fig. 2, the transistor 710 is biased unidirectional and allows current to flow into the MID node, but does not allow any substantial DC current to flow out of the MID node.

Operation of the control loop

Fig. 8 illustrates, in partial block diagram and partial schematic form, a portion 800 of leakage compensation circuits 810 and 820 according to other embodiments. The leakage compensation circuit 810 includes additional elements such as the buffer amplifier 210 and low pass filter 812 previously shown with respect to fig. 2 and the leakage compensation circuit 200 not shown in fig. 8. Low pass filter 812 includes resistor 814 and capacitor 816. Resistor 814 has a first terminal connected to the output of buffer amplifier 210, and a second terminal connected to the CTRL node. Capacitor 816 has a first terminal connected to the second terminal of resistor 814 and a second terminal connected to ground.

Leakage compensation circuit 820 includes additional elements such as buffer amplifier 210 and low pass filter 822 previously shown with respect to fig. 2 and leakage compensation circuit 200 not shown in fig. 8. The low pass filter 822 includes a resistor 824 and a capacitor 826. Resistor 824 has a first terminal connected to the SENSE node, and a second terminal connected to the input of buffer amplifier 210. Capacitor 826 has a first terminal connected to the second terminal of resistor 824, and a second terminal connected to ground potential.

The leakage compensation circuit 200 is a feedback control loop formed by a buffer amplifier 210 having an input connected to the SENSE node, a link coupling element 220, and a leakage compensation element 230 having an output connected to the SENSE node. In various embodiments, the SENSE node may carry a useful signal, or it may receive electromagnetic interference (EMI) noise. The leakage compensation circuits 810 and 820 compensate for signal variations by providing low pass filtering to prevent the leakage compensation loop from following these signals. It is believed that a simple RC low pass filter as shown in fig. 8 is sufficient for this purpose. However, other suitable filters may be used, such as higher order low pass filters, band pass filters, and the like, where appropriate.

Fig. 9 shows a set of correlation graphs 900 illustrating the relationship of signals related to the operation of the leakage compensation circuit 200 of fig. 2. Graph 900 includes graph 910 and graph 920 related by mirror line 930. Graph 910 shows the relationship between the voltage of the CTRL node labeled "V (CTRL)", on the horizontal axis in volts, and the voltage of the MID node labeled "V (MID)", on the vertical axis in volts. Waveform 912 displays the value of V (MID) as a function of V (CTRL). Generally, waveform 912 shows v (mid) following v (ctrl) and shifted substantially parallel to, but downward due to the turn-on voltage of the PN junction silicon diode. For forward bias conditions, it also generally follows a 45 degree line through the origin, as expected from a piecewise linear model of the voltage-current characteristics of the PN junction diode. For all v (mid) voltages above 0 volts, v (ctrl) is selected to vary substantially linearly to provide a large tuning range. Below v (mid) 0 volts, v (mid) saturates.

Graph 920 shows V (MID) along a horizontal axis in volts and compensation current I pushed into or pulled from the SENSE node along a vertical axis in picoamps (pA)_COMPThe relationship between them. The mirror line 930 shows the correspondence of v (mid) along the vertical axis in graph 910 to v (mid) along the horizontal axis in graph 920. Waveform 922 is_COMPShown as a function of V (MID).

In the example shown in FIG. 9, a particular leakage current to be compensated is pushed into the SENSE node (I)_LEAKPUSH), as shown along the vertical axis in graph 920. Waveform 922 shows V (MID) and I that will balance ILEAK _ PUSH_COMPThe relationship between them. The intersection of ILEAK _ PUSH and waveform 922 indicates the ideal value of V (MID), which will generate an equal and opposite I as ILEAK _ PUSH_COMP. This v (mid) value is then projected onto waveform 912 using mirror line 930. The value of v (ctrl) at the point where the projected v (mid) line intersects waveform 912 determines the ideal value of v (ctrl). The difference between ideal V (CTRL) and V (SENSE) is equal to the ideal offset voltage V_OS。

When V (CTRL)>>V (SENSE), such as when V (SENSE) + V_OS>>V (SENSE), the link coupling element 220 pulls up the MID node to (V (SENSE) + V_OSVFW _ LINK), where VFW _ LINK is the forward voltage of the PN junction diode 222, thereby reversing the potential across the PN junction diode 232. In this case, the SENSE node will receive a compensation current I equivalent to the reverse saturation current of the PN junction diode 232_COMP. For this example, additional current will be pushed into the SENSE node, tending to pull the SENSE node up. Leakage current of the PN junction diode 234 does not flow to the SENSE node, but rather passes through the PN junction diode222 and delivered by the differential amplifier 212.

When V (CTRL)<<V (SENSE), such as when V (SENSE) + V_OS<<V (sense), the unidirectional nature of the PN junction diode 222 prevents the PN junction diode 222 from determining v (mid). In contrast, V (MID) will settle to its minimum value, equal to V (SENSE-VFW _ DTOP), where VFW _ DTOP is the forward-biased turn-on voltage of PN junction diode 232. This may occur regardless of how low V (CTRL) is relative to V (SENSE). In this case, the SENSE node will receive a compensation current I equivalent to the reverse saturation current of PN junction diode 232 having a reverse voltage equal to V (MID) -REF and the reverse saturation current of PN junction diode 222 having a reverse voltage equal to V (MID) -V (CTRL)_COMP. Therefore, in this case, I will be pulled from the SENSE node_COMPTending to pull down the SENSE node.

Thus, by setting V_OSTo adjust the voltage on the CTRL node relative to the SENSE node, the leakage compensation circuit 200 operates bi-directionally and is able to compensate for small leakage currents, regardless of their sign.

Implementation of leakage compensation element 230

As shown in fig. 2, leakage compensation element 230 is implemented as an anti-series diode. In the example shown in fig. 2, the anti-series diode may be implemented with two PN junction diodes having a common cathode forming the MID node. In an alternative embodiment, the anti-series diode may be implemented with two PN junction diodes having a common anode forming the MID node. These structures may be implemented in monolithic silicon integrated circuits using a variety of device architectures.

Fig. 10 illustrates a cross-section of an integrated circuit 1000 that may be used to implement a portion of the leakage compensation element 230 of fig. 2. A portion of integrated circuit 1000 illustrates a device structure that may be used to implement leakage compensation element 230. The integrated circuit 1000 includes a semiconductor body 1010 having an epitaxially grown P-type region labeled "Pepi" that forms the anode of the bottom diode (PN junction diode 234). The N-type region 1020 covers the Pepi region and forms the common cathode region of the anti-serial diode. In various embodiments, N-type region 1020 may be a deep N-well region or an N-type reduced surface field region (NRESURF). Integrated circuit 1000 includes N-type semiconductor well regions 1030 and 1040 extending from N-type region 1020 to the surface of semiconductor substrate 1110. Both N-type well region 1030 and N-type well region 1040 isolate P-type well region 1050 from surrounding circuitry. The P-type well region 1050 forms the anode of the PN junction diode 232 of the leakage compensation element and also forms the SENSE node. Within the P-type well region 1050 may be other circuitry 1060 that may form all or part of the sensor 110, a portion of the buffer amplifier 210, or other elements and circuitry of the integrated circuit 1000.

Fig. 11 illustrates a cross section of another integrated circuit 1100 that may be used to implement a portion of the leakage compensation circuit 200 of fig. 2, in accordance with various embodiments. The inventors of the present patent application have implemented the leakage compensation circuit 200 with such a structure called a dielectric trench isolation (MTI) structure. Details of the structure of integrated circuit 1100 are described in U.S. patent No.10,026,728, which is incorporated herein by reference in its entirety.

The integrated circuit 1100 includes a semiconductor substrate 1110 in which the link coupling element 220 and the leakage compensation element 230 are formed. The semiconductor substrate 1110 includes a P-type region 1112, a buried N-type region 1114, an N-type region 1116, a P-type region 1118, a deep trench structure 1120, a dielectric trench isolation (MTI) structure 1130, a circuit region 1140, a circuit region 1150, a conductive contact 1160, and an electrode 1170. P-type region 1112 serves as the REF node, and buried N-type region 1114 forms the bottom diode (PN junction diode 234). The N-type region 1116 and the overlying P-type region 1118 together form a top diode (PN junction diode 232) with the P-type region 1118 forming a SENSE node. The portions of the N-type region 1116 and the P-type region 1118 between the deep trench structure 1120 and the MTI structure 1130 form the PN junction diode 222. The deep trench structure 1120 includes a dielectric layer 1122 lining the buried deep trench structure and a polysilicon layer 1124 filling the deep trench structure 1120. Similarly, the MTI structure 1130 includes a dielectric layer 1132 that lines the MTI structure and a polysilicon layer 1134 that fills the MTI structure 1130.

Since the N-type region 1114 is uninterrupted by the MTI structure 1130, the cathode of the PN junction diode 222 is electrically connected to the cathodes of the PN junction diodes 232 and 234, conveniently forming the MID node. Thus, the device structure shown in cross-section in fig. 11 with MTI structure 1130 may be used to form link coupling element 220 and leakage compensation element 230.

The device structure shown in fig. 11 may be implemented using known integrated circuit fabrication techniques, including those described in U.S. patent No.10,026,728, as well as other known techniques. In the embodiment shown in fig. 11, the device structures use a batch process, but in other embodiments they may be formed with corresponding epitaxial structures.

Fig. 12 illustrates a cross-section of yet another integrated circuit 1200 that may be used to implement a portion of the leakage compensation circuit 200 of fig. 2. The portion of integrated circuit 1200 shown in fig. 12 implements link coupling element 220 and leakage compensation element 230. The integrated circuit 1200 includes a semiconductor body 1210 having a Pepi region forming the anode of the bottom diode (PN junction diode 234). The N-type region 1220 overlies the Pepi region and forms the common cathode region of the anti-series diode and the cathode region of the PN junction diode 222 in the link coupling element 220. In various embodiments, N-type region 1020 may be a deep N-well region, an N-type reduced surface field region ((NRESURF), or an N-type well region [ integrated circuit 1200 ] includes N-type semiconductor well regions 1230, 1240, and 1250 forming a MID node that extends from deep N-well region 1220 to the surface of semiconductor body 1210. N-well region 1230 and N-well region 1250 isolate P-well region 1260 from surrounding circuitry P-well region 1260 forms P-well region 1260 anode of PN junction diode 232 of leakage compensation element 230 and also forms a SENSE node N-well region 1250 and N-well region 1240 isolate P-well region 1270 from surrounding circuitry P-well region 1270 forms the anode of PN junction diode 222 of link-coupling element 220 and also forms a CTRL node.

Fig. 13 illustrates a cross section of yet another integrated circuit 1300 that may be used to implement a portion of the leakage compensation circuit 200 of fig. 2. Integrated circuit 1300 includes a semiconductor body 1310 having a Pepi region forming the anode of the bottom diode (PN junction diode 234). The first N-type region 1320 covers the Pepi region and forms the common cathode region of the anti-serial diode. Integrated circuit 1300 includes N-type semiconductor well regions 1330 and 1340 forming MID nodes that extend from first N-type region 1320 to the surface of semiconductor body 1310. N-well regions 1330 and 1340 surround and isolate P-well region 1350. The P-type well region 1350 forms an anode of the PN junction diode 232 of the leakage compensation element 230 and also forms a SENSE node. A second N-type region 1360 overlies the Pepi region and forms the common cathode region of the second anti-series diode. Integrated circuit 1300 includes N-type well regions 1370 and 1380 that form the MID node, which extends from second N-type region 1360 to the surface of semiconductor body 1310. N-type well regions 1370 and 1380 surround and isolate P-well region 1390. The P-type well region 1390 forms the anode of the PN junction diode 222 of the link coupling element 220 and also forms the CTRL node. In various embodiments, N regions 1320 and 1360 may be deep N-well regions, NRESURF regions, or N-well regions. This portion of integrated circuit 1300 shows a device structure that may be used to implement link coupling element 220 and leakage compensation element 230 using only one type of device structure, in which case PN junction diode 224 is present but not used.

Fig. 14 illustrates a cross-section of yet another integrated circuit 1400 that may be used to implement a portion of the leakage compensation circuit 200 of fig. 2. The integrated circuit 1400 includes a semiconductor body 1410 having a Pepi region forming the anode of the bottom diode (PN junction diode 234). The first N-type region 1430 covers the Pepi region and forms the common cathode region of the anti-serial diode. The integrated circuit 1400 includes N-type well regions 1440 and 1450 forming MID nodes that extend from the first N-type region 1430 to the surface of the semiconductor body 1410. N-type well regions 1430 and 1450 surround and isolate P-type well region 1460. The P-type well region 1460 forms an anode of the PN junction diode 232 of the leakage compensation element 230, and also forms a SENSE node. The second N-type region 1470 covers the Pepi region and forms the common-cathode region of the second anti-serial diode. Integrated circuit 1300 includes N-type well regions 1480 and 1490 that also form the MID node, which extends from second N-type region 1470 to the surface of semiconductor body 1310 and is connected to N-type well region 1450 by a metal conductor. N-type well regions 1480 and 1490 surround and isolate P-type well region 1492. The P-type well region 1492 forms the anode of the PN junction diode 222 of the link coupling element 220 and also forms the CTRL node. This portion of the integrated circuit 1400 shows a device structure that may be used to implement the link coupling element 220 and the leakage compensation element 230 using only one type of device structure, in which case the PN junction diode 224 is present but not used.

In addition, the integrated circuit 1400 includes an N-type well region 1420 that forms the cathode of the PN junction diode 236. The anode of the PN junction diode 236 is formed in the semiconductor body 1410. An N-well 1420 is connected to the MID node through a metal connection, for example at N-well region 1440. Diode 236 operates in parallel with diode 234 to increase the reverse saturation current. The portion of the integrated circuit 1400 shown in fig. 14 implements a modification of the link coupling element 230, modifying the junction area with the increased bottom diode, to allow for increased reverse saturation current when the MID node is biased to a relatively high voltage.

Thus, the leakage compensation circuit and method as disclosed herein accurately compensate for small leakage currents that are not easily compensated by conventional techniques. The leakage compensation circuit exhibits a temperature dependence that will track the temperature dependence of various leakage sources, such as ESD protection diodes. In one form the leakage compensation circuit includes a buffer amplifier, a link coupling element, and a leakage compensation element. The buffer amplifier has an output and an input connected to the sensing node. The link coupling element has an output and an input connected to the output of the buffer amplifier, wherein the link coupling element is unidirectional in a direction from the input to the output thereof. The leakage compensation element has a first current terminal connected to the sense node, a control terminal connected to the output of the link coupling element, and a second current terminal connected to a reference voltage terminal.

The leakage compensation circuit comprises a compensation current I capable of being injected with a variable value and a variable flag_COMPThe leakage compensation element of (1). It acts as a voltage controlled bi-directional current source and can be compensated for leakage in situ. Thus, a sensor circuit incorporating a leakage compensation circuit may achieve a higher dynamic input range.

The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true scope of the claims. For example, various implementations of each of the buffer amplifier, the link coupling element, and the leakage compensation element are possible. For example, the buffer amplifier may generate the desired offset for the SENSE node in a number of ways. The link coupling element may be implemented using a unidirectional circuit element such as a diode, a MOS transistor source follower, or a bipolar transistor emitter follower. The leakage compensation element can also be implemented in a number of ways. If anti-series diodes are used for the link-coupling elements, the anti-series diodes may have back-to-back cathodes or back-to-back anodes. The anti-series diode may also be implemented using various integrated circuit device structures, including structures in which the link-coupling element and the leakage compensation element share a co-buried diffusion region using a MTI structure.

In one form, a leakage compensation circuit includes: a buffer amplifier having an output and an input coupled to the sensing node; a link coupling element having an output and an input coupled to the output of the buffer amplifier, wherein the link coupling element is unidirectional in a direction from the input to the output thereof; and a leakage compensation element having a first current terminal coupled to the sense node, a control terminal coupled to an output of the link coupling element, and a second current terminal coupled to the reference voltage terminal.

According to one aspect, a buffer amplifier includes a single-ended non-inverting amplifier having a positive input coupled to a sense node, and an output coupled to an output of the buffer amplifier. According to this aspect, the buffer amplifier may further include: a variable offset generator coupled between the sensing node and one of the positive input of the differential amplifier and the negative input of the differential amplifier and having a control input for receiving the digital correction signal; and an offset circuit having an output coupled to the control input of the variable offset generator to provide a digital correction signal.

According to another aspect, the link coupling element includes a Metal Oxide Semiconductor (MOS) transistor having a drain coupled to the second reference voltage terminal, a gate coupled to the output of the buffer amplifier, and a source coupled to the control terminal of the leakage compensation element.

According to yet another aspect, the link coupling element includes a bipolar transistor having a collector coupled to the second reference voltage terminal, a base coupled to the output of the buffer amplifier, and an emitter coupled to the control terminal of the leakage compensation element.

According to yet another aspect, the leakage compensation element includes an anti-series diode having a first current terminal coupled to the sense node, a second current terminal coupled to the reference voltage terminal, and an intermediate terminal serving as a control terminal for the leakage compensation element, the intermediate terminal being coupled to the output of the link coupling element. According to this aspect, the anti-series diode may include a first PN diode having an anode coupled to the sensing node and a cathode forming an intermediate terminal of the anti-series diode, and a second PN diode having an anode coupled to the reference voltage terminal and a cathode coupled to the cathode of the first PN diode.

According to another aspect, the leakage compensation circuit further comprises a filter for compensating for a loop between the sense node and the first current terminal of the leakage compensation element.

In another form an integrated circuit has a leakage compensation circuit, the leakage compensation circuit comprising: a buffer amplifier having an output and an input coupled to the sensing node; a link coupling element having an output and an input coupled to the output of the buffer amplifier, wherein the link coupling element is unidirectional in a direction from the input to the output thereof; and a leakage compensation element having a first current terminal coupled to the sense node, a control terminal coupled to an output of the link coupling element, and a second current terminal coupled to the reference voltage terminal.

According to one aspect, the first current terminal of the leakage compensation element is formed in a first region of the integrated circuit, and the first region includes at least one semiconductor device formed in the first region.

According to another aspect, the leakage compensation element includes an anti-series diode having a first current terminal coupled to the sense node, a second current terminal coupled to the reference voltage terminal, and an intermediate terminal forming a control terminal of the leakage compensation element, the intermediate terminal coupled to the output of the link coupling element. According to this aspect, the anti-series diode may include a first PN diode having an anode coupled to the sensing node and a cathode forming an intermediate terminal of the anti-series diode, and a second PN diode having an anode coupled to the reference voltage terminal and a cathode coupled to the cathode of the first PN diode. In this case, the integrated circuit may further comprise a semiconductor region of the first conductivity type, wherein the semiconductor region forms a terminal region of both the first PN diode and the second PN diode. According to this aspect, the integrated circuit may further include a semiconductor region of the first conductivity type, wherein the semiconductor region forms a terminal region of the anti-series diode and a terminal of the other semiconductor device.

According to yet another aspect, the output of the link coupling element and the control terminal of the leakage compensation element are coupled together using a metal connection.

In another form a method of performing leakage compensation for leakage current flowing into or out of a sense node includes: buffering the voltage on the sensing node and providing a buffered voltage to the intermediate node in response to the buffering; unidirectionally coupling the buffered voltage to a control node; and biasing a leakage compensation element having a first current terminal coupled to the sense node and a second current terminal coupled to the reference voltage terminal by coupling a control terminal of the leakage compensation element to the control node.

According to one aspect, the buffering includes buffering a voltage on the sense node using a differential amplifier, and applying an offset to the differential amplifier.

According to another aspect, unidirectionally coupling the buffered voltage to the control node includes coupling the buffered voltage to the control node using a PN diode.

According to yet another aspect, unidirectionally coupling the buffered voltage to the control node includes coupling the buffered voltage to the control node using a Metal Oxide Semiconductor (MOS) transistor having a drain coupled to the second reference voltage terminal, a gate for receiving the buffered voltage, and a source coupled to the intermediate node.

According to yet another aspect, unidirectionally coupling the buffer voltage to the control node includes coupling a bipolar transistor having a collector coupled to the second reference voltage terminal, a base for receiving the buffer voltage, and an emitter coupled to the control node.

According to yet another aspect, an offset leakage compensation element includes an offset anti-series diode having a first current terminal coupled to a sense node, a second current terminal coupled to a reference voltage terminal, and an intermediate terminal coupled to a control node.

Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.