阅读说明：本技术 显示装置 (Display device ) 是由 花田明纮 伊藤友幸 于 2018-12-04 设计创作，主要内容包括：本发明的课题为,在使用了聚酰亚胺基板的显示装置中,抑制由基板带电引起的TFT的特性变动。本发明的概要为一种显示装置,在由树脂形成的基板(100)的一面,存在由氧化物半导体(107)形成的第一TFT与由第一多晶硅(102)形成的第二TFT,其特征在于,所述第一TFT与所述第二TFT形成于俯视观察时不同的部位,所述第二TFT与所述第一TFT相比,形成为在剖视观察时更靠近所述基板(100),所述氧化物半导体(107)具有沟道长度与沟道宽度,在所述氧化物半导体(107)与所述基板(100)之间存在第二多晶硅(50),该第二多晶硅(50)由与所述第一多晶硅(102)相同的材料形成,并形成在与形成有所述第一多晶硅(100)的层相同的层之上。(The present invention addresses the problem of suppressing variation in characteristics of TFTs caused by substrate charging in a display device using a polyimide substrate. The present invention is a display device including a substrate (100) made of a resin, and a first TFT formed of an oxide semiconductor (107) and a second TFT formed of first polysilicon (102) on one surface of the substrate, wherein the first TFT and the second TFT are formed at different positions in a plan view, the second TFT is formed closer to the substrate (100) than the first TFT in a cross-sectional view, the oxide semiconductor (107) has a channel length and a channel width, second polysilicon (50) is present between the oxide semiconductor (107) and the substrate (100), and the second polysilicon (50) is formed of the same material as the first polysilicon (102) and is formed on the same layer as a layer on which the first polysilicon (100) is formed.)

1. A display device having a first TFT formed of an oxide semiconductor and a second TFT formed of a first polysilicon on a substrate formed of a resin,

the first TFT and the second TFT are formed at non-overlapping positions in a plan view,

the second TFT is formed closer to the substrate than the first TFT in a cross-sectional view,

a second polysilicon is present between the oxide semiconductor and the substrate, is formed of the same material as the first polysilicon, and is formed over the same layer as the layer in which the first polysilicon is formed.

2. The display device of claim 1,

the length of the second polysilicon in the channel length direction of the oxide semiconductor is greater than the length of the oxide semiconductor in the channel length direction.

3. The display device of claim 1,

the width of the second polysilicon in the channel width direction of the oxide semiconductor is larger than the width of the oxide semiconductor in the channel width direction.

4. The display device of claim 1,

a metal layer formed of the same material as the gate electrode of the second TFT on the same layer as the gate electrode of the second TFT with an insulating film interposed therebetween,

the length of the metal layer in the channel length direction of the oxide semiconductor is smaller than the length of the oxide semiconductor in the channel length direction.

5. The display device of claim 1,

a metal layer formed of the same material as the gate electrode of the second TFT on the same layer as the gate electrode of the second TFT with an insulating film interposed therebetween,

the length of the metal layer in the channel length direction of the oxide semiconductor is smaller than the length of the second polysilicon in the channel length direction.

6. The display device of claim 1,

a metal layer formed of the same material as the gate electrode of the second TFT on the same layer as the gate electrode of the second TFT with an insulating film interposed therebetween,

the metal layer is supplied with a gate potential.

7. The display device of claim 1,

a metal layer formed of the same material as the gate electrode of the second TFT on the same layer as the gate electrode of the second TFT with an insulating film interposed therebetween,

the metal layer is supplied with a reference potential.

8. The display device of claim 1,

the second polysilicon is supplied with a reference potential.

9. The display device of claim 1,

the first TFT is a top gate.

10. The display device of claim 1,

the second TFT is a top gate.

11. A display device having a first TFT formed of an oxide semiconductor on a substrate formed of a resin,

a first conductive film is formed in a region overlapping with the oxide semiconductor in a plan view in contact with the substrate, a base film made of an inorganic material is formed over the first conductive film,

the oxide semiconductor has a channel length and a channel width,

the length of the first conductive film in the channel length direction is greater than the length of the oxide semiconductor in the channel length direction.

12. The display device of claim 11,

the width of the first conductive film in the channel width direction is larger than the width of the oxide semiconductor in the channel width direction.

13. The display device of claim 11,

the first conductive film is formed of a metal.

14. The display device of claim 11,

the first conductive film is applied with a reference potential.

15. The display device of claim 11,

a second TFT formed of polycrystalline silicon on the substrate at a portion not overlapping the first TFT in a plan view,

the second TFT is formed closer to the substrate than the first TFT in a cross-sectional view.

16. The display device of claim 11,

the display device has a portion overlapping with the polycrystalline silicon in a plan view, and a second conductive film formed of the same material as the first conductive film is formed between the substrate and the base film.

17. The display device of claim 11,

the polysilicon has a channel length and a channel width,

the length of the second conductive film in the channel length direction is smaller than the length of the polysilicon in the channel length direction.

18. The display device of claim 11,

the second conductive film is applied with a reference potential.

19. The display device of claim 15,

a metal film formed of the same material as a gate electrode of the second TFT over the same layer as the gate electrode of the second TFT is formed between the oxide semiconductor and the base film,

the length of the metal film in the channel length direction is smaller than the length of the oxide semiconductor in the channel length direction.

20. The display device of claim 19,

the metal film is supplied with a gate potential.

Technical Field

The present invention relates to a display device, and more particularly, to a flexible display device capable of bending a substrate.

Background

The organic EL display device and the liquid crystal display device can be used by making the display device thin and flexibly bent. In this case, the substrate for forming the element is formed of thin glass or thin resin.

In the organic EL display device, the organic light emitting layer is driven by a driving Transistor composed of a TFT (Thin Film Transistor). When noise intrudes into the driving transistor, the threshold value of the driving transistor changes, and accurate luminance can no longer be reproduced.

In the cited document 1, in an organic EL display device in which a driving transistor is formed using a top gate TFT, a metal thin film for shielding is used below the TFT in order to suppress variation in the threshold of the driving transistor due to external noise.

Disclosure of Invention

Problems to be solved by the invention

When the substrate of the organic EL display device is formed of a resin such as polyimide, a flexible organic EL display device can be formed. However, it is known that, in a substrate using a resin, luminance fluctuation occurs when the organic EL display device is operated for a long time as compared with the case of a glass substrate. It is considered that the luminance fluctuation is a result of a distribution of charges generated in the resin substrate due to a long-time operation and the influence of the charging of the resin in the vicinity of the driving transistor on the characteristics of the driving transistor.

TFTs formed of an oxide semiconductor have a feature that a leak current is small. Therefore, low-frequency driving is possible, and power consumption can be reduced. However, TFTs made of oxide semiconductors have a problem that they are susceptible to organic fixed charges on a substrate or the like.

In addition, when a TFT using an oxide semiconductor is used in a liquid crystal display device, the TFT is easily affected by a backlight. Therefore, a light-shielding layer needs to be provided.

Therefore, it is reasonable to use a TFT using LTPS for a peripheral driver circuit such as a scan line driver circuit and to use a TFT using an oxide semiconductor as a driver transistor or a switching transistor in a pixel region.

In the hybrid structure, a TFT using LTPS and a TFT using an oxide semiconductor are manufactured by sequential processes. In this case, it is necessary to adopt a structure in which the influence of charging, light shielding from a backlight, and the like are considered for both types of TFTs.

The present invention addresses the problem of realizing a structure that suppresses the effects of substrate charging, a structure that suppresses the effects of external light on TFTs, and a structure that can reasonably solve these problems in a hybrid structure, when a resin substrate is used.

Means for solving the problems

The present invention overcomes the above problems, and the representative means is as follows.

(1) A display device having a first TFT formed of an oxide semiconductor and a second TFT formed of a first polysilicon on a substrate formed of a resin, wherein the first TFT and the second TFT are formed at positions not overlapping in a plan view, the second TFT is formed closer to the substrate than the first TFT in the plan view, a second polysilicon is present between the oxide semiconductor and the substrate, and the second polysilicon is formed of the same material as the first polysilicon and formed on the same layer as the layer on which the first polysilicon is formed in a cross-sectional view.

(2) A display device having a first TFT formed of an oxide semiconductor on one surface of a substrate formed of a resin, wherein a first conductive film is formed in a region overlapping with the oxide semiconductor in a plan view, and a base film made of an inorganic material is formed over the first conductive film, wherein the oxide semiconductor has a channel length and a channel width, and wherein a length of the first conductive film in the channel length direction is larger than a length of the oxide semiconductor in the channel direction.

(3) The display device according to (2), wherein a second TFT made of polycrystalline silicon is formed on the substrate at a position different from the first TFT in a plan view, and the second TFT is formed closer to the substrate than the first TFT in a cross-sectional view.

Drawings

Fig. 1 is a plan view of an organic EL display device.

Fig. 2 is a sectional view of a display region of the organic EL display device.

Fig. 3 is an equivalent circuit of a pixel portion of the organic EL display device.

Fig. 4 is a cross-sectional view illustrating charging of the substrate.

Fig. 5 is a cross-sectional view illustrating the influence of charging of the substrate.

Fig. 6 is a cross-sectional view of the vicinity of the TFT of the comparative example.

Fig. 7 is a sectional view of the vicinity of the TFT of the present invention.

Fig. 8 is a sectional view showing a part of the manufacturing process of the present invention.

Fig. 9 is a plan view of the vicinity of the TFT of the present invention.

Fig. 10 is a sectional view of the vicinity of the TFT of embodiment 2.

Fig. 11 is a sectional view of the vicinity of the TFT of embodiment 2.

Fig. 12 is a sectional view of the vicinity of the TFT of embodiment 3 of example 2.

Fig. 13 is a sectional view of the vicinity of the TFT of embodiment 2, which is the 4 th mode.

Fig. 14 is a plan view of the liquid crystal display device.

Fig. 15 is a sectional view of a display region of the liquid crystal display device.

Fig. 16 shows an example of voltages applied to the scanning lines.

Detailed Description

Hereinafter, the present invention will be described in detail with reference to examples.

[ example 1 ]

Fig. 1 is a plan view of an organic EL display device having a flexible substrate 100 to which the present invention is applied. In the organic EL display device of fig. 1, a display region 10 and a terminal region 30 are present. In the display area 10, the scanning lines 11 extend in the lateral direction (x direction) and are arranged in the longitudinal direction (y direction). In addition, the video signal lines 12 extend in the longitudinal direction and are arranged in the lateral direction. Also, the power supply lines 13 extend in the longitudinal direction and are arranged in the lateral direction. Pixels 14 are formed in regions surrounded by the scanning lines 11, the video signal lines 12, or the power supply lines 13.

In fig. 1, a terminal area 30 is formed in a portion other than the display area 10, and a driver IC31 is mounted on the terminal area 30. The image signal is arranged (range) in the driver IC31 and supplied to the display region 10. A flexible wiring board 32 for supplying power and signals to the organic EL display device is connected to the terminal region 30.

In fig. 1, the scanning line driving circuit 20 is formed on both sides of the display region 10. Further, a current supply region 21 is formed above (on the upper side in the y direction) the display region 10. A current is supplied from the flexible wiring substrate 31 connected to the terminal region 30 to a current bus line, and the current bus line is wired to the current supply region 21 on the upper side (upper side in the y direction) of the display region 10. Then, a current is supplied from the current supply region 21 to each pixel 14 through the power supply line 13. This is to avoid concentration of the wiring on the lower side of the display region 10.

Fig. 2 is a cross-sectional view showing an example of a layer structure of a display region of the organic EL display device shown in fig. 1. In fig. 2, the glass substrate 90 is sometimes used as a support substrate, but in the present invention, it is removed after the flexible display device is completed. That is, since the resin substrate alone cannot pass through the process, in the manufacturing process, the elements of the organic EL display device are formed on the glass substrate, and after the organic EL display device is completed, the glass substrate 90 is removed by laser ablation or the like.

In fig. 2, a TFT substrate 100 formed of a resin is formed on a glass substrate 90. Polyimide was used as the resin. Polyimide has excellent properties as a substrate of a flexible display device due to mechanical strength, heat resistance, and the like. Hereinafter, the resin substrate will be described as a polyimide substrate.

The polyimide material containing polyamic acid is applied by a slit coater, a bar coater, an ink jet printer, or the like, fired to imidize and cure. The thickness of the polyimide substrate 100 is 10 μm to 20 μm. However, polyimide is more easily charged than glass. This phenomenon is presumed to be due to the fact that polyimide is not a perfect insulator such as glass, and therefore charges are moved by the potential of the electrode formed thereon.

In fig. 2, a base film 101 is formed on a TFT substrate 100. This is to prevent moisture and impurities derived from polyimide from contaminating the semiconductor layer 107 and the organic EL layer. The base film 101 is formed of a three-layer laminated film in which silicon nitride (SiN) is sandwiched between silicon oxide (SiO), for example. In addition, alumina (AlOx) is sometimes used.

A semiconductor layer 107 is formed over the base film 101. The semiconductor layer 107 is formed of, for example, an oxide semiconductor. The oxide semiconductor 107 can be formed at a temperature of about 350 ℃. The optically Transparent and Amorphous substance in the Oxide Semiconductor 108 is referred to as TAOS (Transparent Amorphous Oxide Semiconductor). Examples of TAOS include IGZO (Indium Gallium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnON (Zinc Oxide Nitride), and IGO (Indium Gallium Oxide). In the present invention, an example in which IGZO is used for the oxide semiconductor 107 will be described.

A gate insulating film 108 is formed to cover the semiconductor layer 107, and a gate electrode 109 is formed on the gate insulating film 108. The gate electrode 109 is formed of, for example, MoW, but when it is desired to reduce the resistance, a structure in which Al is sandwiched between Ti and the like is used. Thereafter, ion implantation (ion implantation) of Ar atoms or the like is performed using the gate electrode 109 as a mask, thereby forming a drain electrode 1071 and a source electrode 1072 in the semiconductor layer 107. In the semiconductor layer 107, a channel is formed directly below the gate electrode 109.

An interlayer insulating film 110 is formed to cover the gate electrode 109. A drain electrode 111 and a source electrode 112 are formed on the interlayer insulating film 110. A via hole 131 is formed in the interlayer insulating film 110 and the gate insulating film 108, the drain electrode 111 is connected to the drain 1071, a via hole 132 is formed, and the source electrode 112 is connected to the source 1072.

An organic passivation film 120 is formed to cover the drain electrode 111, the source electrode 112, and the interlayer insulating film 110. The organic passivation film 120 is formed of a transparent resin such as acrylic. The organic passivation film 120 also serves as a planarizing film, and is formed thick to 2 μm to 4 μm.

A reflective film 1211 and an anode 1212 are formed in a stacked manner on the organic passivation film 120. The stack of the reflective film 1211 and the anode 1212 is referred to as a lower electrode 121. The reflective film 1211 is formed of, for example, silver having a high reflectance, and the anode 1212 is formed of ITO (Indium Tin Oxide). In addition, a via hole 130 is formed in the organic passivation film 120 to connect the source electrode 112 and the lower electrode 121.

A bank (bank)122 is formed to cover the lower electrode 121. The dam 122 is formed of a transparent resin such as acrylic. The bank 122 functions to prevent the organic EL layer 123 formed on the lower electrode 121 from being broken (cut) by the end of the lower electrode 121 and to divide each pixel.

The organic EL layer 123 is formed on the via hole (hole) formed on the bank 120. The organic EL layer 123 is formed of a plurality of layers such as a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer, and each layer is a very thin film of about several nm to 100 nm.

An upper electrode (cathode) 124 is formed to cover the organic EL layer 123. The cathode is formed on the entire display region in common. The cathode 124 may be formed of a thin film of a metal such as silver, in addition to IZO (Indium Zinc Oxide), ITO (Indium tin Oxide), or the like, which is a transparent conductive film.

Then, in order to prevent moisture from entering from the cathode 124 side, the cathode 124 is covered with SiN by CVD to form a protective film 125. Since the organic EL layer 123 is not heat-resistant, CVD for forming the protective film 125 is formed by low-temperature CVD at around 100 ℃. In the protective film 125, a transparent resin film such as acrylic resin may be laminated for mechanical protection.

Since the top emission type organic EL display device has the reflective electrode 1211, the screen reflects external light. To prevent this, a polarizing plate 127 is disposed on the surface to prevent reflection of external light. The polarizing plate 127 has an adhesive 126 on one surface thereof, and is bonded to the organic EL display device by being pressed against the protective film 125. The adhesive 126 has a thickness of about 30 μm, and the polarizer 127 has a thickness of about 100 μm.

After the flexible display device is formed on the glass substrate in this manner, the interface between the TFT substrate 100 made of polyimide and the glass substrate 90 is irradiated with laser light, and the glass substrate 90 is removed from the TFT substrate 100. Thereby, a flexible display device having a resin substrate is completed.

Fig. 3 and 4 are diagrams illustrating a mechanism of source current fluctuation in the driving TFT, taking the organic EL display device as an example. Fig. 3 is an example of an equivalent circuit of a pixel portion of the organic EL display device. In fig. 3, the scanning line 11 extends in the lateral direction. The cathode line 124 extends in the lateral direction, but this is an expression in an equivalent circuit, and the cathode 124 is formed over the entire surface of the display region 10 as described with reference to fig. 2. The video signal lines 12 extend in the longitudinal direction, and the power supply lines 13 extend in the longitudinal direction. The region surrounded by the scanning line 11 and the video signal line 12 or the power supply line 13 becomes a pixel.

In fig. 3, the switching transistor T1 has a drain connected to the video signal line 12 and a gate connected to the scanning line 11. The drain of the driving transistor T2 is connected to the power supply line 13, and the source is connected to the organic EL layer EL. The gate of the driving transistor T2 is connected to the source of the switching transistor T1. Further, a storage capacitor Cs is connected between the gate and the source of the driving transistor T2.

In fig. 3, when the switching transistor T1 receives a scanning signal, a video signal is stored in the storage capacitor Cs through the switching transistor, and the driving transistor T2 supplies a current to the organic EL layer EL in accordance with the potential of the charge stored in the storage capacitor Cs. The transistor illustrated in fig. 2 is the driving transistor T2 in fig. 3. Since the one electrode of the driving transistor T2 is one electrode of the storage capacitor Cs, the area thereof is large, and the gate electrode 109 of the driving transistor T2 is greatly affected by the polyimide constituting the TFT substrate 100.

Fig. 4 is a schematic cross-sectional view of the vicinity of the drive transistor. In fig. 4, a polyimide substrate 100 is formed on a glass substrate 90, and a base film 101 is formed thereon. A semiconductor layer 107 is formed over the base film 101. The semiconductor layer 107 is formed of, for example, an oxide semiconductor. A gate insulating film 108 is formed on the semiconductor layer 107, and a gate electrode 109 is formed thereon. In the semiconductor layer 108, a portion directly below the gate electrode 109 serves as a channel, and the other portion serves as a source or a drain. The gate electrode 109 of the driving transistor extends to other regions to become one electrode of the storage capacitor Cs.

The organic EL display device continuously displays images by continuously applying a dc voltage to the gate electrode 109. The voltage application to the gate electrode 109 means that a dc voltage is continuously applied to one electrode of the storage capacitor Cs at the same potential. The area of the electrode of the storage capacitor Cs is larger than the area of the gate electrode 109.

Then, as shown in fig. 4, a part of the polyimide as the TFT substrate 100 is charged. The charged charges move from other positions of the polyimide substrate 100, for example, portions of the TFTs. In fig. 4, it is shown that negative charges move to one electrode side of the storage capacitor by the resistance Rpi of the polyimide, and as a result, the polyimide substrate 100 near the TFT is positively charged. Then, the source current of the TFT fluctuates due to this influence. Such a variation in the characteristics of the TFT due to the influence of the charging of the substrate 100 is particularly significant in a TFT using an oxide semiconductor.

The TFT using the oxide semiconductor 107 has a feature that a leak current is small. This means that the potential of the pixel electrode can be stably maintained for a long time. Therefore, by using the oxide semiconductor 107 for the TFT, low-frequency driving can be performed, and power consumption can be reduced. However, the mobility of the oxide semiconductor 107 may be insufficient to constitute a peripheral driver circuit.

LTPS mobility, on the other hand, is large. However, LTPS has a problem of a larger leakage current than an oxide semiconductor. Therefore, it is reasonable to use TFTs made of an oxide semiconductor for driving TFTs or switching TFTs in pixels and TFTs made of LTPS for peripheral driver circuits. This structure is referred to as a hybrid configuration.

Fig. 5 is a cross-sectional view showing a structure in the vicinity of a TFT in the case where the TFT including the oxide semiconductor 107 and the TFT including the LTPS102 are formed on the same substrate 100. Since the TFT using the oxide semiconductor 107 is formed in the display region and the TFT using the LTPS102 is formed in the peripheral driver circuit, two TFTs are actually disposed separately, but in fig. 5, the TFT using the LTPS102 and the TFT using the oxide semiconductor 107 are described adjacently in order to facilitate understanding of the layer structure.

In fig. 5, the left side is a TFT made of LTPS102, and the right side is a TFT made of an oxide semiconductor 107. In fig. 5, a TFT substrate 100 made of polyimide is formed on a glass substrate 90, and a base film 101 is formed thereon. The structure of the base film 101 is as illustrated in fig. 2. A semiconductor layer 102 made of LTPS is formed over the base film 101. LTPS first covers a-Si on the base film 101 by CVD, and the a-Si film is irradiated with excimer laser light to be converted into polysilicon. The LTPS is formed to a thickness of about 50 nm.

A first gate insulating film 103 is formed covering the LTPS102, and a first gate electrode 104 is formed thereon. The gate electrode 104 is formed of a metal or alloy such as Mo or MoW, or a laminated film such as Ti — Al — Ti. In fig. 5, a channel is formed in a portion of the LTPS102 corresponding to the gate electrode 104, and a drain and a source are formed on both sides thereof.

A first interlayer insulating film 105 made of, for example, silicon nitride (SiN) and a second interlayer insulating film 106 made of silicon oxide (SiO) are formed so as to cover the first gate electrode 104. In order to stabilize the characteristics of a TFT formed of LTPS, the first interlayer insulating film 105 is preferably formed of SiN. On the other hand, when the oxide semiconductor 107 formed on the right side of fig. 5 is in contact with SiN, the characteristics vary due to hydrogen supplied from SiN. To prevent this, the second interlayer insulating film 106 is formed of SiO.

On the right side of fig. 5, an oxide semiconductor 107 is formed of IGZO, for example, on the second interlayer insulating film 106. The thickness of the oxide semiconductor 107 is, for example, 10nm to 100 nm. A second gate insulating film 108 is formed to cover the oxide semiconductor 107. Further, a second gate electrode 109 is formed over the second gate insulating film 108 over the oxide semiconductor 107. In the oxide semiconductor 107, a channel is formed in a portion corresponding to the second gate electrode 109, and a drain electrode 1071 and a source electrode 1072 are formed on both sides thereof.

A third interlayer insulating film 110 made of SiO is formed so as to cover the second gate electrode 109. Since the third interlayer insulating film 110 is formed in the vicinity of the oxide semiconductor 107 with the second gate insulating film 108 interposed therebetween, it is formed of SiO to supply oxygen to the oxide semiconductor 107, and thus the characteristics of the oxide semiconductor 107 can be stabilized.

In the TFT on the left side of fig. 5, through holes 115 and 116 are formed in five insulating films, that is, the third interlayer insulating film 110, the second gate insulating film 108, the second interlayer insulating film 106, the first interlayer insulating film 105, and the first gate insulating film 103, in order to connect the drain electrode 111 and the source electrode 112. In the TFT on the right side, through holes 117 and 118 are formed in the third interlayer insulating film 110 and the second gate insulating film 108 to connect the drain electrode 113 and the source electrode 114.

In fig. 5, the vias 115, 116 for the LTPS102 and the vias 117, 118 for the oxide semiconductor 107 are formed simultaneously. When the LTPS102 via hole is formed, hydrofluoric acid (HF) cleaning is performed. In this case, in order to prevent the oxide semiconductor 107 from disappearing through the through-hole for the oxide semiconductor 107 to be cleaned at the same time, an etching stopper made of metal or the like may be formed in the portion of the oxide semiconductor 107 corresponding to the through-holes 117 and 118.

In fig. 5, when the display device is operated, as described in fig. 3 and 4, electric charges are induced in the TFT substrate 100 corresponding to the TFT formed of the oxide semiconductor 107. This charge causes the characteristics of the TFT including the oxide semiconductor 107 to fluctuate. In fig. 4, only the base film 101 is present under the oxide semiconductor 107, and in fig. 5, four layers of the second interlayer insulating film 106, the first interlayer insulating film 105, the first gate insulating film 103, and the base film 101 are present under the oxide semiconductor 107, but the phenomenon of electric charges being induced on the TFT substrate 100 is the same.

Fig. 6 is a cross-sectional view of a TFT as a comparative example for coping with this problem. In fig. 6, the structure of the TFT including the LTPS102 on the left side is the same as that described in fig. 5. In the TFT on the right side of fig. 6, a shield layer 60 is formed below an oxide semiconductor 107 with a second interlayer insulating film 106 and a first interlayer insulating film 105 interposed therebetween. The shield layer 60 is connected to, for example, Ground (GND) potential, and charges induced in the TFT substrate 100 are shielded by the shield layer 60. In addition, the shield layer 60 may become a bottom gate electrode (third gate electrode) in the TFT made of an oxide semiconductor by applying a gate voltage.

The shield layer 60 is formed of the same metal material as the first gate electrode 104 at the same time as the first gate electrode 104. The shield layer 60 made of a metal also functions as a light-shielding film for the oxide semiconductor 107 against light from the back surface. On the other hand, if a sufficient shielding effect is to be obtained by the shielding layer 60, a certain area is required.

When the area of the shield layer 60 is increased, large parasitic capacitances Cgd and Cgs are generated between the drain 1071 and the source 1072 of the oxide semiconductor 107 as shown in fig. 6. If the shield layer 60 is used as a bottom gate, the parasitic capacitances Cgd and Cgs cause a problem such as a gate voltage being flown into the pixel electrode or the anode, and a problem such as a decrease in the operating speed of the TFT when the ground potential (GND) is applied to the shield layer 60.

Fig. 7 is a sectional view showing the structure of example 1 of the present invention which deals with such a case. In fig. 7, the structure of the TFT including the LTPS102 on the left side is the same as the structure described in fig. 5 and 6. The TFT formed of the oxide semiconductor 107 on the right side in fig. 7 is different in structure from that in fig. 6.

In fig. 7, the third gate electrode 60 (shield layer 60) formed below the oxide semiconductor 107 has the minimum area that functions as a bottom gate and a light-shielding layer facing the channel of the oxide semiconductor 107. Thus, there is no sufficient shielding effect against the charges induced in the TFT substrate 100. However, since the third gate electrode 60 has a small area, parasitic capacitances Cgd and Cgs formed between the third gate electrode 60 and the drain 1071, the source 1072, and the like of the oxide semiconductor can be minimized.

In fig. 7, a shield layer 50 formed of LTPS has a function of shielding charges induced at the TFT substrate. The shield layer 50 is formed simultaneously when the LTPS102 for the TFT on the left side in fig. 7 is formed. The shield layer 50 is formed of LTPS, but is imparted with conductivity by ion implantation-based doping.

The shield layer 50 is applied with a ground potential (GND), for example. Here, the ground potential is a reference potential and is not necessarily a ground (earth) potential. That is, the reference potential may be a cathode potential or the like.

As shown in fig. 7, a first gate insulating film 103 is present between the shield layer 50 made of LTPS and the drain electrode 1071 and the source electrode 1072 in the oxide semiconductor 107, in addition to the first interlayer insulating film 105 and the second interlayer insulating film 106. Accordingly, the parasitic capacitance can be reduced. On the other hand, in order to reduce the parasitic capacitance with the oxide semiconductor 107, the area of the shield layer 50 can be increased, thereby providing a sufficient shield effect.

Fig. 8 is a sectional view showing a process of forming the shield layer 50 made of LTPS. The shield layer 50 composed of LTPS is patterned at the same time as the LTPS102 when the LTPS tft is formed. After that, the first gate insulating film 103 covers the TFT-LTPS 102 and the shield layer 50 with the LTPS. Thereafter, in order to form a channel portion in the LTPS102, a resist 400 is formed in a portion of the LTPS102 corresponding to the channel.

Then, the LTPS except for the portion where the resist 400 is present is doped with phosphorus (P), boron (B), or the like by ion implantation to impart conductivity. Fig. 8 is a cross-sectional view showing a state where a drain 1021 and a source 1022 are formed in the LTPS by ion implantation. As shown in fig. 8, the drain 1021 and the source 1022 of the TFT are formed, and the LTPS constituting the shield layer 50 is provided with conductivity.

The ion implantation shown in FIG. 8 is, for example, doping 1 × 10¹⁴ions/cm²Phosphorus (P) of (a). As shown in fig. 8, the shield layer 50 of the present invention does not require an additional step to be formed.

Fig. 9 is a plan view of a TFT formed of the oxide semiconductor 107. In fig. 9, a shield layer 50 made of LTPS is formed in the lowermost layer. Above the shield layer 50, there is a third gate electrode 60 constituting a bottom gate, on which an oxide semiconductor 107 is formed. In fig. 9, the lateral direction (x direction) is the channel length direction, and the longitudinal direction (y direction) is the channel width direction.

As shown in fig. 9, the width w2 of the shield layer 50 in the lateral direction is greater than the width w1 of the third gate electrode in the lateral direction. In fig. 9, the width w3 in the lateral direction of the oxide semiconductor 107 is larger than the width w2 of the shield layer 50, but as a shielding effect, the width w2 of the shield layer 50 is preferably larger than the width w3 in the lateral direction of the oxide semiconductor 107. The width w5 of the shield layer 50 in the longitudinal direction is larger than the width w4 of the oxide semiconductor 107. That is, the shield layer 50 made of LTPS is formed farther from the oxide semiconductor 107 than the third gate electrode 60, and thus the area can be increased.

In fig. 6, when the bottom gate 60 is not required or when the bottom gate 60 serving as a light shielding film is not required, the third gate electrode 60 in fig. 7 can be omitted.

As described above, according to the present invention, by forming the shield layer 50 from LTPS, the TFT using the oxide semiconductor 107 can be prevented from being affected by charges induced in the substrate, and an increase in parasitic capacitance due to the formation of the shield layer can be suppressed.

[ example 2 ]

Fig. 10 is a sectional view showing embodiment 2 of the present invention. In embodiment 1, as a shield against charges induced in the TFT substrate, LTPS is used. In embodiment 1, since three layers of the second interlayer insulating film 106, the first interlayer insulating film 105, and the first gate insulating film 103 are present between the oxide semiconductor 107 and the shield layer 50, parasitic capacitance can be suppressed.

The structure of embodiment 2 shown in fig. 10 further reduces the parasitic capacitance between the shield layer 70 and the oxide semiconductor 107 by forming the layer 70 for shielding under the base film 101. In fig. 7, a shielding layer 70 formed of a conductive material is formed under a base film 101. The conductive material is preferably a metal, and the same material as the gate electrode can be used as the metal.

In fig. 10, since the second interlayer insulating film 106, the first interlayer insulating film 105, the first gate insulating film 103, and the base film 101 are present between the oxide semiconductor 107 and the shield layer 70, the distance between the oxide semiconductor 107 and the shield layer 70 can be further increased as compared with the case of embodiment 1. Further, since the base film 101 is formed of three layers of SiO/SiN/SiO in many cases, the distance can be further increased.

When the shield layer 70 is formed of a metal, it can function as a light shielding film. When the thickness of the shield layer 70 is, for example, about 50nm, a sufficient shielding effect can be obtained. On the other hand, when the light-shielding film functions as a light-shielding film, it is preferably about 100 nm.

The oxide semiconductor 107 has a channel length and a channel width, and the length of the shielding layer 70 in the channel length direction is preferably larger than the length of the oxide semiconductor 107 in the channel length direction. In addition, the width of the shield layer 70 in the channel width direction is preferably larger than the width of the oxide semiconductor 107 in the channel width direction.

Fig. 11 is a sectional view showing embodiment 2 of embodiment 2. The shielding layer 70 in this embodiment is formed of a metal, and has a light shielding effect. Therefore, in the case where the TFT including the oxide semiconductor 107 does not require a bottom gate, the third gate electrode 60 having a light shielding effect can be omitted.

In fig. 11, only the shield layer 70 is present below the oxide semiconductor 107 with an insulating layer interposed therebetween. Thus, the parasitic capacitance can be further reduced as compared with the case of fig. 10. The structure of the shield layer 70 is the same as that illustrated in fig. 10.

Fig. 12 is a sectional view showing embodiment 3 of example 2. Fig. 12 is different from fig. 10 in that a light shielding film 71 is formed below the LTPS 102. The LTPS102 is also affected by the electrification in the TFT substrate 100. In addition, regarding the LTPS102, a photocurrent based on light from the back surface is also generated. In fig. 12, a shield layer 71 having both a shielding effect against electric charges generated in the TFT substrate 100 and a light shielding effect is formed also for the LTPS 102.

In fig. 12, the width of the shield layer 71 is formed to an area of such a degree as to cover the channel of the LTPS102 from below. This is for shielding of the channel portion and a light shielding effect of the channel portion. On the other hand, in a plan view, the overlap between the shield layer 71 and the drain 1021 and the source 1021 of the LTPS is reduced, and the occurrence of parasitic capacitance is prevented.

Fig. 13 is a sectional view showing the 4 th mode of example 2. Fig. 13 is different from fig. 11 in that a light shielding film 71 is formed below the LTPS 102. The other structure is the same as that of fig. 11. The structure of the light shielding film 71 in fig. 13 is the same as the structure of the light shielding film 71 illustrated in fig. 12. With the structure of fig. 13, the influence of charging in the TFT substrate 100 can be reduced not only for the oxide semiconductor 107 but also for the LTPS 102.

[ example 3 ]