阅读说明：本技术 基于冗余的信息产生数据流的系统 (System for generating data stream based on redundant information ) 是由 马库斯·韦德纳 于 2019-01-14 设计创作，主要内容包括：本发明涉及一种基于冗余的信息产生数据流的系统。所述系统包括第一控制器、第二控制器和电路。所述第一控制器设置用于经由第一数据输出端输出第一数据的第一部分。所述第二控制器设置用于经由第二数据输出端输出第二数据的第二部分。所述电路设置用于将经由第一和/或第二数据输出端输出的数据组合成数据流。第一控制器设置用于至少读入组合后的数据流的第二数据的第二部分。第二控制器设置用于至少读入组合后的数据流的第一数据的第一部分。第一控制器设置用于将读入的第二数据的第二部分与第一数据的第二部分比较,并且当比较得出偏差时,中止第一数据输出端的数据输出和/或阻止数据流的继续输送。第二控制器设置用于将读入的第一数据的第一部分与第二数据的第一部分比较,并且当比较得出偏差时,中止第二数据输出端的数据输出和/或阻止数据流的继续输送。(The invention relates to a system for generating a data stream based on redundant information. The system includes a first controller, a second controller, and a circuit. The first controller is arranged to output a first portion of the first data via the first data output. The second controller is arranged to output a second part of the second data via the second data output. The circuit is provided for combining data output via the first and/or second data output into a data stream. The first controller is arranged for reading in at least a second part of the second data of the combined data stream. The second controller is arranged for reading in at least a first part of the first data of the combined data stream. The first controller is provided for comparing the second part of the second data read in with the second part of the first data and, if the comparison yields a deviation, for interrupting the data output at the first data output and/or for preventing further transport of the data stream. The second control unit is provided for comparing the first part of the first data read in with the first part of the second data and, if the comparison yields a deviation, for stopping the data output at the second data output and/or for preventing further transport of the data stream.)

1. A system (10) for generating a data stream based on redundant information, comprising:

a first controller (12) having a first data output (12a), wherein the first controller (12) is arranged for outputting a first portion of first data via the first data output (12 a);

a second controller (14) having a second data output (14a), wherein the second controller (14) is arranged for outputting a second portion of second data via the second data output (14 a); and

a first circuit (16) which is connected to the first data output (12a) and the second data output (14a), wherein the first circuit (16) is provided for combining data which are output via the first data output (12a) and/or the second data output (14a) into a data stream; wherein the content of the first and second substances,

the first controller (12) is provided for reading in at least a second part of the second data of the combined data stream;

the second controller (14) is arranged for reading in at least a first part of the first data of the combined data stream;

the first controller (12) is provided for comparing a second part of the second data read in with a second part of the first data and, if the comparison yields a deviation, for interrupting the data output via the first data output (12a) and/or for preventing further transport of the data stream; and is

The second control unit (14) is provided for comparing the first part of the first data read in with the first part of the second data and, if the comparison yields a deviation, for interrupting the data output via the second data output (14a) and/or for preventing further transport of the data stream.

2. The system (10) according to claim 1, wherein the first data and the second data have redundant information.

3. The system (10) according to claim 1 or 2, wherein the data stream has a second part of the first data and a first part of the second data when the comparison does not result in a deviation.

4. The system (10) according to claim 3, wherein the first data is consistent with the second data when the comparison yields no deviation.

5. The system (10) according to one of claims 1 to 4, wherein the controllers (12, 14) are synchronized in such a way that the first portion of the first data and the second portion of the second data are not output at the same time.

6. System (10) according to one of claims 1 to 5, wherein the second controller (14) is arranged for synchronizing with the first controller by means of a read-in data stream and for outputting a second part of the second data via the second data output (14a) after the first controller (12) outputs the first part of the first data via the first data output (12 a).

7. The system (10) as claimed in one of claims 1 to 6, wherein the first circuit (16) is constructed as a logic circuit.

8. The system (10) as claimed in one of claims 1 to 7, wherein the first circuit (16) is constructed as a non-clocked logic circuit.

9. The system (10) of claim 7 or 8, wherein the logic circuit has logic gates.

10. The system (10) as claimed in one of claims 1 to 9, wherein a first data input (12b) of the first controller (12) and a second data input (14b) of the second controller (14) are connected via a second circuit (22) to a data output (16c) of the output data stream of the first circuit (16) and to a data output of a third controller (18) for a communication connection, in particular via a bus connection, wherein the second circuit (22) enables data to be received via the third controller (18) and a partial data stream to be read in.

11. A method (10) of generating a data stream based on redundant information, comprising:

generating (28), by the first controller, first data based on the first information;

generating (30), by a second controller, second data based on second information, wherein the second information partially or completely corresponds to the first information;

arranging (32) a first part of the first data and a second part of the second data to produce a data stream;

reading in (34) at least a second portion of second data of the data stream by the first controller;

reading (36) at least a first part of first data of a data stream by the second controller; and

checking (38) the correctness of the read-in data, wherein the checking comprises comparing the first part of the read-in first data with a first part of the second data and comparing the second part of the read-in second data with a second part of the first data.

Technical Field

The invention relates to a system for generating a data stream on the basis of redundant information.

Background

Systems are known from the prior art in which safety-relevant information about unreliable transmission paths is transmitted and errors are checked on the receiver side. In this case, redundant communication devices are provided on the transmitter side and/or on the receiver side, which monitor one another, for example, by cyclically switching and comparing the calculation results.

Disclosure of Invention

In this respect, the invention enriches the prior art in that the communication device according to the invention alternately transmits safety-relevant information about a common transmission path and monitors the transmission path at the transmission means, wherein the data of the two communication devices complement each other in such a way that, when the two communication devices transmit in cooperation, only effective communication takes place and the communication of the two communication devices can be stopped by causing the two communication devices to cease their transmission cooperation.

The system according to the invention for generating a data stream on the basis of redundant information comprises a first controller having a first data output, wherein the first controller is provided for outputting a first part of first data via the first data output, a second controller having a second data output, wherein the second controller is provided for outputting a second part of second data via the second data output, and a first circuit which is connected to the first data output and to the second data output. The first circuit is provided for combining data output via the first and/or second data output into a data stream. The first controller is arranged for reading in at least a second part of the second data of the combined data stream. The second controller is arranged for reading in at least a first part of the first data of the combined data stream. The first controller is provided for comparing the second part of the second data read in with the second part of the first data and, if the comparison yields a deviation, for interrupting the data output at the first data output and/or for preventing further transport of the data stream. The second control unit is provided for comparing the first part of the first data read in with the first part of the second data and, if the comparison yields a deviation, for stopping the data output at the second data output and/or for preventing further transport of the data stream.

The term "controller" as used in the description and in the claims is understood here to mean, in particular, an electronic circuit which is provided for reading in, processing or outputting an analog signal and/or a digital signal in a clock of a clock signal. Furthermore, the term "data output" as used in the description and claims is to be understood in particular as an electrical interface, on which predefined levels can be output, a series of levels representing the data to be output. Furthermore, the term "circuit" as used in the description and in the claims is to be understood in particular as an arrangement in which electrical and/or electronic components are coupled to correspond to a function. Furthermore, the concept of "data stream" as used in the description and in the claims is understood in particular to mean a predefined sequential order of levels, which represent data.

Preferably, the first data and the second data have redundant information.

The term "redundant information" used in the description and the claims is understood here to mean, in particular, information that can be (unambiguously) mapped to one another.

When the comparison yields no deviation, it is preferred that the data stream has a second part of the first data and a first part of the second data.

When the comparison yields no deviation, the first data preferably corresponds to the second data.

Preferably, the controller is synchronized such that the first portion of the first data and the second portion of the second data are not output at the same time.

The second controller is preferably provided for synchronizing with the first controller by means of the read-in data stream and for outputting a second part of the second data via the second data output after the first controller has output the first part of the first data via the first data output.

The first circuit is preferably designed as a logic circuit.

The first circuit is preferably designed as a non-clocked logic circuit.

The logic circuit preferably has logic gates.

The first data input of the first controller and the second data input of the second controller are preferably connected via a second circuit to the data output of the output data stream of the first circuit and to the data output of a third controller for a communication connection, in particular via a bus, wherein the second circuit enables the reading in of a partial data stream via the third controller and the reception of data.

The method for generating a data stream based on redundant information according to the present invention comprises: generating first data by a first controller based on the first information; generating second data by a second controller based on second information, wherein the second information partially or completely corresponds to the first information;

arranging a first portion of the first data and a second portion of the second data to produce a data stream; reading in at least a second portion of second data of the data stream by the first controller; reading in at least a first portion of first data of the data stream by a second controller; and checking the correctness of the read data, wherein the checking comprises comparing the first part of the read first data with the first part of the second data and comparing the second part of the read second data with the second part of the first data.

Drawings

The invention will be explained in the following in a detailed description by means of embodiments, wherein reference is made to the appended drawings, in which:

fig. 1 shows a system according to a first embodiment;

FIG. 2 illustrates the combined data flow;

FIG. 3 shows a system according to a second embodiment, an

Fig. 4 shows a flow chart of a method for generating a data stream based on redundant information.

Identical and functionally similar elements are denoted by the same reference numerals in the figures herein.

Detailed Description

Fig. 1 shows a system 10 having a first controller 12 and a second controller 14, which is connected to a bus controller 18 via a first circuit 16. The first line 16 has two data inputs 16a, 16B, the first data input 16a being connected to the data output 12a of the first controller 12 by means of a data line a (for example a conductor circuit or a wire) and the second data input 16B being connected to the data output 14a of the second controller 14 by means of a data line B (for example a conductor circuit or a wire). The data line A, B is grounded via resistors 20a, 20b (pull-down resistors).

The first circuit 16 also has a data output 16c, on which the result of the logical operation is output. The logical operation is applied to the logic levels present at the data inputs 16a, 16b so that the logic level output at the data output 16c results from the logic levels present at the data inputs 16a, 16 b. As shown in fig. 1, a bus controller 18 is connected to a data output 16c of the first circuit 16 by means of a data line G. It is to be understood, however, that instead of the bus controller 18, another communication partner device may also be connected to the data output 16c of the first circuit 16.

Both controllers 12, 14 are supplied with redundant information during error-free operation and are provided for transmitting said information to the bus controller 18. For example, as is symbolized by dashed lines in fig. 1, the two controllers 12, 14 can be connected to a common information or data source, for example one or more sensors, by means of a data line E. The controllers 12, 14 are further arranged to derive/calculate from the information/data first and second data which are identical or differ in a predetermined manner in error-free operation.

Fig. 2 illustrates for this purpose the process of combining the parts of the identical first and second data present in the controllers 12, 14 into a data stream. Here, the data in the controllers 12, 14 is divided into respective portions (e.g., into constant size data words D1-D6). As illustrated in fig. 2, a data section (or a data word in fig. 2) is accordingly always transmitted from only one of the controllers 12, 14 to the first circuit 16. The data segments are combined again by the circuit 16 into a continuous (gapless) data stream which, in error-free operation, corresponds both to the first data and to the second data. If one of the controllers 12, 14 is transmitting data, the other controller 12, 14 outputs an idle level at the data output 12a, 14a in error-free operation. In the embodiment shown in fig. 1, the idle level corresponds to a recessive logic level, i.e., a logic 1, wherein it is to be understood that an inverted logic with an or connection and a pull-up resistance may also be used.

Thus, an efficient data flow is produced only by the cooperation of the two controllers 12, 14. Here, it is to be understood that the data stream may in principle be formed by any number of segments (parts) which are alternately provided by the controllers 12, 14. Further, it is to be understood that the controllers 12, 14 are preferably synchronized. The synchronization can take place, for example, via a dedicated clock line or via a read-back data stream.

For reading back the data stream, the system 10 has a second circuit 22 (or read-back line), wherein the first data input 12b of the first controller 12 and the second data input 14b of the second controller 14 are connected via the second circuit 22 to the data output 16c of the first circuit 16. As shown in fig. 1, the second circuit 22 has a data output 22c on which the result of a logical operation is output, which logical operation is applied to the logic levels present at the data inputs 22a, 22b of the second circuit 22. The first data input 22a is connected to the data line G or the data output 16c of the first circuit 16, and the second data output 22b is connected to the data output of the bus controller 18 (data line H).

If data are transmitted to bus controller 18 via first circuit 16, bus controller 18 outputs an idle level at data output 18a, so that the logic level output at data output 22c of second circuit 22 corresponds to the logic level present at data input 22 a. The second circuit 22 enables data to be received from the bus controller 18 if no data is transmitted to the bus controller 18 via the first circuit 16.

For example, the bus controller 18 can be connected via a data line F to a bus via which the bus controller 18 transmits data to other bus subscriber devices or receives data from other bus subscriber devices. Thus, bi-directional communication is possible via the circuits 16, 22. In the case of bidirectional communication, for example, data telegrams can be exchanged, wherein the data telegrams generated by the two controllers 12, 14 in cooperation are transmitted via the first circuit 16 (and the bus controller 22) to the communication partner device, which itself responds with a response telegram, which is transmitted via the second circuit 22 to the two controllers 12, 14.

If data are transmitted to the bus controller 18 via the first circuit 16, the controllers 12, 14 read in at least the part of the combined data stream generated by the respective other controller 12, 14 and check the correctness of the read-in data. Upstream cross-traffic can thus be avoided. If an error is determined in the read-in data, the respective controller 12, 14 (i.e. the controller 12, 14 determining the error) can suspend the output of the data via the first data output 12a, 14 a. Thereby, the data output on the data output 16c of the first circuit 16 (or the data stream segment output on the data output 16c of the first circuit 16) can be forced to no longer correspond to the predetermined format and thus an error finding at the receiver side can be achieved.

For example, the bus controller 18 can check the consistency of the received data stream with the data frame format or the data telegram format or can ascertain the reliability of one or more data telegrams contained in the data stream by means of redundant check values calculated over the entire data frame or the entire data telegram. In order to recognize errors as early as possible, a data character containing a check value may be transmitted first.

Alternatively or additionally, the respective controller 12, 14 (i.e. the error-determining controller 12, 14) can block the output of data via the data output 16c of the first circuit 16 in that instead of the idle level a dominant logic level, which is opposite to the idle level, is output at the data output 12a, 14a of the respective controller 12, 14, which logic level covers all recessive logic levels of the other controller 12, 14, whereby the data output at the data output 16c of the first circuit 16 (or the data stream segment output at the data output 16c of the first circuit 16) can likewise be forced not to (again) correspond to the predetermined format (and errors can be found on the receiver side).

Furthermore, it is also possible to prevent data output via the data output 16c of the first circuit 16 when one controller 12, 14 is switched into a safe state (for example on the basis of an external or internal error), by switching the resistors 24a, 24b in such a way that, when one controller 12, 14 is deactivated, an explicit signal level is generated which prevents the communication of the remaining controllers 12, 14. Thus, preventing the data from being transmitted via the first circuit 16 also prevents the data from being transmitted via the second circuit 22, since in this state a logic level is dominant at the first data input 22 a. Conversely, if, in error-free operation, for example, a response of the communication partner device is awaited, the transmission of data via the second circuit 22 can be effected by applying a recessive logic level to the first data input 22 a.

Fig. 3 shows a modified embodiment of the system 10. This system differs from the system 10 shown in fig. 1 in that two separate Y-shaped data lines are provided instead of the second circuit 22. A Y-data line connects the data output 16c of the first circuit 16 to the readback inputs of the controllers 12, 14, and a second Y-data line connects the data output of the bus controller 18 to the data inputs 12d, 14d of the controllers 12, 14 for transmitting data from the bus controller 18 to the controllers 12, 14. This enables data to be output and read in by the controllers 12, 14 independently of each other (and therefore simultaneously).

The system 10 shown in fig. 3 differs from the system 10 shown in fig. 1 in that the first circuit 16 is extended with a function monitor 26 ("Watchdog"). The function monitor 26 is connected to the signal outputs 12c, 14c of the controllers 12, 14, which enable the function monitor 26 to be controlled with a signal which causes the function monitor 26 to allow data to be transmitted from the controllers 12, 14 to the bus controller 18 when the system 10 is operating without error. When one of the controllers 12, 14 fails or is replaced in a safe state (for example on the basis of an external or internal error) and therefore no (re) signal for activating the function monitor 26 is output, the control monitor 26 prevents data from being transmitted to the bus controller 18.

Fig. 4 shows a flow chart of a method for generating a data stream on the basis of redundant information, which can be performed in the system 10 shown in fig. 1 and 3. The method starts with steps 28, 30, namely generating first data by the first controller 12 based on first information and generating 30 second data 14 by the second controller 14 based on second information, wherein the second information partially or completely corresponds to the first information. In step 32, the first portion of the first data and the second portion of the second data are combined to produce a data stream.

After steps 34, 36, i.e. after reading in at least a second part of the second data of the data stream by the first controller 12 and at least a first part of the first data of the data stream by the second controller 14, the correctness of the read-in data is checked in step 38, wherein the checking comprises comparing the read-in first part of the first data with the read-in first part of the second data and comparing the read-in second part of the second data with the read-in second part of the first data.

If a difference is determined in the comparison which points to an error in the generation or transmission of data, the transmission of further data via the first circuit 16 is prevented in that one of the controllers 12, 14 inhibits the transmission of data from the other controller 12, 14 or suspends the transmission of its own data by means of outputting a logic level which is dominant.

Furthermore, each controller 12, 14 is provided for reading back the data it has output and comparing it with the data to be output. It can thus be determined whether the respective other controller 12, 14 outputs the idle level correctly or whether an alternate transmission is maintained and the communication of the other controller 12, 14 is not disturbed.

List of reference numerals

10 system

12 controller

12a data output

12b data input

12c signal output terminal

12d data input

14 controller

14a data output

14b data input terminal

14c signal output terminal

14b data input terminal

16 circuit

16a input terminal

16b input terminal

16c output terminal

18 bus controller

18a data output

20a resistance

20b resistance

22 circuit

24a resistor

24b resistance

26 function monitor

28-38 process steps