阅读说明：本技术 电流源电路 (Current source circuit ) 是由 邵博闻 于 2020-04-02 设计创作，主要内容包括：本申请公开了一种电流源电路,涉及集成电路领域。该电流源电路包括主体电路、启动电路和大电流限制电路；所述主体电路由2个PMOS管和2个NMOS管构成,所述启动电路由2个PMOS管构成,所述主体电路与所述启动电路连接；所述大电流限制电路连接电源电压,所述大电流限制电路与所述启动电路连接,所述大电流限制电路用于在所述电源电压的上跳幅度大于所述启动电路中PMOS管的阈值电压时,限制电流源电路的基础电流变化幅度包括；解决了现有的电流源电路在电源电压跳变幅度较大时,电流源电路的基础电流上跳幅度大的问题；达到了在电源电压异常跳变时稳定电流源电路输出的效果。(The application discloses a current source circuit relates to the field of integrated circuits. The current source circuit comprises a main circuit, a starting circuit and a large current limiting circuit; the main circuit is composed of 2 PMOS tubes and 2 NMOS tubes, the starting circuit is composed of 2 PMOS tubes, and the main circuit is connected with the starting circuit; the high-current limiting circuit is connected with a power supply voltage, the high-current limiting circuit is connected with the starting circuit, and the high-current limiting circuit is used for limiting the basic current change amplitude of the current source circuit when the jump-up amplitude of the power supply voltage is larger than the threshold voltage of a PMOS (P-channel metal oxide semiconductor) tube in the starting circuit; the problem that the jump amplitude of the basic current of the current source circuit is large when the jump amplitude of the power voltage is large in the existing current source circuit is solved; the effect of stabilizing the output of the current source circuit when the power supply voltage abnormally jumps is achieved.)

1. A current source circuit is characterized by comprising a main circuit, a starting circuit and a large current limiting circuit;

the main circuit is composed of 2 PMOS tubes and 2 NMOS tubes, the starting circuit is composed of 2 PMOS tubes, and the main circuit is connected with the starting circuit;

the high-current limiting circuit is connected with a power supply voltage, the high-current limiting circuit is connected with the starting circuit, and the high-current limiting circuit is used for limiting the basic current change amplitude of the current source circuit when the up-jump amplitude of the power supply voltage is larger than the threshold voltage of a PMOS (P-channel metal oxide semiconductor) tube in the starting circuit.

2. The current source circuit according to claim 1, wherein the main body circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, the first PMOS transistor and the second PMOS transistor are connected to the supply voltage, the first PMOS transistor and the second PMOS transistor constitute a first current mirror, the first NMOS transistor and the second NMOS transistor constitute a second current mirror, the first PMOS transistor and the first NMOS transistor are connected to the first NMOS transistor, the second PMOS transistor and the second NMOS transistor are connected to the second NMOS transistor, and the first NMOS transistor and the second NMOS transistor are respectively grounded;

the starting circuit comprises a third PMOS tube and a fourth PMOS tube, the third PMOS tube is connected with the power supply voltage, the grid electrode of the third PMOS tube is connected with the drain electrode of a second PMOS tube in the starting circuit, the third PMOS tube is connected with the grid electrode of the fourth PMOS tube, the drain electrode of the fourth PMOS tube is connected with the grid electrode of a first NMOS tube in the starting circuit, and the grid electrode of the fourth PMOS tube is grounded through a capacitor;

the high-current limiting circuit comprises a fifth PMOS tube and a third NMOS tube, the drain electrode of the fifth PMOS tube is connected with the source electrode of a fourth PMOS tube in the starting circuit, the source electrode of the fifth PMOS tube is connected with the power supply voltage, the drain electrode of the fifth PMOS tube is connected with the grid electrode of the third NMOS tube, the grid electrode of the fifth PMOS tube is connected with the drain electrode of the third NMOS tube, and the source electrode of the third PMOS tube is grounded.

3. The current source circuit of claim 2, wherein the high current limiting circuit is configured to limit a leakage current of a fourth PMOS transistor in the start-up circuit when the supply voltage jump-up magnitude is greater than a threshold voltage of the fourth PMOS transistor.

4. The current source circuit of claim 2, wherein in the main circuit, the source of the first PMOS transistor and the source of the second PMOS transistor are respectively connected to the power supply voltage;

the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube, and the grid electrode of the second PMOS tube is connected with the drain electrode;

the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, and the drain electrode of the first NMOS tube is connected with the grid electrode;

the grid electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, and the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube;

the source electrode of the first NMOS tube is grounded, and the source electrode of the second NMOS tube is grounded through a resistor.

5. The current source circuit of claim 2, wherein in the start-up circuit, the source of the third PMOS transistor is connected to the supply voltage, and the drain of the third PMOS transistor is connected to the gate of the fourth PMOS transistor.

6. The current source circuit of claim 2, wherein the first NMOS transistor, the second NMOS transistor, the first PMOS transistor and the second PMOS transistor are enhancement type MOS transistors.

7. The current source circuit of claim 2, wherein the third and fourth PMOS transistors are enhancement MOS transistors.

8. The current source circuit of claim 2, wherein the fifth PMOS transistor and the third NMOS transistor are enhancement MOS transistors.

Technical Field

The application relates to the field of integrated circuits, in particular to a current source circuit.

Background

Various current sources are widely used in an analog integrated circuit, the current sources provide bias current for other modules in the circuit, and in order to ensure the normal operation of the circuit, the current sources need to provide source current which does not change along with the supply voltage.

Fig. 1 provides a conventional current source circuit, a gate of a first PMOS transistor MP1 is connected to a gate of a second PMOS transistor MP2, a gate of a first NMOS transistor MN1 is connected to a gate of a second NMOS transistor MN2, a gate and a drain of the second PMOS transistor are connected, a gate and a drain of the first NMOS transistor are connected, the first PMOS transistor is connected to the first NMOS transistor, the second PMOS transistor is connected to the second NMOS transistor, a drain of the second PMOS transistor is connected to a gate of a third PMOS transistor, a drain of the third PMOS transistor is connected to a gate and a capacitor C of a fourth PMOS transistor, a drain of the fourth PMOS transistor is connected to a gate of the first NMOS transistor, and a source of the fourth PMOS transistor is connected to a power supply voltage VDD.

In fig. 1, when the power voltage is stabilized at a normal value, the drain current of the third PMOS transistor MP3 is small, and the fourth PMOS transistor MP4 is turned off; when the power supply voltage suddenly jumps up, the power supply voltage has a large jump-up amplitude, and the variation amplitude exceeds the threshold voltage of the fourth PMOS transistor, the leakage current of the third PMOS transistor MP3 increases, the capacitor C connected to the drain of the third PMOS transistor MP3 is not charged in time, the fourth PMOS transistor MP4 is turned on, the leakage current of the fourth PMOS transistor MP4 increases, which causes the currents of the first NMOS transistor MN1 and the second NMOS transistor MN2 connected to the drain of the fourth PMOS transistor MP4 to increase, and further the overall current of the current source circuit jumps, which affects the normal operation of other modules.

Disclosure of Invention

To solve the problems in the related art, the present application provides a current source circuit. The technical scheme is as follows:

on one hand, the embodiment of the application provides a current source circuit, which comprises a main circuit, a starting circuit and a large current limiting circuit;

the main circuit is composed of 2 PMOS tubes and 2 NMOS tubes, the starting circuit is composed of 2 PMOS tubes, and the main circuit is connected with the starting circuit;

the high-current limiting circuit is connected with the power supply voltage, the high-current limiting circuit is connected with the starting circuit, and the high-current limiting circuit is used for limiting the basic current change amplitude of the current source circuit when the jump-up amplitude of the power supply voltage is larger than the threshold voltage of a PMOS (P-channel metal oxide semiconductor) tube in the starting circuit.

Optionally, the main circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, the first PMOS transistor is connected to the second PMOS transistor for power supply voltage, the first PMOS transistor and the second PMOS transistor form a first current mirror, the first NMOS transistor and the second NMOS transistor form a second current mirror, the first PMOS transistor is connected to the first NMOS transistor, the second PMOS transistor is connected to the second NMOS transistor, and the first NMOS transistor and the second NMOS transistor are grounded respectively;

the starting circuit comprises a third PMOS tube and a fourth PMOS tube, the third PMOS tube is connected with power supply voltage, the grid electrode of the third PMOS tube is connected with the drain electrode of a second PMOS tube in the starting circuit, the third PMOS tube is connected with the grid electrode of the fourth PMOS tube, the drain electrode of the fourth PMOS tube is connected with the grid electrode of a first NMOS tube in the starting circuit, and the grid electrode of the fourth PMOS tube is grounded through a capacitor;

the high-current limiting circuit comprises a fifth PMOS tube and a third NMOS tube, the drain electrode of the fifth PMOS tube is connected with the source electrode of the fourth PMOS tube in the starting circuit, the source electrode of the fifth PMOS tube is connected with power supply voltage, the drain electrode of the fifth PMOS tube is connected with the grid electrode of the third NMOS tube, the grid electrode of the fifth PMOS tube is connected with the drain electrode of the third NMOS tube, and the source electrode of the third PMOS tube is grounded.

Optionally, the large-current limiting circuit is configured to limit a leakage current of the fourth PMOS transistor when a power supply voltage jump amplitude is greater than a threshold voltage of the fourth PMOS transistor in the starting circuit.

Optionally, in the main circuit, a source of the first PMOS transistor and a source of the second PMOS transistor are respectively connected to a power supply voltage;

the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube, and the grid electrode of the second PMOS tube is connected with the drain electrode;

the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, and the drain electrode of the first NMOS tube is connected with the grid electrode;

the grid electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, and the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube;

the source electrode of the first NMOS tube is grounded, and the source electrode of the second NMOS tube is grounded through a resistor.

Optionally, in the starting circuit, a source of the third PMOS transistor is connected to the power supply voltage, and a drain of the third PMOS transistor is connected to a gate of the fourth PMOS transistor.

Optionally, the first NMOS transistor, the second NMOS transistor, the first PMOS transistor, and the second PMOS transistor are enhancement MOS transistors.

Optionally, the third PMOS transistor and the fourth PMOS transistor are enhancement MOS transistors.

Optionally, the fifth PMOS transistor and the third NMOS transistor are enhancement MOS transistors.

The technical scheme at least comprises the following advantages:

through the large-current limiting circuit, when the power supply voltage jumps up, the change amplitude of the basic current of the current source circuit is reduced, and more stable bias current is provided for other circuit modules.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a circuit schematic of a prior art current source circuit;

fig. 2 is a schematic circuit diagram of a current source circuit according to an embodiment of the present disclosure;

fig. 3 is a graph illustrating a supply voltage jump and a current jump of the PMOS transistor MP1 in the current source circuit according to the embodiment of the present disclosure.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.

The embodiment of the application provides a current source circuit, which comprises a main circuit, a starting circuit and a large current limiting circuit.

The main circuit is composed of 2 PMOS tubes and 2 NMOS tubes, and the starting circuit is composed of 2 PMOS tubes.

The main circuit is connected with power supply voltage, the starting circuit is connected with the power supply voltage, and the main circuit is connected with the starting circuit.

The large current limiting circuit is connected with the power supply voltage, and the large current limiting circuit is connected with the starting circuit.

The large-current limiting circuit is used for limiting the change amplitude of the basic current of the current source circuit when the jump-up amplitude of the power supply voltage is larger than the threshold voltage of a PMOS (P-channel metal oxide semiconductor) tube in the starting circuit.

The base current of the current source circuit is used to provide bias current for other circuit modules.

Through the large-current limiting circuit, when the power supply voltage jumps up, the change amplitude of the basic current of the current source circuit is reduced, and more stable bias current is provided for other circuit modules.

Fig. 2 shows a schematic circuit diagram of a current source circuit according to an embodiment of the present application.

Referring to fig. 2, the main circuit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN 2; the starting circuit comprises a third PMOS tube MP3 and a fourth PMOS tube MP 4; the high current limiting circuit comprises a fifth PMOS transistor MP5 and a third NMOS transistor MN 3.

In the main circuit, the first PMOS transistor MP1 and the second PMOS transistor MP2 form a first current mirror, and the first NMOS transistor MN1 and the second NMOS transistor MN2 form a second current mirror. The first PMOS tube MP1 and the second PMOS tube MP2 are respectively connected with a power supply voltage VDD; the first PMOS transistor MP1 is connected with the first NMOS transistor MN1, the second PMOS transistor is connected with the second NMOS transistor MN2, and the first NMOS transistor MN1 and the second NMOS transistor MN2 are respectively grounded.

Specifically, the source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are respectively connected to the power voltage VDD; the grid electrode of the first PMOS tube MP1 is connected with the grid electrode of the second PMOS tube MP2, and the grid electrode of the second PMOS tube MP2 is connected with the drain electrode of the second PMOS tube MP 2; the drain electrode of the first PMOS tube MP1 is connected with the drain electrode of the first NMOS tube MN1, and the drain electrode of the first NMOS tube MN1 is connected with the gate electrode of the first NMOS tube MN 1; the grid electrode of the first NMOS transistor MN1 is connected with the grid electrode of the second NMOS transistor MN 2; the drain electrode of the second NMOS transistor MN2 is connected with the drain electrode of the second PMOS transistor MP 2; the source of the first NMOS transistor MN1 is grounded, and the source of the second NMOS transistor MN2 is grounded through a resistor R1.

In the starting circuit, a third PMOS transistor MP3 is connected to a power supply voltage VDD, a gate of the third PMOS transistor MP3 is connected to a drain of the second PMOS transistor MP2, a third PMOS transistor MP3 is connected to a gate of the fourth PMOS transistor MP4, a drain of the fourth PMOS transistor MP4 is connected to a gate of the first NMOS transistor MN1 and a gate of the second NMOS transistor MN2, and a gate of the fourth PMOS transistor MP4 is grounded through a capacitor C1.

Specifically, the source of the third PMOS transistor MP3 is connected to the power voltage VDD, and the drain of the third PMOS transistor MP3 is connected to the gate of the fourth PMOS transistor MP 4.

In the large current limiting circuit, the drain of the fifth PMOS transistor MP5 is connected to the source of the fourth PMOS transistor MP4, the source of the fifth PMOS transistor MP5 is connected to the power supply voltage VDD, the drain of the fifth PMOS transistor MP5 is connected to the gate of the third NMOS transistor MN3, the gate of the fifth PMOS transistor MP5 is connected to the drain of the third NMOS transistor MN3, and the source of the third PMOS transistor MP3 is grounded.

When the power voltage VDD jumps up and the jump-up amplitude is greater than the threshold voltage of the fourth PMOS transistor MP4 in the start-up circuit, the large current limiting circuit limits the leakage current of the fourth PMOS transistor MP 4.

When the power voltage VDD jumps up and the jump-up amplitude is greater than the threshold voltage of the fourth PMOS transistor, the fifth PMOS transistor MP5 functions as a resistor to limit the generation of a large current, and the third NMOS transistor MN3 functions as a capacitor to stabilize the leakage current of the fifth PMOS transistor MP5, so that the jump-up amplitude of the leakage current of the fourth PMOS transistor MP4 is low, which is beneficial to stabilizing the basic current output by the current source circuit.

In an example, the threshold voltage of the PMOS transistor in the current source circuit is less than 5V, the power voltage VDD rapidly jumps from 3V to 5V, and the jump time is 1ns, as shown in fig. 3, a curve 31 corresponds to the power voltage VDD, a curve 32 corresponds to the source-drain current of the PMOS transistor MP1 in the current source circuit shown in fig. 1, and a curve 33 corresponds to the source-drain current of the PMOS transistor MP1 in the current source circuit shown in fig. 2; as can be seen from fig. 3, the magnitude of the jump-up of the source-drain current of the PMOS transistor MP1 from 1.25 μ a to 1.5 μ a in the current source circuit shown in fig. 1, and the magnitude of the jump-up of the source-drain current of the PMOS transistor MP1 from 1.25 μ a to 0.3uA in the current source circuit shown in fig. 2.

It can be seen that after the large current limiting circuit is added, when the power supply voltage jump amplitude is larger than the threshold voltage of the PMOS transistor in the starting circuit, the jump-up amplitude of the basic current of the current source circuit is effectively reduced, which is helpful to stabilize the output of the current power supply circuit.

In an alternative embodiment based on the embodiment shown in fig. 2, the first NMOS transistor MN1, the second NMOS transistor MN2, the first PMOS transistor MP1, and the second PMOS transistor MP2 are all enhancement MOS transistors.

In an alternative embodiment based on the embodiment shown in fig. 2, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are both enhancement MOS transistors.

In an alternative embodiment based on the embodiment shown in fig. 2, the fifth PMOS transistor MP5 and the third NMOS transistor are enhancement MOS transistors.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.