阅读说明：本技术 一种参数可调的窄脉冲产生电路 (Parameter-adjustable narrow pulse generation circuit ) 是由 覃良标 鲁正 付益 陈昉 于 2020-04-01 设计创作，主要内容包括：本发明为一种参数可调的窄脉冲产生电路,其包括复杂可编程逻辑器件CPLD、可编程延时芯片和触发器,接有晶振的CPLD产生的方波脉冲信号分成两路分别进入两片可编程延时芯片,CPLD的延时设置信号接入第一可编程延时芯片的11个延时量设置引脚,第二可编程延时芯片设置延时量为0,二延时芯片延时后的信号分别接入D类触发器的RESET和CLK引脚,D类触发器输出窄脉冲信号。CPLD可由FPGA替代。优点为设置二延时芯片延时量的差,即可设置所需窄脉冲的脉宽,脉冲参数调节方便；不受延时芯片固有延时的限制,可产生最小为330ps的脉冲信号,电路简单,易于实施推广。(The invention relates to a parameter-adjustable narrow pulse generating circuit, which comprises a complex programmable logic device CP L D, a programmable delay chip and a trigger, wherein a square wave pulse signal generated by the CP L D connected with a crystal oscillator is divided into two paths and respectively enters the two programmable delay chips, a delay setting signal of the CP L D is accessed into 11 delay setting pins of the first programmable delay chip, a delay setting of the second programmable delay chip is set to be 0, signals delayed by the two delay chips are respectively accessed into a RESET pin and a C L K pin of the D type trigger, the D type trigger outputs a narrow pulse signal, the CP L D can be replaced by an FPGA (field programmable gate array).)

1. A parameter-adjustable narrow pulse generation circuit comprises a trigger, and is characterized in that:

the trigger is a D-type trigger, and further comprises a complex programmable logic device CP L D or a field programmable gate array FPGA and a programmable delay chip, a crystal oscillator is connected into the CP L D or the FPGA to provide a standard clock, the CP L D or the FPGA generates a square wave pulse signal, the square wave pulse signal is divided into two paths to respectively enter two programmable delay chips, and a delay setting signal of the CP L D or the FPGA is connected into 11 delay setting pins D of the first programmable delay chip₀，D₁……D₁₀The first programmable delay chip sets the delay amount to be T₁The second programmable delay chip sets the delay amount to be 0, signals delayed by the first programmable delay chip and the second programmable delay chip are respectively connected to a RESET pin and a C L K pin of the D-type trigger, and the D-type trigger outputs a narrow pulse signal with the frequency consistent with that of a square wave pulse signal generated by CP L D or FPGA.

2. The parameter adjustable narrow pulse generating circuit of claim 1, wherein:

the two programmable delay chips are identical, the inherent delay of the devices of the two programmable delay chips is t, the t is 1-6 ns, the delay step is d, and the d is 8-12 ps.

3. The parameter adjustable narrow pulse generating circuit according to claim 2, wherein:

the delay setting signals of the CP L D or the FPGA are 11 high-level or low-level signals which are sequentially connected into 11 delay setting pins of the programmable delay chip, the high-level and low-level signals of the CP L D or the FPGA respectively represent 1 and 0 of binary numbers, 11 high-level or low-level delay setting signals form 11-bit binary numbers, the product of decimal values corresponding to the binary numbers and delay stepping D of devices of the programmable delay chip is the set delay of the programmable delay chip, and the inherent delay t of the devices of the programmable delay chip is equal to the total delay of the programmable delay chip.

4. The parameter adjustable narrow pulse generating circuit of claim 1, wherein:

the pulse width of the narrow pulse signal output by the D-type trigger is the difference of the delay amount of the two programmable delay chips, namely T₁。

5. The parameter adjustable narrow pulse generating circuit of claim 1, wherein:

the frequency of the crystal oscillator is equal to or greater than 5 MHz.

6. The parameter adjustable narrow pulse generating circuit of claim 1, wherein:

the pulse width of the square wave pulse signal output by the complex programmable logic device CP L D and the field programmable gate array FPGA is larger than that of the square wave pulse signal required to be output.

Technical Field

The invention relates to the technical field of pulse circuits, in particular to a parameter-adjustable narrow pulse generating circuit.

Background

The narrow pulse electric signal generating circuit is an important component in a narrow pulse driving circuit of a semiconductor laser. With the development of semiconductor technology, many integrated chips suitable for pulse driving of semiconductor lasers have appeared, and these driving chips generate different laser modulation currents according to different pulse input signals. Therefore, one of the keys of the design of the pulse driving circuit of the semiconductor laser is the design of the pulse electric signal generating circuit.

At present, there are two main methods for generating electric pulse signals:

1. generating electric pulses by using analog characteristics of a tunnel diode, an avalanche diode and a step diode; the tunnel diode is utilized to generate electric pulse signals, the amplitude of the electric pulse signals is low, and the electric pulse signals are generally millivolt-level and are not beneficial to driving of a post-stage circuit; the pulses generated with avalanche transistors require very high collector voltages, which increases the complexity of the system design; the parameters of the pulse signal generated using the step diode are unstable.

2. The pulse generator is formed by adopting a switching device and a passive element, for example, a 555 timer and a resistance capacitor are used for forming the pulse generator. The pulse adjustment is difficult, and different resistance capacitance values are configured for different pulse parameters.

Obviously, the pulse signal generating circuits of the two existing methods have the defects of difficult pulse parameter adjustment, complex circuit, poor stability and the like. The current market needs a narrow pulse generating circuit with adjustable pulse parameters and simple circuit.

Disclosure of Invention

The invention aims to overcome the defects of the existing narrow pulse generating circuit, and designs a parameter-adjustable narrow pulse generating circuit which comprises a programmable logic device and a trigger, wherein the pulse parameters are adjustable, the circuit is simple, and an electric pulse signal with the minimum of 330ps can be generated.

The invention relates to a parameter-adjustable narrow pulse generating circuit, which comprises a trigger, a Complex Programmable logic Device CP L D (Complex Programmable L organic Device) or a field Programmable Gate array FPGA (field Programmable Gate array), and a Programmable delay chip, wherein the Complex Programmable logic Device is CP L D for short, the field Programmable Gate array is FPGA for short, the trigger is a D-type trigger, a crystal oscillator is connected into the CP L D or the FPGA to provide a standard clock, and the CP L D or the FPGA is adjusted to generate a square pulse signal with required frequency, and the square pulse signal is used for generating the square pulse signalThe number is divided into two paths which respectively enter two programmable delay chips, and CP L D or FPGA delay setting signals are accessed into 11 delay setting pins D of the first programmable delay chip₀，D₁……D₁₀The first programmable delay chip sets the delay amount to be T₁The second programmable delay chip sets the delay amount to be 0, signals delayed by the first programmable delay chip and the second programmable delay chip are respectively connected to a RESET (RESET) pin and a C L K (clock) pin of the D-type trigger, and the D-type trigger outputs a narrow pulse signal with the frequency consistent with that of a square wave pulse signal generated by CP L D or FPGA.

The two programmable delay chips are identical, the inherent delay of the two programmable delay chips is t, the t is 1-6 ns, the delay step is D, the D is 8-12 ps.CP L D or the delay setting signal of the FPGA is 11 high-level or low-level signals, 11 delay setting pins of the programmable delay chips are sequentially connected, the high-level and low-level signals of the CP L D or the FPGA respectively represent 1 and 0 of a binary number, the 11 high-level or low-level delay setting signals form 11-bit binary numbers, the product of a decimal numerical value corresponding to the binary number and the D is a set delay, and the inherent delay t of the two programmable delay chips is equal to the total delay.

The set delay amount of the first programmable delay chip is T₁The actual total delay amount of a path of signal passing through the first programmable delay chip is T₁+t。

The set delay amount of the second programmable delay chip is 0, and the actual total delay amount of the other path of signal passing through the second programmable delay chip is the inherent delay t.

The pulse width of the narrow pulse signal output by the D-type trigger is the difference of the delay amount of the two programmable delay chips, namely T₁。

The frequency of the crystal oscillator is equal to or greater than 5 MHz.

The pulse width of the square wave pulse signal generated by the complex programmable logic device CP L D and the field programmable gate array FPGA is larger than that of the square wave pulse signal required to be output.

Compared with the prior art, the parameter-adjustable narrow pulse generating circuit has the advantages that 1, the required square wave pulse frequency can be obtained by adjusting CP L D or FPGA, the pulse width of the generated narrow pulse signal can be set by setting the delay difference of two programmable delay chips, output pulse parameter adjustment is realized, 2, the pulse width of the output signal is convenient to adjust, only the delay amount of one delay chip needs to be set, 3, the minimum pulse width output by the circuit is determined by the delay step of the delay chip and the maximum response frequency of a D trigger, the delay step of the delay chip is only 8-12 ps, the parameter-adjustable sub-nanosecond pulse signal with the minimum pulse width of 330ps can be obtained by adopting a D trigger with the maximum response frequency of 3GHz, and 4, the circuit is internally provided with the existing devices, is simple to manufacture and easy to implement, popularize and apply.

Drawings

Fig. 1 is a block diagram of an embodiment of the parameter-adjustable narrow pulse generation circuit.

Detailed Description

The embodiment of the parameter-adjustable narrow pulse generating circuit is shown in figure 1 and comprises a crystal oscillator, a complex programmable logic device CP L D, a programmable delay chip and a D-type trigger, wherein the crystal oscillator with the frequency of 5MHz is adopted in the embodiment, the crystal oscillator is connected into the CP L D to provide a standard clock, the CP L D generates a square wave pulse signal, the square wave pulse signal is divided into two paths to respectively enter two programmable delay chips, the CP L D delay setting signal is connected into a delay setting pin D of a first programmable delay chip, and the delay setting of the first programmable delay chip is T₁The second programmable delay chip sets the delay amount to be 0, signals delayed by the first programmable delay chip and the second programmable delay chip are respectively connected to a RESET (RESET) pin and a C L K (clock) pin of the D-type trigger, and the D-type trigger outputs a narrow pulse signal with the frequency consistent with that of a square wave pulse signal generated by the CP L D.

In this example, the two programmable delay chips are the same, and the inherent delay t of the two programmable delay chips is 2.2ns, and the delay step is d is 10 ps.

The programmable delay chip of the embodiment has 11 setting delay setting pins D₀，D₁……D₁₀。

When the pulse width of the square wave pulse signal is required to be output to be 1000ps, namely T is required₁1000ps, the delay step D is divided by 1000ps to 10ps, the obtained result 100 is converted into binary numbers, i.e. 1 and 0 of binary numbers are respectively represented by the high-level and low-level delay setting signals of 00001100100. CP L D, and the high-level and low-level signals corresponding to 00001100100 binary numbers are sequentially input to 11 delay amount setting pins of the first programmable delay chip.

The set delay amount of the first programmable delay chip is T₁And 100d is 1000ps, and the actual total delay amount of one path of signal passing through the first programmable delay chip is 1000ps +2.2 ns.

The set delay amount of the second programmable delay chip is 0, and the actual total delay amount of the other path of signals passing through the second programmable delay chip is 2.2ns of the inherent delay.

The pulse width of the narrow pulse signal output by the D-type trigger is the difference of the delay amount of the two programmable delay chips, namely 1000 ps.

When the circuit of the present embodiment is required to output a pulse signal with a pulse width of 330ps, i.e. T is required₁The result 33 is converted into binary number, i.e. 00000100001. CP L D sequentially inputs the high and low levels corresponding to the binary number to the 11 delay setting pins of the first programmable delay chip, because of the limitation of the response frequency of the class D flip-flop, the minimum pulse width of the pulse signal generated by the present circuit is 330 ps.

The maximum frequency output by the complex programmable logic device CP L D in this example is 100MHz, and the pulse width of the output square wave pulse signal corresponding to the maximum frequency is 5 ns.

The present example complex programmable logic device CP L D may be replaced with a field programmable gate array FPGA.

The above-described embodiments are only specific examples for further explaining the object, technical solution and advantageous effects of the present invention in detail, and the present invention is not limited thereto. Any modification, equivalent replacement, improvement and the like made within the scope of the disclosure of the present invention are included in the protection scope of the present invention.