阅读说明：本技术 一种支持多显示器功能的多媒体控制系统 (Multimedia control system supporting multi-display function ) 是由 甯稿姜 常彪 于 2018-12-29 设计创作，主要内容包括：本发明提供了一种支持多显示器功能的多媒体控制系统,包括显示控制卡和至少一个显示器；显示控制卡包括FPGA芯片、DRAM芯片和HDMI控制器芯片；FPGA芯片上设有PCIE PHY电路、PCIE控制器、CPU、DDR控制器和显示控制电路；显示控制电路包括依次连接的输入linebuffer模块、显示处理模块和输出linebuffer模块,显示处理模块包括相互连接的视频缩放透明处理单元和映射器；PCIE PHY电路与PCIE控制器信号连接,PCIE控制器经DDR控制器与DRAM芯片信号连接；DDR控制器与CPU信号连接；DRAM芯片通过DDR控制器与显示控制电路信号连接,所述显示控制电路通过HDMI控制器芯片与显示器信号连接。本发明在CPU的控制下通过视频缩放透明处理单元及映射器的叠加处理,实现了在显示器上的多画面编辑显示。(The invention provides a multimedia control system supporting multi-display function, comprising a display control card and at least one display; the display control card comprises an FPGA chip, a DRAM chip and an HDMI controller chip; the FPGA chip is provided with a PCIE PHY circuit, a PCIE controller, a CPU, a DDR controller and a display control circuit; the display control circuit comprises an input linebuffer module, a display processing module and an output linebuffer module which are sequentially connected, wherein the display processing module comprises a video zooming transparent processing unit and a mapper which are mutually connected; the PCIE PHY circuit is in signal connection with the PCIE controller, and the PCIE controller is in signal connection with the DRAM chip through the DDR controller; the DDR controller is in signal connection with the CPU; the DRAM chip is in signal connection with the display control circuit through the DDR controller, and the display control circuit is in signal connection with the display through the HDMI controller chip. The invention realizes the multi-picture editing display on the display through the overlapping processing of the video zooming transparent processing unit and the mapper under the control of the CPU.)

1. A multimedia control system supporting multiple display functions, characterized by: the system comprises a display control card and at least one display;

the display control card comprises an FPGA chip, a DRAM chip and an HDMI controller chip;

the FPGA chip is provided with a PCIE PHY circuit, a PCIE controller, a CPU, a DDR controller and a display control circuit;

the display control circuit comprises an input linebuffer module, a display processing module and an output linebuffer module which are sequentially connected, wherein the display processing module comprises a video zooming transparent processing unit and a mapper which are mutually connected;

the PCIE PHY circuit is in signal connection with a PCIE controller, and the PCIE controller is in signal connection with the DRAM chip through a DDR controller;

the DDR controller is in signal connection with the CPU;

the DRAM chip is in signal connection with the display control circuit through the DDR controller, and the display control circuit is in signal connection with the display through the HDMI controller chip.

2. The multimedia control system supporting multiple display functions of claim 1, further comprising a serial F L ASH chip, wherein the serial F L ASH chip is signal connected to the PCIE controller and signal connected to the CPU.

3. The multi-display-function-enabled multimedia control system of claim 1, wherein: the display is a 4K display.

4. The multimedia control system supporting multi-display function according to claim 1, wherein the FPGA chip has a model of XC 5L V550.

5. The multi-display-function-enabled multimedia control system of claim 1, wherein: the HDMI controller chip is an HDMI2.0 controller chip or an HDMI2.1 controller chip.

6. The multi-display-function-enabled multimedia control system of claim 1, wherein: the video scaling transparent processing unit is a scaling transparent mixing module.

7. The multi-display-function-enabled multimedia control system of claim 1, wherein: the mapper comprises a plurality of buffer buffers which are arranged in parallel and are in one-to-one corresponding signal connection with a plurality of video scaling transparent processing units, and a DMA read-write controller which is in signal connection with the buffer buffers through a high-speed data bus.

8. The multi-display-function-enabled multimedia control system of claim 1, wherein: the buffer buffers are at least 16, and the corresponding video scaling transparent processing units are at least 16.

9. The multi-display-function-enabled multimedia control system of claim 7, wherein: each HDMI controller chip supports 2 output video channels.

Technical Field

The invention belongs to the field of high-definition digital television broadcasting, and particularly relates to a multimedia control system supporting multiple display functions.

Background

With the development of digital high-definition 4K studios, the studios of broadcast stations and media production centers face the requirements of multi-picture real-time display, multi-picture superposition, multi-picture nonlinear editing and the like. The current display and broadcast control system cannot meet the broadcast control of 4K content multi-picture.

Disclosure of Invention

In view of the above, the present invention is directed to a multimedia control system supporting multiple display functions, which implements a multi-screen editing display on a display through an overlay process of a video scaling transparent processing unit and a mapper under the control of a CPU.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

a multimedia control system supporting multi-display function comprises a display control card and at least one display;

the display control card comprises an FPGA chip, a DRAM chip and an HDMI controller chip;

the FPGA chip is provided with a PCIE PHY circuit, a PCIE controller, a CPU, a DDR controller and a display control circuit;

the display control circuit comprises an input linebuffer module, a display processing module and an output linebuffer module which are sequentially connected, wherein the display processing module comprises a video zooming transparent processing unit and a mapper which are mutually connected;

the PCIE PHY circuit is in signal connection with a PCIE controller, and the PCIE controller is in signal connection with the DRAM chip through a DDR controller;

the DDR controller is in signal connection with the CPU;

the DRAM chip is in signal connection with the display control circuit through the DDR controller, and the display control circuit is in signal connection with the display through the HDMI controller chip.

Further, the multimedia control system supporting the multi-display function further comprises a serial F L ASH chip, and the serial F L ASH chip is in signal connection with the PCIE controller and is in signal connection with the CPU.

Further, the display is a 4K display.

Furthermore, the model of the FPGA chip is XC 5L V550, which is a American Xilinx chip product.

Further, the HDMI controller chip is an HDMI2.0 controller chip or an HDMI2.1 controller chip.

Further, the Video zooming transparent processing unit is a zooming transparent mixing module designed in one piece, and the zooming transparent mixing module has a zooming transparent mixing (Scaler Alpha mixing) function and is realized by L g original IP Video Scaler core of Xilinx corporation in America.

Further, the video scaling transparent processing unit is a video scaler and a transparent display unit which are in communication connection with each other.

Further, the serial F L ASH chip is model number SST25VF040, which is a chip product of SST corporation in usa.

Furthermore, the model of the HDMI controller chip is ADV8005, which is a chip product of ADI corporation in the united states.

Further, the DRAM chip, model K4T1G164QF, is a chip product of samsung corporation in korea.

Furthermore, the model of the PCIE PHY circuit is dwc _ pci 3.0_ PHY, which is an IP product of Synopsys, usa.

Further, the PCIE controller model is dwc _ pci 3.0_ ctrl, which is an IP product of Synopsys, usa.

Further, the CPU model is Cortex a7, which is an IP product of ARM corporation, uk.

Further, the model of the DDR controller is dwc _ DDR23l _ mctl, which is an IP product of Synopsys, usa.

Compared with the prior art, the multimedia control system supporting the multi-display function has the following advantages:

(1) the multimedia control system supporting the multi-display function realizes multi-picture editing display on the display through the superposition processing of the video zooming transparent processing unit and the mapper under the control of the CPU.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate an embodiment of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:

FIG. 1 is a diagram illustrating a multimedia control system supporting multiple display functions according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an arbitrary splicing combination relationship of 4K displays according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a display control card according to an embodiment of the present invention;

fig. 4 is a signal processing flow chart of 16 frames 4x4 according to the embodiment of the present invention;

FIG. 5 is a flow chart of displaying 1 frame by any splicing combination of 4K displays according to an embodiment of the present invention;

fig. 6 is a schematic diagram of a mapper according to an embodiment of the present invention.

Detailed Description

It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention. Furthermore, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art through specific situations.

The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.

As shown in fig. 1 and 3, the present invention provides a multimedia control system supporting a multi-display function, including a display control card and at least one display;

the display control card comprises an FPGA chip, a DRAM chip and an HDMI controller chip;

the FPGA chip is provided with a PCIE PHY circuit, a PCIE controller, a CPU, a DDR controller and a display control circuit;

the display control circuit comprises an input linebuffer module, a display processing module and an output linebuffer module which are sequentially connected, wherein the display processing module comprises a video zooming transparent processing unit and a mapper which are mutually connected;

the PCIE PHY circuit is in signal connection with a PCIE controller, and the PCIE controller is in signal connection with the DRAM chip through a DDR controller;

the DDR controller is in signal connection with the CPU;

the DRAM chip is in signal connection with the display control circuit through the DDR controller, and the display control circuit is in signal connection with the display through the HDMI controller chip.

Further, the multimedia control system supporting the multi-display function further comprises a serial F L ASH chip, and the serial F L ASH chip is in signal connection with the PCIE controller and is in signal connection with the CPU.

Further, the display is a 4K display.

Furthermore, the model of the FPGA chip is XC 5L V550, which is a American Xilinx chip product.

Further, the HDMI controller chip is an HDMI2.0 controller chip or an HDMI2.1 controller chip.

Further, the video scaling transparent processing unit is a scaling transparent blending module, which has a scaling transparent blending (Scaler Alpha blending) function and is implemented by L ogiCORE IPVideo Scaler core of Xilinx, usa.

Furthermore, the video scaling transparent processing unit is a video scaler and a transparent display unit which are separately designed and are mutually connected in a communication manner, and both the video scaler and the transparent display unit are relatively mature prior art, for example, a display control unit in a patent [ CN200810089674 ] -a liquid crystal display device and a display control method thereof ] can implement zoom processing on a picture, a display control method and a display control system in a patent [ CN201611127912 ] -terminal also disclose a zoom display module for zoom processing on a picture, a transparent display unit in a patent [ CN201410338821 ] -a display device and a method for controlling the display device ] implement setting of picture transparency, and a patent [ CN201711142161 ] -a display control method and an electronic device for desktop icons also disclose a transparency processing unit for processing picture transparency.

As shown in fig. 6, the mapper includes a plurality of buffer buffers disposed in parallel and in signal connection with the plurality of video scaling transparent processing units in a one-to-one correspondence, and a DMA read/write controller in signal connection with the buffer buffers through a high-speed data bus.

The mapper is a commonly used functional device in an image stitching technology, and also belongs to the prior art, for example, a mapping process disclosed in a patent [ CN 201510915712-a coal face real-time video stitching system based on an image processing technology ].

Furthermore, the buffer buffers are at least 16, and the corresponding video scaling transparent processing units are at least 16.

Further, each HDMI controller chip supports 2 output video channels.

Further, there are 4 output linebuffer modules.

Further, there are 4 displays.

Further, the serial F L ASH chip is model number SST25VF040, which is a chip product of SST corporation in usa.

Furthermore, the model of the HDMI controller chip is ADV8005, which is a chip product of ADI corporation in the united states.

Further, the DRAM chip, model K4T1G164QF, is a chip product of samsung corporation in korea.

Furthermore, the model of the PCIE PHY circuit is dwc _ pci 3.0_ PHY, which is an IP product of Synopsys, usa.

Further, the PCIE controller model is dwc _ pci 3.0_ ctrl, which is an IP product of Synopsys, usa.

Further, the CPU model is Cortex a7, which is an IP product of ARM corporation, uk.

Further, the model of the DDR controller is dwc _ DDR23l _ mctl, which is an IP product of Synopsys, usa.

The working process of the invention is as follows: inserting a display control card into a mainboard PCIE slot of a multimedia broadcasting control server, calling multimedia file data to be broadcasted from a hard disk array by the server, and sending the multimedia file data to the display control card through the mainboard PCIE slot of the server;

data enters an FPGA chip from a PCIE slot of a mainboard of the server at first, and enters a PCIE controller through a PCIE PHY circuit in the XC 5L V550 circuit;

the data is stored in the DRAM chip by the PCIE controller through the DDR controller;

the CPU calls data from the DRAM chip to enter a display control circuit through the DDR controller;

the display control circuit is the core of the system and realizes various controls on the display picture of the display.

Firstly, the 164 Kx2K pictures can be independently scaled and transparently processed, and the control pictures are overlapped and respectively output to the 4 output linebuffer modules, and the processing procedure is as follows:

as shown in fig. 4, data of 16 frames are taken out from a DRAM chip by a DDR controller under the control of a CPU, and then stored in an input linebuffer module, each frame is correspondingly output to a corresponding video scaling transparent processing unit, the frames subjected to scaling transparent processing are stored in a corresponding buffer, and then are input to a DMA read/write controller in a 4x4 mapping relationship by a high-speed data bus, the DMA read/write controller stores the spliced frames in an output linebuffer module, the output linebuffer module selects frames and respectively outputs the frames to an HDMI controller chip outside an FPGA chip, each HDMI controller chip supports 2 output video channels, can change pixel data output by the FPGA into an HDMI signal and send the HDMI signal to a display, realizes the display of 16 frames in a 4x4 relationship on the same display, and can transmit the 4x4 frames to multiple displays for display.

Secondly, 1 picture is supported to be displayed by any splicing combination of 4K displays, and the process is as follows:

as shown in fig. 2 and 5, data of 4 frames are taken out from the DRAM chip via the DDR controller under the control of the CPU, then storing the pictures into an input linebuffer module, correspondingly outputting each picture to a corresponding video scaling transparent processing unit, storing the pictures subjected to scaling transparent processing into a corresponding buffer, then input into the DMA read-write controller through the high-speed data bus in a quarter mapping relationship, the DMA read-write controller determines the arrangement relation of four quarter pictures according to the splicing combination form of the display and stores the spliced pictures into an output linebuffer module, the output linebuffer module selects pictures to be respectively output to HDMI controller chips outside the FPGA chip, each HDMI controller chip supports 2 output video channels, pixel data output by the FPGA can be changed into HDMI signals to be sent to a display, and four display screens are respectively used for displaying splicing display of quarter pictures.

Thirdly, the invention can also respectively carry out independent zooming and superposition editing control on 16 pictures, and the process is as follows:

data of 16 pictures are taken out from a DRAM chip through a DDR controller under the control of a CPU, and then are stored in an input linebuffer module, each picture is correspondingly output to a corresponding video zooming transparent processing unit, the pictures subjected to zooming transparent processing are stored in a corresponding buffer, and then are input into a DMA read-write controller through a high-speed data bus according to respective set mapping relation, the DMA read-write controller stores the spliced pictures into an output linebuffer module, the output linebuffer module selects pictures to be respectively output to an HDMI controller chip outside an FPGA chip, each HDMI controller chip supports 2 output video channels, pixel data output by the FPGA can be changed into HDMI signals to be sent to a display, and the 16 pictures are independently edited and independently displayed on the respective display.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.