阅读说明：本技术 一种用于治疗高血压的系统 (System for treating hypertension ) 是由 邹定武 邹晓筱 邹宗立 张宏才 于 2019-01-05 设计创作，主要内容包括：本发明公开了一种用于治疗高血压的系统,通过调控模块M、电子开关模块J、第一电源模块K、第二电源模块A、内磁共振供电控制模块A1、内磁共振超低压电位调控模块B和内磁共振超低压电位发生模块C的配合工作,内磁共振供电控制模块A1控制内磁共振的供电,内磁共振超低压电位调控模块B调控内磁共振超低压电位,内磁共振超低压电位发生模块C产生内磁共振超低压电位,第一电源模块K给整个内磁共振超低压电位调控及显示提供合适电压,电子开关模块J可以对第一电源模块K中的电压进行控制,本发明提供的用于治疗高血压的系统能够输出生物电子形成-5V～-150V的超低压电位,操作安全,可长期居家使用,有助于高血压患者的康复向愈。(The invention discloses a system for treating hypertension, which is characterized in that through the cooperation of a regulation module M, an electronic switch module J, a first power module K, a second power module A, an internal magnetic resonance power supply control module A1, an internal magnetic resonance ultralow voltage potential regulation module B and an internal magnetic resonance ultralow voltage potential generation module C, the internal magnetic resonance power supply control module A1 controls the power supply of internal magnetic resonance, the internal magnetic resonance ultralow voltage potential regulation module B regulates the internal magnetic resonance ultralow voltage potential, the internal magnetic resonance ultralow voltage potential generation module C generates the internal magnetic resonance ultralow voltage potential, the first power module K provides proper voltage for the regulation and display of the whole internal magnetic resonance ultralow voltage potential, the electronic switch module J can control the voltage in the first power module K, and the system for treating hypertension can output bioelectronics to form the ultralow voltage potential of-5V to-150V, the operation is safe, the medicine can be used at home for a long time, and the recovery of the hypertensive is facilitated.)

1. The system for treating the hypertension is characterized by comprising a regulation module M for internal magnetic resonance ultralow voltage potential regulation and control display, a display module L for countdown and internal magnetic resonance ultralow voltage potential regulation, an electronic switch module J for controlling the regulation module M, a first power supply module K, a second power supply module A, an internal magnetic resonance power supply control module A1, an internal magnetic resonance ultralow voltage potential regulation module B and an internal magnetic resonance ultralow voltage potential generation module C, wherein:

the control module M is connected to the display module L, the first power module K, and the electronic switch module J;

the internal magnetic resonance power supply control module A1 is connected with the internal magnetic resonance ultralow voltage potential regulating and controlling module B;

the internal magnetic resonance ultralow voltage potential regulating and controlling module B is connected with the internal magnetic resonance ultralow voltage potential generating module C;

the second power supply module a provides required voltage for the regulation and control module M, the display module L, the electronic switch module J, the first power supply module K, the internal magnetic resonance power supply control module a1, the internal magnetic resonance ultra-low voltage potential regulation and control module B, and the internal magnetic resonance ultra-low voltage potential generation module C.

2. The system for treating hypertension according to claim 1, wherein the second power module a includes a fuse (F), an adjustable resistor (VR), a switching power supply (J3), a twenty-second diode (D22), a first inductor (L1), and a power supply (VCC12), wherein:

one end of the fuse (F) and one end of the adjustable resistor (VR) are connected with one pin of the switching power supply (J3), the other end of the fuse (F) and the cathode of the twenty-second diode (D22) are connected with one end of the first inductor (L1), and the other end of the first inductor (L1) is connected with the power supply (VCC 12);

two pins of the switching power supply (J3), three pins of the switching power supply (J3), the other end of the adjustable resistor (VR), and the anode of the twenty-second diode (D22) are all grounded.

3. The system for treating hypertension according to claim 2, wherein the regulation module M for internal magnetic resonance extra-low voltage potential regulation and control display comprises: first switch (K1), second switch (K2), third switch (K3), fourth switch (K4), fifth switch (K5), sixth switch (K6), first resistor (R1), second resistor (R2), third resistor (R3), fourth resistor (R4), fifth resistor (R4), sixth resistor (R4), seventh resistor (R4), eighth resistor (R4), ninth resistor (R4), tenth resistor (R4), eleventh resistor (R4), twelfth resistor (R4), thirteenth resistor (R4), fourteenth resistor (R4), fifteenth resistor (R4), sixteenth resistor (R4), seventeenth resistor (R4), STCI2C5410 4, first capacitor (C4), second capacitor (C4), third capacitor (C4), fourth capacitor (C4), crystal (JT) 4), monolithic computer 4:

the first switch (K1), the second switch (K2), the third switch (K3), the fourth switch (K4), the fifth switch (K5), and the sixth switch (K6) are all grounded;

the first end of the first resistor (R1) is connected with the power supply (VCC12), and the second end of the first resistor (R1) is connected with the P2.3 pin of the single chip microcomputer STCI2C5410AD and the sixth switch (K6); a first end of the second resistor (R2) is connected with the power supply (VCC12), and a second end of the second resistor (R2) is connected with a P3.0 pin of the single chip microcomputer STCI2C5410AD and the fifth switch (K5);

the first end of the third resistor (R3) is connected with the power supply (VCC12), and the second end of the third resistor (R3) is connected with the P3.1 pin of the single chip microcomputer STCI2C5410AD and the fourth switch (K4);

a first end of the fourth resistor (R4) is connected with the power supply (VCC12), and a second end of the fourth resistor (R4) is connected with a P3.2 pin of the single chip microcomputer STCI2C5410AD and the third switch (K3);

a first end of the fifth resistor (R5) is connected with the power supply (VCC12), and a second end of the fifth resistor (R5) is connected with a P3.3 pin of the single chip microcomputer STCI2C5410AD and the second switch (K2);

a first end of the sixth resistor (R6) is connected with the power supply (VCC12), and a second end of the sixth resistor (R6)) is connected with a P3.4 pin of the single chip microcomputer STCI2C5410AD and the first switch (K1);

a first end of the seventh resistor (R7) is connected with the power supply (VCC12), and a second end of the seventh resistor (R7) is connected with a P2.2 pin of the single chip microcomputer STCI2C5410 AD;

the first end of the eighth resistor (R8) is connected with the power supply (VCC12), the second end of the eighth resistor (R8) is connected with a P3.7 pin of the single chip microcomputer STCI2C5410AD, and the first ends of the ninth resistor (R9), the tenth resistor (R10), the eleventh resistor (R11), the twelfth resistor (R12), the thirteenth resistor (R13), the fourteenth resistor (R14) and the fifteenth resistor (R15) are connected with the display module L;

second ends of the ninth resistor (R9), the tenth resistor (R10), the eleventh resistor (R11), the twelfth resistor (R12), the thirteenth resistor (R13), the fourteenth resistor (R14) and the fifteenth resistor (R15) are respectively connected with a pin P1.6, a pin P1.5, a pin P1.4, a pin P1.3, a pin P1.2, a pin P1.1 and a pin P1.0 of the single chip microcomputer STCI2C5410 AD;

a first end of the sixteenth resistor (R16) is connected with a P2.4 pin of the single chip microcomputer STCI2C5410AD, and a second end of the sixteenth resistor (R16) is connected with the display module L;

the first end of the seventeenth resistor (R17) is connected with the RSE pin of the single chip microcomputer STCI2C5410AD, and the second end of the seventeenth resistor (R17) is grounded;

one end of the first capacitor (C1) is connected with the power supply (VCC12), the other end of the first capacitor (C1) is grounded, and a VCC pin of the single chip microcomputer STCI2C5410AD is connected with the power supply (VCC 12);

one end of the second capacitor (C2) is grounded, the other end of the second capacitor (C2) is connected with an XATA L2 pin of the single-chip microcomputer STCI2C5410AD, one end of the third capacitor (C3) is grounded, and the other end of the third capacitor (C3) is connected with an XATA L1 pin of the single-chip microcomputer STCI2C5410 AD;

one end of the fourth capacitor (C4) is connected with the power supply (VCC12), and the other end of the fourth capacitor (C4) is connected with an RSE pin of the single chip microcomputer STCI2C5410 AD;

two ends of the crystal oscillator (JT2) are respectively connected with an XATA L1 pin and an XATA L2 pin of the single chip microcomputer STCI2C5410 AD;

the anode of the first diode (D1) is connected with the second end of the seventeenth resistor (R17), and the cathode of the first diode (D1) is connected with the RSE pin of the single-chip microcomputer STCI2C5410 AD;

the GND pin of the single chip microcomputer STCI2C5410AD is grounded, and the P2.1 pin, the P2.0 pin, the P2.7 pin and the P2.6 pin of the single chip microcomputer STCI2C5410AD are all connected with the display module L;

a pin P2.5 of the single chip microcomputer STCI2C5410AD is connected with the electronic switch module J; the pin STCI2C5410ADP2.2 of the singlechip and the pin P3.7 of the singlechip are connected with the first power module K; the pin P3.5 and the pin P1.7 of the single chip microcomputer STCI2C5410AD are suspended.

4. The system for treating hypertension according to claim 3, wherein the display module L for countdown and internal magnetic resonance extra low voltage potential regulation includes a first transistor (Q1), a second transistor (Q2), a third transistor (Q3), a fourth transistor (Q4), a nineteenth resistor (R19), a twentieth resistor (R20), a twenty-first resistor (R21), a twenty-second resistor (R22), a twenty-third resistor (R23), a twenty-fourth resistor (R24), a twenty-fifth resistor (R25), a first L ED, a second L ED, a third L ED, a fourth L ED, a fifth capacitor (C5), and a sixth capacitor (C6), wherein:

an emitter of the first triode (Q1) is connected with the power supply (VCC12), a collector of the first triode (Q1) is connected with VCC of the first L ED, and a base of the first triode (Q1) is connected with a first end of the eighteenth resistor (R18);

one end of the fifth capacitor (C5) is connected with the power supply (VCC12), and the other end of the fifth capacitor (C5) is grounded;

an emitter of the second triode (Q2) is connected with the power supply (VCC12), a collector of the second triode (Q2) is connected with VCC of the second L ED, and a base of the second triode (Q2) is connected with a first end of the nineteenth resistor (R19);

a first end of the twentieth resistor (R20) is connected with the power supply (VCC12), and a second end of the twentieth resistor (R20) and a second end of the eighteenth resistor (R18) are both connected with a P2.7 pin of the single-chip microcomputer STCI2C5410 AD;

a first end of the twenty-first resistor (R21) is connected with the power supply (VCC12), and a second end of the twenty-first resistor (R21) and a second end of the nineteenth resistor (R19) are both connected with a P2.6 pin of the single chip microcomputer STCI2C5410 AD;

a G, F, A, B, E, D, C end of the first L ED is connected to second ends of the ninth resistor (R9), the tenth resistor (R10), the fifteenth resistor (R15), the fourteenth resistor (R14), the eleventh resistor (R11), the twelfth resistor (R12) and the thirteenth resistor (R13), respectively;

a G, F, A, B, E, D, C end of the second L ED is connected to second ends of the ninth resistor (R9), the tenth resistor (R10), the fifteenth resistor (R15), the fourteenth resistor (R14), the eleventh resistor (R11), the twelfth resistor (R12), and the thirteenth resistor (R13), respectively;

the DP end of the first L ED is floating, and the DP end of the second L ED is connected with the second end of the sixteenth resistor (R16);

an emitter of the third transistor (Q3) is connected to the power supply (VCC12), a collector of the third transistor (Q3) is connected to VCC of the third L ED, and a base of the third transistor (Q3) is connected to a first end of the twenty-second resistor (R22);

one end of the sixth capacitor (C6) is connected with the power supply (VCC12), and the other end of the sixth capacitor (C6) is grounded;

an emitter of the fourth transistor (Q4) is connected to the power supply (VCC12), a collector of the fourth transistor (Q4) is connected to VCC of the fourth L ED, and a base of the fourth transistor (Q4) is connected to a first end of the twenty-third resistor (R23);

a first end of the twenty-fourth resistor (R24) is connected with the power supply (VCC12), and a second end of the twenty-fourth resistor (R24) and a second end of the twenty-second resistor (R22) are both connected with a P2.0 pin of the single chip microcomputer STCI2C5410 AD;

a first end of the twenty-fifth resistor (R25) is connected with the power supply (VCC12), and a second end of the twenty-fifth resistor (R25) and a second end of the twenty-third resistor (R23) are both connected with a P2.1 pin of the single chip microcomputer STCI2C5410 AD;

a G, F, A, B, E, D, C end of the third L ED is connected to second ends of the ninth resistor (R9), the tenth resistor (R10), the fifteenth resistor (R15), the fourteenth resistor (R14), the eleventh resistor (R11), the twelfth resistor (R12), and the thirteenth resistor (R13), respectively;

a G, F, A, B, E, D, C end of the fourth L ED is connected to second ends of the ninth resistor (R9), the tenth resistor (R10), the fifteenth resistor (R15), the fourteenth resistor (R14), the eleventh resistor (R11), the twelfth resistor (R12), and the thirteenth resistor (R13), respectively;

the DP end of the third L ED and the DP end of the fourth L ED are both floating.

5. The system for treating hypertension according to claim 4, wherein the electronic switch module J includes a twenty-sixth resistor (R26), a twenty-seventh resistor (R27), a twenty-eight resistor (R28), a twenty-ninth resistor (R29), a thirty-third resistor (R30), a thirty-eleventh resistor (R31), a thirty-second resistor (R32), a first inverting amplifier (U2F), a second inverting amplifier (U2B), a third inverting amplifier (U2C), a fourth inverting amplifier (U2D), an eleventh capacitor (C11), a twelfth capacitor (C12), a thirteenth capacitor (C13), a fourteenth capacitor (C14), a fifteenth capacitor (C15), a second diode (D2), a third diode (D3), a fourth diode (D4), a seventh switch (K7), and a fifth transistor (Q5), wherein:

a first end of the twenty-sixth resistor (R26) is connected to the P2.5 pin of the single chip microcomputer STCI2C5410AD, a second end of the twenty-sixth resistor (R26) is connected to an input end of the first inverting amplifier (U2F), an output end of the first inverting amplifier (U2F) is connected to a cathode of the second diode (D2), an anode of the second diode (D2) and a first end of the twenty-eighth resistor (R28) are both connected to an output end of the third inverting amplifier (U2C), a second end of the twenty-eight resistor (R28) is connected to one end of the eleventh capacitor (C11), and the other end of the eleventh capacitor (C11) is grounded;

a first end of the twenty-seventh resistor (R27) is grounded, a second end of the twenty-seventh resistor (R27) is connected to an input end of the second inverting amplifier (U2B), an output end of the second inverting amplifier (U2B) is connected to an input end of the third inverting amplifier (U2C), an output end of the third inverting amplifier (U2C) is connected to an input end of the fourth inverting amplifier (U2D), an output end of the fourth inverting amplifier (U2D) is connected to a first end of the thirty-first resistor (R31), a second end of the thirty-first resistor (R31) is connected to a base of the fifth triode (Q5), a collector of the fifth triode (Q5) is connected to a positive six volt power supply, an emitter of the fifth triode (Q5) is connected to the power supply (VCC12), a first end of the thirty-second resistor (R32) is connected to the power supply (VCC12), a second end of the thirty-second resistor (R32) is connected with the anode of the fourth diode (D4), and the cathode of the fourth diode (D4) is grounded;

one end of the thirteenth capacitor (C13) is connected with the second end of the twenty-sixth resistor (R26), and the other end of the thirteenth capacitor (C13) is grounded;

a first end of the twenty-seventh resistor (R27) is grounded, and a second end of the twenty-seventh resistor (R27) is connected with the input end of the second inverting amplifier (U2B);

one end of the twelfth capacitor (C12) is grounded, the other end of the twelfth capacitor (C12) is connected with the first end of the twenty-ninth resistor (R29), and two ends of the seventh switch (K7) are respectively connected with the first end of the twenty-ninth resistor (R29) and the second end of the twenty-eight resistor (R28);

a second end of the twenty-ninth resistor (R29) is connected to the output end of the second inverting amplifier (U2B) and a negative electrode of the third diode (D3), an anode of the third diode (D3) is connected to a first end of the thirty-second resistor (R30) and one end of the fourteenth capacitor (C14), a second end of the thirty-second resistor (R30) is grounded, the other end of the fourteenth capacitor (C14) is connected to a positive six-volt power supply, one end of the fifteenth capacitor (C15) is connected to the positive six-volt power supply, and the other end of the fifteenth capacitor (C15) is grounded.

6. The system for treating hypertension according to claim 5, wherein the first power module K includes a single pin (J2), a first chip (U1), a seventh capacitor (C7), an eighth capacitor (C8), a ninth capacitor (C9), a tenth capacitor (C10), a thirty-third resistor (R33), a thirty-fourth resistor (R34), a sixth triode (Q6), a fifth diode (D5), a sixth diode (D6), and a sixth triode (Q6), wherein:

one end of the seventh capacitor (C7), one end of the eighth capacitor (C8) and one pin of the single-row pin (J2) are all connected with the input end of the first chip (U1), one end of the ninth capacitor (C9), one end of the tenth capacitor (C10) and the output end of the first chip (U1) are all connected with a positive six-volt power supply, and the other end of the seventh capacitor (C7), the other end of the eighth capacitor (C8), the other end of the ninth capacitor (C9), the other end of the tenth capacitor (C10) and the ground end of the first chip (U1) are all grounded;

two pins of the single-row pin (J2) are connected with the P2.2 pin of the single chip microcomputer STCI2C5410 AD; three pins of the single-row pin (J2) are connected with the P3.7 pin of the single chip microcomputer STCI2C5410 AD;

a fourth pin of the single-row pin (J2) is connected to a first end of a thirty-fourth resistor (R34), a second end of the thirty-fourth resistor (R34) is connected to a base of a sixth transistor (Q6), a collector of the sixth transistor (Q6) is connected to a first end of a thirty-third resistor (R33), a second end of the thirty-third resistor (R33) is connected to the power supply (VCC12), a positive electrode of the fifth diode (D5) and a positive electrode of the sixth diode (D6) are both connected to an emitter of the sixth transistor (Q6), and a positive electrode of the fifth diode (D5) and a negative electrode of the sixth diode (D6) are both grounded;

five pins of the single-row pin (J2) are grounded.

7. The system for treating hypertension according to claim 6, wherein the internal magnetic resonance power control module A1 includes a single pin (J1), a sixteenth capacitor (C16), a seventeenth capacitor (C17), a twentieth capacitor (C20), a twenty-first capacitor (C21), a thirty-eighth resistor (R38), a fifty-eighth resistor (R58), a seventh transistor (Q7), an eighth transistor (Q8), a ninth transistor (Q9), and a seventh diode (D7), wherein:

one end of the sixteenth capacitor (C16), one end of the seventeenth capacitor (C17), a first end of the fifty-eighth resistor (R58), and a first end of the thirty-eighth resistor (R38) are all connected to one pin of the single-row pin (J1), the other end of the sixteenth capacitor (C16) and the other end of the seventeenth capacitor (C17) are all grounded, a second end of the fifty-eighth resistor (R58) is connected to an emitter of the eighth transistor (Q8), a base of the eighth transistor (Q8) is connected to a collector of the seventh transistor (Q7), a cathode of the seventh diode (D7) and a base of the ninth transistor (Q9) are all connected to a collector of the eighth transistor (Q8);

a base electrode of the seventh triode (Q7), one end of the twentieth capacitor (C20) are connected to two pins of the single-row pin (J1), an emitter electrode of the seventh triode (Q7), the other end of the twentieth capacitor (C20), an anode electrode of the seventh diode (D7), and one end of the twenty-first capacitor (C21) are all grounded, the other end of the twenty-first capacitor (C21) and an emitter electrode of the ninth triode (Q9) are both connected to the power supply (VCC12), and a collector electrode of the ninth triode (Q9) is connected to a second end of the thirty-eighth resistor (R38);

four pins of the single-row pin (J1) are grounded, and one pin, three pins and five pins of the single-row pin (J1) are connected with the internal magnetic resonance ultralow voltage potential regulating and controlling module B.

8. The system for treating hypertension according to claim 7, wherein the internal magnetic resonance extra-low voltage potential modulation module B comprises a chip BIT3715(U4), a thirty-fifth resistor (R35), a thirty-sixth resistor (R36), a thirty-seventh resistor (R37), a thirty-ninth resistor (R39), a forty resistor (R40), a forty-first resistor (R41), a forty-second resistor (R42), a forty-third resistor (R43), a forty-fourth resistor (R44), a forty-fifth resistor (R45), a forty-sixth resistor (R46), a forty-seventh resistor (R47), a fifty-eighth resistor (R48), a forty-ninth resistor (R49), a forty-fourth resistor (R50), a first resistor (R51), a second resistor (R52), a third resistor (R53), a fifty-fourth resistor (R54), a fifth resistor (R55), and a sixth resistor (R56), An eighteenth capacitor (C18), a nineteenth capacitor (C19), a twenty-second capacitor (C22), a twenty-third capacitor (C23), a twenty-eighth capacitor (C28), a twenty-ninth capacitor (C29), a thirty-third capacitor (C30), a thirty-eleventh capacitor (C31), a thirty-sixth capacitor (C36), a thirty-seventh capacitor (C37), a thirty-eighth capacitor (C38), a thirty-ninth capacitor (C39), a forty capacitor (C40), an eighth diode (D8), a ninth diode (D9), a twelfth diode (D10), an eleventh diode (D11), a twentieth diode (D20), a twenty-first diode (D21), a twenty-third diode (D23), a twenty-fourth diode (D24), a thirteenth diode (Q10), and an eleventh triode (Q11), wherein:

a first end of the thirty-fifth resistor (R35) is connected to the three pins of the single-row pin (J1), a second end of the thirty-fifth resistor (R35) is connected to a first end of the thirty-seventh resistor (R37), a first end of the thirty-sixth resistor (R36) is connected to the power supply (VCC12), one end of the eighteenth capacitor (C18), a first end of the thirty-seventh resistor (R37), and a thirteen pin of the chip BIT3715(U4) are connected to a second end of the thirty-sixth resistor (R36), the other end of the eighteenth capacitor (C18), a second end of the thirty-seventh resistor (R37), and one end of the nineteenth capacitor (C19) are all grounded, and the other end of the nineteenth capacitor (C19) is connected to a twelve pin of the chip BIT3715 (U4);

a first terminal of the fifty-th resistor (R50) is connected to an eleven pin of the chip BIT3715(U4), a second end of the fifty-first resistor (R50), a pin of the chip BIT3715(U4), and an end of the thirty-fifth capacitor (C35) are all connected to a first end of the fifty-first resistor (R51), the other end of the thirty-fifth capacitor (C35) is connected with two pins of the chip BIT3715(U4), a second end of the fifty-first resistor (R51), a first end of the forty-eighth resistor (R48), and a first end of the fifty-second resistor (R52) are each connected, a second end of the fifty-second resistor (R52) is grounded, a second end of the forty-eighth resistor (R48) and a first end of the forty-seventh resistor (R47) are connected with a first end of the forty-ninth resistor (R49), and a second end of the forty-ninth resistor (R49) is grounded;

a first end of the fifty-third resistor (R53), a first end of the thirty-sixth capacitor (C36), a first end of the thirty-seventh capacitor (C37) and a first end of the thirty-eighth capacitor (C38) are respectively connected with the three pins, the four pins, the five pins and the six pins of the chip BIT3715(U4), a second end of the fifty-third resistor (R53), a second end of the thirty-sixth capacitor (C36), a second end of the thirty-seventh capacitor (C37) and a second end of the thirty-eighth capacitor (C38) are all grounded, a first end of the thirty-ninth resistor (R39) is connected with the six pins of the chip BIT3715(U4), and a second end of the thirty-ninth resistor (R39) is connected with the power supply (VCC 12);

one end of the twenty-second capacitor (C22) is connected to the nine pin of the chip BIT3715(U4), the other end of the twenty-second capacitor (C22), the first end of the fortieth resistor (R40) and the base of the thirteenth diode (Q10) are connected to the anode of the eighth diode (D8), the second end of the fortieth resistor (R40) and the cathode of the eighth diode (D8) are connected to one pin of the single-row pin (J1), the collector of the thirteenth diode (Q10) is connected to one end of the twenty-third capacitor (C23), the other end of the twenty-third capacitor (C23) is grounded, the emitter of the thirteenth diode (Q10) is connected to the collector of the eleventh transistor (Q11), the base of the eleventh transistor (Q11) and the base of the ninth diode (D9) are connected to the forty-first end of the first resistor (R41), a second end of the forty-first resistor (R41) and a cathode of the ninth diode (D9) are both connected with the eight pins of the chip BIT3715(U4), and an emitter of the eleventh triode (Q11) is grounded;

an emitter of the thirteenth polar tube (Q10) and a collector of the eleventh triode (Q11) are both connected with the internal magnetic resonance ultra-low voltage potential generation module C;

one end of the thirty-ninth capacitor (C39), the first end of the fifty-fifth resistor (R55) and the cathode of the twenty-third diode (D23) are all connected with the fifteen pins of the chip BIT3715(U4), the other end of the thirty-ninth capacitor (C39), the second end of the fifty-fifth resistor (R55) and one end of the forty capacitor (C40) are all grounded, the anode of the twenty-third diode (D23) and the anode of the twenty-fourth diode (D24) are all connected with the first end of the fifty-fourth resistor (R54), the second end of the fifty-fourth resistor (R54) is connected with the power supply (VCC12), the other end of the forty-fourth capacitor (C40), the first end of the sixth resistor (R56) are all connected with the cathode of the twenty-fourth diode (D24), the sixth resistor (R56), the cathode of the first end of the twenty-fifth resistor (R35 21) and the cathode of the twenty-fourth diode (R47) are all connected with the cathode of the twenty-fourth resistor (R367) Connecting;

a cathode of the twentieth diode (D20), one end of the thirty-first capacitor (C31) and one end of the twenty-first diode (D21) are both connected to an anode of the twentieth diode (D20) which is grounded, the other end of the thirty-first capacitor (C31) and one end of the twenty-ninth capacitor (C29) are both connected to a first end of the forty-third resistor (R43), a first end of the forty-second resistor (R42), a first end of the forty-third resistor (R43) and one end of the twenty-eighth capacitor (C28) are both connected to a ground, and the other end of the twenty-eighth capacitor (C28), a second end of the forty-second resistor (R42) and a second end of the forty-third resistor (R43) are both connected to a fifth pin of the single row of pins (J1);

one end of the thirtieth capacitor (C30), the cathode of the twelfth diode (D10) and the other end of the twenty-ninth capacitor (C29) are all connected with the anode of the eleventh diode (D11), the other end of the thirtieth capacitor (C30) and the anode of the twelfth diode (D10) are all grounded, the cathode of the eleventh diode (D11) is connected with the first end of the forty-fourth resistor (R44), and the second end of the forty-fourth resistor (R44) is grounded;

ten pins of the chip BIT3715(U4) are connected with the fourteenth power supply, and seven pins, fourteen pins and sixteen pins of the chip BIT3715(U4) are all grounded.

9. The system for treating hypertension according to claim 8, wherein the internal magnetic resonance extra low voltage potential generating module C includes a transformer (T1), a twenty-fourth capacitor (C24), a twenty-fifth capacitor (C25), a twenty-sixth capacitor (C26), a twenty-seventh capacitor (C27), a twelfth diode (D12), a thirteenth diode (D13), a fourteenth diode (D14), a fifteenth diode (D15), a sixteenth diode (D16), a seventeenth diode (D17), an eighteenth diode (D18), a nineteenth diode (D19), a second inductor (L2) and a fifty-ninth resistor (R59), wherein:

an emitter of the thirteenth diode (Q10), a collector of the eleventh triode (Q11) are all connected with the primary coil of the transformer (T1), one end of the twenty-fourth capacitor (C24), one end of the twenty-fifth capacitor (C25), one end of the twenty-sixth capacitor (C26) and one end of the twenty-seventh capacitor (C27) are all connected with the primary coil of the transformer (T1), and the other end of the twenty-fourth capacitor (C24), the other end of the twenty-fifth capacitor (C25), the other end of the twenty-sixth capacitor (C26) and the other end of the twenty-seventh capacitor (C27) are all grounded;

an anode of the nineteenth diode (D19), an anode of the twelfth diode (D12), an anode of the sixteenth diode (D16), and an anode of the fifteenth diode (D15) are connected to the secondary coil of the transformer (T1), a cathode of the nineteenth diode (D19), a cathode of the twelfth diode (D12), a cathode of the sixteenth diode (D16), and a cathode of the fifteenth diode (D15) are connected to an anode of the eighteenth diode (D18), an anode of the thirteenth diode (D13), an anode of the seventeenth diode (D17), and an anode of the fourteenth diode (D14), respectively, a cathode of the eighteenth diode (D18), a cathode of the thirteenth diode (D13), a cathode of the seventeenth diode (D17), and a cathode of the fourteenth diode (D14) are all grounded;

the secondary winding of the transformer (T1) is connected out.

Technical Field

The invention relates to the field of medical treatment, in particular to a system for treating hypertension.

Background

The method is characterized in that China gradually enters an aging social stage, and the increasingly prominent problems in the aging social stage are health and safety problems of aging people, such as hypertension and heart diseases easily caused by old people in the aging stage. On the other hand, attention is paid to the health education of society, family and old people, including health care common sense, nursing knowledge, emergency measures in emergency, and improvement of the understanding of people on physical and mental characteristics of old people and the mastering of general health care and nursing knowledge. Therefore, in order to solve the aging problem, how to effectively treat hypertension occurring in the elderly becomes a problem of great attention of the young generation.

The traditional industrial frequency high potential therapeutic apparatus is a high voltage (potential) alternating electric field therapeutic apparatus which boosts 220V (110V) alternating current commercial power to 1000V-10000V, and can not cure hypertension.

Because the existing western medicine for hypertension can only control and treat hypertension, patients must take antihypertensive western medicines daily for a long time for a lifetime without cure, a high-tech therapeutic apparatus is needed to participate in solving the bottleneck of the existing hypertension treatment field, but the high-potential therapeutic apparatus cannot meet the requirement, and the defects are extremely many:

1. the high-potential therapeutic apparatus adopts 220V AC 50Hz (60Hz) power frequency electricity as a therapeutic factor, has great side effect on human health, and can not be used for a long time.

2. The voltage of the high-potential therapeutic apparatus is increased to 1000V-10000V, harmful electromagnetic waves are generated, the potential danger is high for human bodies, and the high-potential therapeutic apparatus cannot be used for rehabilitation treatment of hypertension patients for long-term use at home.

3. The high-voltage electric shock hazard exists when the high-potential therapeutic apparatus is operated and used.

Disclosure of Invention

To address the deficiencies of the prior art, the present invention provides a system for treating hypertension.

The invention provides a system for treating hypertension, which comprises a regulation module M for internal magnetic resonance ultralow voltage potential regulation and control display, a display module L for countdown and internal magnetic resonance ultralow voltage potential regulation and control, an electronic switch module J for controlling the regulation module M, a first power supply module K, a second power supply module A, an internal magnetic resonance power supply control module A1, an internal magnetic resonance ultralow voltage potential regulation and control module B and an internal magnetic resonance ultralow voltage potential generation module C, wherein the regulation module M comprises:

the control module M is connected to the display module L, the first power module K, and the electronic switch module J;

the internal magnetic resonance power supply control module A1 is connected with the internal magnetic resonance ultralow voltage potential regulating and controlling module B;

the internal magnetic resonance ultralow voltage potential regulating and controlling module B is connected with the internal magnetic resonance ultralow voltage potential generating module C;

the second power supply module a provides required voltage for the regulation and control module M, the display module L, the electronic switch module J, the first power supply module K, the internal magnetic resonance power supply control module a1, the internal magnetic resonance ultra-low voltage potential regulation and control module B, and the internal magnetic resonance ultra-low voltage potential generation module C.

Optionally, the second power module a includes a fuse, an adjustable resistor, a switching power supply, a twenty-second diode, a first inductor, and a power supply, where:

one end of the fuse and one end of the adjustable resistor are both connected with one pin of the switching power supply, the other end of the fuse and the negative electrode of the twenty-second diode are both connected with one end of the first inductor, and the other end of the first inductor is connected with the power supply;

and the two pins of the switching power supply, the three pins of the switching power supply, the other end of the adjustable resistor and the anode of the twenty-second diode are all grounded.

Optionally, the adjusting and controlling module M for adjusting and controlling the internal magnetic resonance ultralow voltage potential and displaying includes: the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor, the sixth resistor, the seventh resistor, the eighth resistor, the ninth resistor, the tenth resistor, the eleventh resistor, the twelfth resistor, the thirteenth resistor, the fourteenth resistor, the fifteenth resistor, the sixteenth resistor, the seventeenth resistor, the single-chip microcomputer STCI2C5410AD, the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the crystal oscillator, the first diode, wherein:

the first switch, the second switch, the third switch, the fourth switch, the fifth switch and the sixth switch are all grounded;

the first end of the first resistor is connected with the power supply, and the second end of the first resistor is connected with the P2.3 pin of the single chip microcomputer STCI2C5410AD and the sixth switch; the first end of the second resistor is connected with the power supply, and the second end of the second resistor is connected with the pin P3.0 of the single chip microcomputer STCI2C5410AD and the fifth switch;

the first end of the third resistor is connected with the power supply, and the second end of the third resistor is connected with the pin P3.1 of the single chip microcomputer STCI2C5410AD and the fourth switch;

the first end of the fourth resistor is connected with the power supply, and the second end of the fourth resistor is connected with the P3.2 pin of the single chip microcomputer STCI2C5410AD and the third switch;

the first end of the fifth resistor is connected with the power supply, and the second end of the fifth resistor is connected with the pin P3.3 of the single chip microcomputer STCI2C5410AD and the second switch;

the first end of the sixth resistor is connected with the power supply, and the second end of the sixth resistor) is connected with the pin P3.4 of the single chip microcomputer STCI2C5410AD and the first switch;

the first end of the seventh resistor is connected with the power supply, and the second end of the seventh resistor is connected with a pin P2.2 of the single chip microcomputer STCI2C5410 AD;

the first end of the eighth resistor is connected with the power supply, and the second end of the eighth resistor is connected with a pin P3.7 of the single chip microcomputer STCI2C5410AD, and the first ends of the ninth resistor, the tenth resistor, the eleventh resistor, the twelfth resistor, the thirteenth resistor, the fourteenth resistor and the fifteenth resistor are all connected with the display module L;

second ends of the ninth resistor, the tenth resistor, the eleventh resistor, the twelfth resistor, the thirteenth resistor, the fourteenth resistor and the fifteenth resistor are respectively connected with a pin P1.6, a pin P1.5, a pin P1.4, a pin P1.3, a pin P1.2, a pin P1.1 and a pin P1.0 of the single chip microcomputer STCI2C5410 AD;

the first end of the sixteenth resistor is connected with a P2.4 pin of the single chip microcomputer STCI2C5410AD, and the second end of the sixteenth resistor is connected with the display module L;

the first end of the seventeenth resistor is connected with an RSE pin of the single chip microcomputer STCI2C5410AD, and the second end of the seventeenth resistor is grounded;

one end of the first capacitor is connected with the power supply, the other end of the first capacitor is grounded, and a VCC pin of the single chip microcomputer STCI2C5410AD is connected with the power supply;

one end of the third capacitor is grounded, and the other end of the third capacitor is connected with an XATA L pin of the single chip microcomputer STCI2C5410 AD;

one end of the fourth capacitor is connected with the power supply, and the other end of the fourth capacitor is connected with an RSE pin of the single chip microcomputer STCI2C5410 AD;

two ends of the crystal oscillator are respectively connected with an XATA L1 pin and an XATA L2 pin of the single chip microcomputer STCI2C5410 AD;

the anode of the first diode is connected with the second end of the seventeenth resistor, and the cathode of the first diode is connected with the RSE pin of the single chip microcomputer STCI2C5410 AD;

the GND pin of the single chip microcomputer STCI2C5410AD is grounded, and the P2.1 pin, the P2.0 pin, the P2.7 pin and the P2.6 pin of the single chip microcomputer STCI2C5410AD are all connected with the display module L;

a pin P2.5 of the single chip microcomputer STCI2C5410AD is connected with the electronic switch module J; the pin STCI2C5410ADP2.2 of the singlechip and the pin P3.7 of the singlechip are connected with the first power module K; the pin P3.5 and the pin P1.7 of the single chip microcomputer STCI2C5410AD are suspended.

Optionally, the display module L for countdown and ltv regulation includes a first transistor, a second transistor, a third transistor, a fourth transistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, a twenty-fifth resistor, a first L ED, a second L ED, a third L ED, a fourth L ED, a fifth capacitor, and a sixth capacitor, where:

an emitting electrode of the first triode is connected with the power supply, a collector electrode of the first triode is connected with VCC of the first L ED, and a base electrode of the first triode is connected with a first end of the eighteenth resistor;

one end of the fifth capacitor is connected with the power supply, and the other end of the fifth capacitor is grounded;

an emitter of the second triode is connected with the power supply, a collector of the second triode is connected with VCC of the second L ED, and a base of the second triode is connected with a first end of the nineteenth resistor;

the first end of the twentieth resistor is connected with the power supply, and the second end of the twentieth resistor and the second end of the eighteenth resistor are both connected with a pin P2.7 of the single chip microcomputer STCI2C5410 AD;

a first end of the twenty-first resistor is connected with the power supply, and a second end of the twenty-first resistor and a second end of the nineteenth resistor are connected with a pin P2.6 of the single chip microcomputer STCI2C5410 AD;

a G, F, A, B, E, D, C terminal of the first L ED is connected to second terminals of the ninth resistor, the tenth resistor, the fifteenth resistor, the fourteenth resistor, the eleventh resistor, the twelfth resistor and the thirteenth resistor, respectively;

a G, F, A, B, E, D, C terminal of the second L ED is connected to second terminals of the ninth resistor, the tenth resistor, the fifteenth resistor, the fourteenth resistor, the eleventh resistor, the twelfth resistor and the thirteenth resistor, respectively;

the DP end of the first L ED is floating, and the DP end of the second L ED is connected with the second end of the sixteenth resistor;

an emitter of the third triode is connected with the power supply, a collector of the third triode is connected with VCC of the third L ED, and a base of the third triode is connected with a first end of the twenty-second resistor;

one end of the sixth capacitor is connected with the power supply, and the other end of the sixth capacitor is grounded;

an emitter of the fourth triode is connected with the power supply, a collector of the fourth triode is connected with VCC of the fourth L ED, and a base of the fourth triode is connected with a first end of the twenty-third resistor;

a first end of the twenty-fourth resistor is connected with the power supply, and a second end of the twenty-fourth resistor and a second end of the twenty-second resistor are both connected with a pin P2.0 of the single chip microcomputer STCI2C5410 AD;

a first end of the twenty-fifth resistor is connected with the power supply, and a second end of the twenty-fifth resistor and a second end of the twenty-third resistor are both connected with a pin P2.1 of the single chip microcomputer STCI2C5410 AD;

a G, F, A, B, E, D, C terminal of the third L ED is connected to second terminals of the ninth resistor, the tenth resistor, the fifteenth resistor, the fourteenth resistor, the eleventh resistor, the twelfth resistor and the thirteenth resistor, respectively;

a G, F, A, B, E, D, C terminal of the fourth L ED is connected to second terminals of the ninth resistor, the tenth resistor, the fifteenth resistor, the fourteenth resistor, the eleventh resistor, the twelfth resistor and the thirteenth resistor, respectively;

the DP end of the third L ED and the DP end of the fourth L ED are both floating.

Optionally, the electronic switch module J includes a twenty-sixth resistor, a twenty-seventh resistor, a twenty-eight resistor, a twenty-ninth resistor, a thirty-third resistor, a thirty-first resistor, a thirty-second resistor, a first inverting amplifier, a second inverting amplifier, a third inverting amplifier, a fourth inverting amplifier, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a fourteenth capacitor, a fifteenth capacitor, a second diode, a third diode, a fourth diode, a seventh switch, and a fifth triode, where:

a first end of the twenty-sixth resistor is connected with a pin P2.5 of the single chip microcomputer STCI2C5410AD, a second end of the twenty-sixth resistor is connected with an input end of the first inverting amplifier, an output end of the first inverting amplifier is connected with a cathode of the second diode, an anode of the second diode and a first end of the twenty-eighth resistor are both connected with an output end of the third inverting amplifier, a second end of the twenty-eight resistor is connected with one end of the eleventh capacitor, and the other end of the eleventh capacitor is grounded;

a first end of the twenty-seventh resistor is grounded, a second end of the twenty-seventh resistor is connected with an input end of the second inverting amplifier, an output end of the second inverting amplifier is connected with an input end of the third inverting amplifier, an output end of the third inverting amplifier is connected with an input end of the fourth inverting amplifier, an output end of the fourth inverting amplifier is connected with a first end of the thirty-first resistor, a second end of the thirty-first resistor is connected with a base electrode of the fifth triode, a collector electrode of the fifth triode is connected with a positive six-volt power supply, an emitter electrode of the fifth triode is connected with the power supply, a first end of the thirty-second resistor is connected with the power supply, a second end of the thirty-second resistor is connected with a positive electrode of the fourth diode, and a negative electrode of the fourth diode is grounded;

one end of the thirteenth capacitor is connected with the second end of the twenty-sixth resistor, and the other end of the thirteenth capacitor is grounded;

a first end of the twenty-seventh resistor is grounded, and a second end of the twenty-seventh resistor is connected with the input end of the second inverting amplifier;

one end of the twelfth capacitor is grounded, the other end of the twelfth capacitor is connected with the first end of the twenty-ninth resistor, and two ends of the seventh switch are respectively connected with the first end of the twenty-ninth resistor and the second end of the twenty-eight resistor;

the second end of the twenty-ninth resistor is connected with the output end of the second inverting amplifier and the cathode of the third diode, the anode of the third diode is connected with the first end of the thirty resistor and one end of the fourteenth capacitor, the second end of the thirty resistor is grounded, the other end of the fourteenth capacitor is connected with a positive six-volt power supply, one end of the fifteenth capacitor is connected with the positive six-volt power supply, and the other end of the fifteenth capacitor is grounded.

Optionally, the first power module K includes a single pin, a first chip, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a thirty-third resistor, a thirty-fourth resistor, a sixth triode, a fifth diode, a sixth diode, and a sixth triode, where:

one end of the seventh capacitor, one end of the eighth capacitor and one pin of the single-row pin are all connected with the input end of the first chip, one end of the ninth capacitor, one end of the tenth capacitor and the output end of the first chip are all connected with a positive six-volt power supply, and the other end of the seventh capacitor, the other end of the eighth capacitor, the other end of the ninth capacitor, the other end of the tenth capacitor and the grounding end of the first chip are all grounded;

two pins of the single-row pin are connected with a P2.2 pin of the single chip microcomputer STCI2C5410 AD; three pins of the single-row pins are connected with a P3.7 pin of the single chip microcomputer STCI2C5410 AD;

the four pins of the single-row pin are connected with a first end of a thirty-fourth resistor, a second end of the thirty-fourth resistor is connected with a base electrode of a sixth triode, a collector electrode of the sixth triode is connected with a first end of the thirty-third resistor, a second end of the thirty-third resistor is connected with the power supply, an anode of the fifth diode and an anode of the sixth diode are both connected with an emitter electrode of the sixth triode, and an anode of the fifth diode and a cathode of the sixth diode are both grounded;

five pins of the single-row pins are grounded.

Optionally, the internal magnetic resonance power supply control module a1 includes a single pin, a sixteenth capacitor, a seventeenth capacitor, a twentieth capacitor, a twenty first capacitor, a thirty eighth resistor, a fifty eighth resistor, a seventh transistor, an eighth transistor, a ninth transistor, and a seventh diode, where:

one end of the sixteenth capacitor, one end of the seventeenth capacitor, a first end of the fifty-eighth resistor and a first end of the thirty-eighth resistor are all connected with one pin of the single-row pin, the other end of the sixteenth capacitor and the other end of the seventeenth capacitor are all grounded, a second end of the fifty-eighth resistor is connected with an emitter of the eighth triode, a base of the eighth triode is connected with a collector of the seventh triode, and a cathode of the seventh diode and a base of the ninth triode are all connected with a collector of the eighth triode;

a base electrode of the seventh triode and one end of the twentieth capacitor are connected with the two pins of the single-row pin, an emitting electrode of the seventh triode, the other end of the twentieth capacitor, an anode of the seventh diode and one end of the twenty-first capacitor are all grounded, the other end of the twenty-first capacitor and an emitting electrode of the ninth triode are all connected with the power supply, and a collector electrode of the ninth triode is connected with a second end of the thirty-eighth resistor;

four pins of the single-row pins are grounded, and one pin, three pins and five pins of the single-row pins are connected with the internal magnetic resonance ultralow voltage potential regulating and controlling module B.

Optionally, the internal magnetic resonance ultra-low voltage potential regulating module B includes a chip BIT3715, a thirty-fifth resistor, a thirty-sixth resistor, a thirty-seventh resistor, a thirty-ninth resistor, a fortieth resistor, a forty-first resistor, a forty-second resistor, a forty-third resistor, a forty-fourth resistor, a forty-fifth resistor, a forty-sixth resistor, a forty-seventh resistor, a forty-eighth resistor, a forty-ninth resistor, a fifty-fifth resistor, a fifty-first resistor, a fifty-second resistor, a fifty-third resistor, a fifty-fourth resistor, a fifty-fifth resistor, a fifty-sixth resistor, an eighteenth capacitor, a nineteenth capacitor, a twenty-second capacitor, a twenty-third capacitor, a twenty-eighth capacitor, a twenty-ninth capacitor, a thirty-eleventh capacitor, a thirty-fifth capacitor, a thirty-sixth capacitor, a thirty-seventh capacitor, a thirty-eighth capacitor, a thirty-ninth capacitor, a twenty-eighth capacitor, a, A fortieth capacitor, an eighth diode, a ninth diode, a twelfth diode, an eleventh diode, a twentieth diode, a twenty-first diode, a twenty-third diode, a twenty-fourth diode, a thirteenth diode, and an eleventh triode, wherein:

a first end of the thirty-fifth resistor is connected with the three pins of the single-row pin, a second end of the thirty-fifth resistor is connected with a first end of the thirty-seventh resistor, a first end of the thirty-sixth resistor is connected with the power supply, one end of the eighteenth capacitor, a first end of the thirty-seventh resistor and the thirteen pins of the chip BIT3715 are all connected with a second end of the thirty-sixth resistor, the other end of the eighteenth capacitor, a second end of the thirty-seventh resistor and one end of the nineteenth capacitor are all grounded, and the other end of the nineteenth capacitor is connected with the twelve pins of the chip BIT 3715;

a first end of the fifty-fifth resistor is connected with an eleventh pin of the chip BIT3715, a second end of the fifty-fifth resistor, a first pin of the chip BIT3715 and one end of the thirty-fifth capacitor are all connected with the first end of the fifty-first resistor, the other end of the thirty-fifth capacitor is connected with a second pin of the chip BIT3715, a second end of the fifty-first resistor and a first end of the forty-eighth resistor are all connected with a first end of the fifty-second resistor, a second end of the fifty-second resistor is grounded, a second end of the forty-eighth resistor and a first end of the forty-seventh resistor are all connected with a first end of the forty-ninth resistor, and a second end of the forty-ninth resistor is grounded;

a first end of the fifty-third resistor, one end of the thirty-sixth capacitor, one end of the thirty-seventh capacitor, and one end of the thirty-eighth capacitor are respectively connected to a three pin, a four pin, a five pin, and a six pin of the chip BIT3715, a second end of the fifty-third resistor, the other end of the thirty-sixth capacitor, the other end of the thirty-seventh capacitor, and the other end of the thirty-eighth capacitor are all grounded, a first end of the thirty-ninth resistor is connected to a six pin of the chip BIT3715, and a second end of the thirty-ninth resistor is connected to the power supply;

one end of the twenty-second capacitor is connected with the nine pins of the chip BIT3715, the other end of the twenty-second capacitor, the first end of the fortieth resistor and the base electrode of the thirteenth diode are all connected with the anode of the eighth diode, the second end of the fortieth resistor and the cathode of the eighth diode are both connected with one pin of the single-row pin, a collector electrode of the thirteenth polar tube is connected with one end of the twenty-third capacitor, the other end of the twenty-third capacitor is grounded, an emitter of the thirteenth diode is connected with a collector of the eleventh triode, a base of the eleventh triode and an anode of the ninth diode are both connected with a first end of the forty-first resistor, a second end of the forty-first resistor and a negative electrode of the ninth diode are both connected with the eight pins of the chip BIT3715, and an emitter of the eleventh triode is grounded;

an emitting electrode of the thirteenth polar tube and a collecting electrode of the eleventh polar tube are both connected with the internal magnetic resonance ultra-low voltage potential generating module C;

one end of the thirty-ninth capacitor, the first end of the fifty-fifth resistor and the cathode of the twenty-third diode are all connected with the fifteen pins of the chip BIT3715, the other end of the thirty-ninth capacitor, the second end of the fifty-fifth resistor and one end of the forty-fourth capacitor are all grounded, the anode of the twenty-third diode and the anode of the twenty-fourth diode are all connected with the first end of the fifty-fourth resistor, the second end of the fifty-fourth resistor is connected with the power supply, the other end of the forty-fourth capacitor and the first end of the fifty-sixth resistor are all connected with the cathode of the twenty-fourth diode, and the second end of the fifty-sixth resistor and the cathode of the twenty-first diode are all connected with the second end of the forty-seventh resistor;

the cathode of the twentieth diode and one end of the thirty-first capacitor are both connected with the anode of the twenty-first diode, the anode of the twentieth diode is grounded, the other end of the thirty-first capacitor and one end of the twenty-ninth capacitor are both connected with the first end of the forty-third resistor, the first end of the forty-second resistor, the first end of the forty-third resistor and one end of the twenty-eighth capacitor are all grounded, and the other end of the twenty-eighth capacitor, the second end of the forty-second resistor and the second end of the forty-third resistor are all connected with the five pins of the single-row pin;

one end of the thirty-first capacitor, the cathode of the twelfth pole tube and the other end of the twenty-ninth capacitor are all connected with the anode of the eleventh diode, the other end of the thirty-first capacitor and the anode of the twelfth pole tube are all grounded, the cathode of the eleventh diode is connected with the first end of the forty-fourth resistor, and the second end of the forty-fourth resistor is grounded;

the ten pins of the chip BIT3715 are connected with the fourteenth power supply, and the seven pins, the fourteen pins and the sixteen pins of the chip BIT3715 are all grounded.

Optionally, the internal magnetic resonance ultra-low voltage potential generating module C includes a transformer, a twenty-fourth capacitor, a twenty-fifth capacitor, a twenty-sixth capacitor, a twenty-seventh capacitor, a twelfth diode, a thirteenth diode, a fourteenth diode, a fifteenth diode, a sixteenth diode, a seventeenth diode, an eighteenth diode, a nineteenth diode, and a fifty-ninth resistor of a second inductor, wherein:

an emitter of the thirteenth polar tube and a collector of the eleventh triode are connected with the primary coil of the transformer, one end of the twenty-fourth capacitor, one end of the twenty-fifth capacitor, one end of the twenty-sixth capacitor and one end of the twenty-seventh capacitor are connected with the primary coil of the transformer, and the other end of the twenty-fourth capacitor, the other end of the twenty-fifth capacitor, the other end of the twenty-sixth capacitor and the other end of the twenty-seventh capacitor are grounded;

the anode of the nineteenth diode, the anode of the twelfth diode, the anode of the sixteenth diode and the anode of the fifteenth diode are all connected with the secondary coil of the transformer, the cathode of the nineteenth diode, the cathode of the twelfth diode, the cathode of the sixteenth diode and the cathode of the fifteenth diode are respectively connected with the anode of the eighteenth diode, the anode of the thirteenth diode, the anode of the seventeenth diode and the anode of the fourteenth diode, and the cathode of the eighteenth diode, the cathode of the thirteenth diode, the cathode of the seventeenth diode and the cathode of the fourteenth diode are all grounded;

and the secondary coil of the transformer is connected out.

According to the technical scheme, the system for treating the hypertension comprises a regulation module M for regulating and controlling the internal magnetic resonance ultralow voltage potential and displaying, a display module L for regulating and controlling countdown and internal magnetic resonance ultralow voltage potential, an electronic switch module J for controlling the regulation module M, wherein the regulation module M is connected with the display module L, the first power supply module K and the electronic switch module J, the internal magnetic resonance power supply control module A1 is connected with the internal magnetic resonance ultralow voltage potential regulation module B, the internal magnetic resonance ultralow voltage potential regulation module B is connected with the internal magnetic resonance ultralow voltage potential generation module C, the second power supply module A is used for providing voltage required by the regulation module M, the display module L, the electronic switch module J, the first power supply module K, the internal magnetic resonance power supply module A1, the internal magnetic resonance voltage regulation module B and the internal magnetic resonance voltage potential generation control module C, the regulation module A and the internal magnetic resonance power supply control module C can provide voltage required by the ultralow voltage regulation module M, the ultralow voltage, the first power supply module K, the internal magnetic resonance power supply module A4690, the internal magnetic resonance ultralow voltage regulation module K and the internal magnetic resonance ultralow voltage control module K, the internal magnetic resonance voltage generation control module K can provide the voltage for the first ultralow resonance ultralow voltage potential regulation module K, the internal magnetic resonance ultralow resonance voltage potential regulation module K, the internal magnetic resonance ultralow voltage control module K-to the internal magnetic resonance ultralow resonance voltage regulation module K, the internal magnetic resonance voltage regulation module K-to provide the whole high voltage generation control module K, the electronic switch module K-potential generation control module K, the high voltage generation control module K-low voltage generation module K, the high voltage potential generation module K-low-voltage potential generation module K for the high-low-voltage potential generation and the electronic switch module K, the high voltage resonance.

Drawings

In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious to those skilled in the art that other drawings can be obtained according to the drawings without any inventive exercise.

FIG. 1 is a first schematic block diagram of a system for treating hypertension according to the present invention;

FIG. 2 is a second schematic diagram of a system for treating hypertension according to the present invention;

FIG. 3 is a schematic diagram of a second power module A of the system for treating hypertension according to the present invention;

FIG. 4 is a schematic structural diagram of a control module M of the system for treating hypertension according to the present invention;

FIG. 5 is a schematic diagram of a display module L of a system for treating hypertension according to the present invention;

fig. 6 is a second partial schematic structural diagram of the display module L of the system for treating hypertension according to the present invention;

fig. 7 is a second partial schematic structural diagram of the display module L of the system for treating hypertension according to the present invention;

FIG. 8 is a partial schematic diagram of a display module L and a control module M of a system for treating hypertension according to the present invention;

FIG. 9 is a second partial connection diagram of a display module L and a control module M of the system for treating hypertension according to the present invention;

fig. 10 is a schematic structural diagram of an electronic switch module J of a system for treating hypertension according to the present invention;

fig. 11 is a schematic structural diagram of a first power module K of a system for treating hypertension according to the present invention;

fig. 12 is a schematic structural diagram of an internal magnetic resonance power supply control module a1 of the system for treating hypertension according to the present invention;

FIG. 13 is a schematic structural diagram of an internal magnetic resonance extra-low voltage potential regulation module B of a system for treating hypertension according to the present invention;

FIG. 14 is a partial schematic structural diagram of an internal magnetic resonance extra-low voltage potential regulation module B of a system for treating hypertension according to the present invention;

fig. 15 is a second partial schematic structural diagram of an internal magnetic resonance ultra-low voltage potential regulation module B of the system for treating hypertension according to the present invention;

fig. 16 is a schematic structural diagram of an internal magnetic resonance ultra-low voltage potential generating module C of a system for treating hypertension according to the present invention;

FIG. 17 is a schematic view of a device for treating hypertension according to the present invention;

figure 18 is a graph of systolic blood pressure for different treatment sessions.

Detailed Description

The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described, and it will be appreciated by those skilled in the art that the present invention may be embodied without departing from the spirit and scope of the invention, and therefore the present invention is not limited to the specific embodiments disclosed below.

Referring to fig. 1 to 16, the present invention provides a system for treating hypertension, including a regulation module M for internal magnetic resonance ultra-low voltage potential regulation and control display, a display module L for countdown and internal magnetic resonance ultra-low voltage potential regulation, an electronic switch module J for controlling the regulation module M, and further including a first power module K, a second power module a, an internal magnetic resonance power supply control module a1, an internal magnetic resonance ultra-low voltage potential regulation module B, and an internal magnetic resonance ultra-low voltage potential generation module C, wherein:

the control module M is connected to the display module L, the first power module K, and the electronic switch module J;

the internal magnetic resonance power supply control module A1 is connected with the internal magnetic resonance ultralow voltage potential regulating and controlling module B;

the internal magnetic resonance ultralow voltage potential regulating and controlling module B is connected with the internal magnetic resonance ultralow voltage potential generating module C;

the second power supply module a provides required voltage for the regulation and control module M, the display module L, the electronic switch module J, the first power supply module K, the internal magnetic resonance power supply control module a1, the internal magnetic resonance ultra-low voltage potential regulation and control module B, and the internal magnetic resonance ultra-low voltage potential generation module C.

Optionally, the second power module a includes a fuse F, an adjustable resistor VR, a switching power supply J3, a twenty-second diode D22, a first inductor L1, and a power supply VCC12, wherein:

one end of the fuse F and one end of the adjustable resistor VR are both connected to one pin of the switching power supply J3, the other end of the fuse F and the cathode of the twenty-second diode D22 are both connected to one end of the first inductor L1, and the other end of the first inductor L1 is connected to the power supply VCC 12;

two pins of the switching power supply J3, three pins of the switching power supply J3, the other end of the adjustable resistor VR, and the anode of the twenty-second diode D22 are all grounded.

The second power module a provides the required voltage for the regulation and control module M, the display module L, the electronic switch module J, the first power module K, the internal magnetic resonance power supply control module a1, the internal magnetic resonance ultra-low voltage potential regulation and control module B, and the internal magnetic resonance ultra-low voltage potential generation module C.

Optionally, the adjusting and controlling module M for adjusting and controlling the internal magnetic resonance ultralow voltage potential and displaying includes: first switch K1, second switch K2, third switch K3, fourth switch K4, fifth switch K5, sixth switch K6, first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, fifth resistor R4, sixth resistor R4, seventh resistor R4, eighth resistor R4, ninth resistor R4, tenth resistor R4, eleventh resistor R4, twelfth resistor R4, thirteenth resistor R4, fourteenth resistor R4, fifteenth resistor R4, sixteenth resistor R4, seventeenth resistor R4, single-chip microcomputer STCI2C5410 4, first capacitor C4, second capacitor C4, third capacitor C4, fourth capacitor C4, crystal oscillator JT 4, first diode D4, wherein:

the single chip microcomputer STCI2C5410AD includes twenty-eight pins, which are a VCC pin, a P2.2 pin, a P2.3 pin, a P3.0 pin, a P3.1 pin, a P3.2 pin, a P3.3 pin, a P3.4 pin, a P3.7 pin, a P1.7 pin, a P1.6 pin, a P1.5 pin, a P1.4 pin, a P1.3 pin, a P1.2 pin, a P1.1 pin, a P1.0 pin, a P3.5 pin, a P2.4 pin, a P2.1 pin, a P2.0 pin, a P2.7 pin, a P2.6 pin, a P2.5 pin, an RSE pin, a XATA L1 pin, a XATA L2 pin, and a GND pin.

The resistances of the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6 are all 2K Ω, the resistances of the seventh resistor R7, the eighth resistor R8 and the seventeenth resistor R17 are 1K Ω, and the resistances of the ninth resistor R9, the tenth resistor R10, the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14, the fifteenth resistor R15 and the sixteenth resistor R16 are all 200 Ω.

The first switch K1, the second switch K2, the third switch K3, the fourth switch K4, the fifth switch K5 and the sixth switch K6 are all grounded;

a first end of the first resistor R1 is connected with the power supply VCC12, and second ends of the first resistor R1 are connected with a P2.3 pin of the single chip microcomputer STCI2C5410AD and the sixth switch K6; a first end of the second resistor R2 is connected with the power supply VCC12, and second ends of the second resistors R2 are connected with a P3.0 pin of the single chip microcomputer STCI2C5410AD and the fifth switch K5;

a first end of the third resistor R3 is connected with the power supply VCC12, and second ends of the third resistor R3 are connected with a P3.1 pin of the single chip microcomputer STCI2C5410AD and the fourth switch K4;

a first end of the fourth resistor R4 is connected with the power supply VCC12, and second ends of the fourth resistor R4 are connected with a P3.2 pin of the single chip microcomputer STCI2C5410AD and the third switch K3;

a first end of the fifth resistor R5 is connected with the power supply VCC12, and second ends of the fifth resistors R5 are connected with a P3.3 pin of the single chip microcomputer STCI2C5410AD and the second switch K2;

a first end of the sixth resistor R6 is connected with the power supply VCC12, and second ends of the sixth resistor R6 are connected with a P3.4 pin of the single chip microcomputer STCI2C5410AD and the first switch K1;

a first end of the seventh resistor R7 is connected with the power supply VCC12, and a second end of the seventh resistor R7 is connected with a P2.2 pin of the single chip microcomputer STCI2C5410 AD;

the first end of the eighth resistor R8 is connected with the power supply VCC12, the second end of the eighth resistor R8 is connected with the P3.7 pin of the single chip microcomputer STCI2C5410AD, and the first ends of the ninth resistor R9, the tenth resistor R10, the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14 and the fifteenth resistor R15 are all connected with the display module L;

second ends of the ninth resistor R9, the tenth resistor R10, the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14 and the fifteenth resistor R15 are respectively connected with a pin P1.6, a pin P1.5, a pin P1.4, a pin P1.3, a pin P1.2, a pin P1.1 and a pin P1.0 of the STCI2C54 5410AD of the single chip microcomputer;

a first end of the sixteenth resistor R16 is connected with a P2.4 pin of the single chip microcomputer STCI2C5410AD, and a second end of the sixteenth resistor R16 is connected with the display module L;

a first end of the seventeenth resistor R17 is connected with an RSE pin of the single chip microcomputer STCI2C5410AD, and a second end of the seventeenth resistor R17 is grounded;

one end of the first capacitor C1 is connected with the power supply VCC12, the other end of the first capacitor C1 is grounded, and a VCC pin of the single chip microcomputer STCI2C5410AD is connected with the power supply VCC 12;

one end of the second capacitor C2 is grounded, and the other end of the second capacitor C2 is connected with an XATA L pin of the single chip microcomputer STCI2C5410 AD;

one end of the fourth capacitor C4 is connected with the power supply VCC12, and the other end of the fourth capacitor C4 is connected with the RSE pin of the single chip microcomputer STCI2C5410 AD;

two ends of the crystal oscillator JT2 are respectively connected with an XATA L1 pin and an XATA L2 pin of the single chip microcomputer STCI2C5410 AD;

the anode of the first diode D1 is connected with the second end of the seventeenth resistor R17, and the cathode of the first diode D1 is connected with the RSE pin of the single-chip microcomputer STCI2C5410 AD;

the GND pin of the single chip microcomputer STCI2C5410AD is grounded, and the P2.1 pin, the P2.0 pin, the P2.7 pin and the P2.6 pin of the single chip microcomputer STCI2C5410AD are all connected with the display module L;

a pin P2.5 of the single chip microcomputer STCI2C5410AD is connected with the electronic switch module J; the pin STCI2C5410ADP2.2 and the pin P3.7 of the singlechip are connected with the first power module K, and the singlechip STCI2C5410AD controls two pins and three pins of the single-row pin J2 through a program so as to control the internal magnetic resonance ultralow voltage potential; the pin P3.5 and the pin P1.7 of the single chip microcomputer STCI2C5410AD are suspended.

An oscillator circuit formed by the XATA L1 pin and the XATA L2 pin of the single chip microcomputer STCI2C5410AD, the crystal oscillator JT2, the second capacitor C2 and the third capacitor C3, the crystal oscillator JT2, the XATA L1 pin and the XATA L2 pin of the single chip microcomputer STCI2C5410AD generate a gem wave (i.e., an undesired wave of other frequencies), the gem wave has little influence on the circuit but reduces the stability of a clock oscillator of the circuit, for the stability of the circuit, two capacitor grounds of 10pf-50pf are connected to two pins of the crystal oscillator JT2 to reduce the influence of the gem wave on the stability of the circuit, and the second capacitor C2 and the third capacitor C3 are capacitors of 20 pf.

Optionally, the display module L for countdown and internal magnetic resonance extra-low voltage potential regulation includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25, a first L ED, a second L ED, a third L ED, a fourth L ED, a fifth capacitor C5, and a sixth capacitor C6, where:

the first L ED, the second L ED, the third L0 ED and the fourth L1 ED respectively comprise an A end, a B end, a C end, a D end, an E end, an F end, a G end, a VCC end and a DP end, the first L ED and the second L ED are used for displaying time, the third L ED and the fourth L ED are used for displaying gears, dynamic scanning is carried out by the single chip STCI2C5410AD, and countdown and internal magnetic resonance voltage potential regulation and control are realized by controlling the first triode Q1, the second triode Q2, the third triode Q3 and the fourth triode Q4 and displayed on the first L ED, the second L ED, the third L ED and the fourth L ED.

An emitter of the first triode Q1 is connected to the power source VCC12, a collector of the first triode Q1 is connected to VCC of the first L ED, and a base of the first triode Q1 is connected to a first end of the eighteenth resistor R18;

one end of the fifth capacitor C5 is connected to the power source VCC12, and the other end of the fifth capacitor C5 is grounded;

an emitter of the second triode Q2 is connected to the power source VCC12, a collector of the second triode Q2 is connected to VCC of the second L ED, and a base of the second triode Q2 is connected to a first end of the nineteenth resistor R19;

a first end of the twentieth resistor R20 is connected with the power supply VCC12, and a second end of the twentieth resistor R20 and a second end of the eighteenth resistor R18 are both connected with a P2.7 pin of the single chip microcomputer STCI2C5410 AD;

a first end of the twenty-first resistor R21 is connected with the power supply VCC12, and a second end of the twenty-first resistor R21 and a second end of the nineteenth resistor R19 are both connected with a P2.6 pin of the single chip microcomputer STCI2C5410 AD;

a G, F, A, B, E, D, C end of the first L ED is connected to second ends of the ninth resistor R9, the tenth resistor R10, the fifteenth resistor R15, the fourteenth resistor R14, the eleventh resistor R11, the twelfth resistor R12 and the thirteenth resistor R13, respectively;

a G, F, A, B, E, D, C end of the second L ED is connected to second ends of the ninth resistor R9, the tenth resistor R10, the fifteenth resistor R15, the fourteenth resistor R14, the eleventh resistor R11, the twelfth resistor R12 and the thirteenth resistor R13, respectively;

the DP end of the first L ED is floating, and the DP end of the second L ED is connected with the second end of the sixteenth resistor R16;

an emitter of the third triode Q3 is connected to the power source VCC12, a collector of the third triode Q3 is connected to VCC of the third L ED, and a base of the third triode Q3 is connected to a first end of the twenty-second resistor R22;

one end of the sixth capacitor C6 is connected to the power source VCC12, and the other end of the sixth capacitor C6 is grounded;

an emitter of the fourth triode Q4 is connected to the power source VCC12, a collector of the fourth triode Q4 is connected to VCC of the fourth L ED, and a base of the fourth triode Q4 is connected to a first end of the twenty-third resistor R23;

a first end of the twenty-fourth resistor R24 is connected with the power supply VCC12, and a second end of the twenty-fourth resistor R24 and a second end of the twenty-second resistor R22 are both connected with a P2.0 pin of the single chip microcomputer STCI2C5410 AD;

a first end of the twenty-fifth resistor R25 is connected with the power supply VCC12, and a second end of the twenty-fifth resistor R25 and a second end of the twenty-third resistor R23 are both connected with a P2.1 pin of the single chip microcomputer STCI2C5410 AD;

a G, F, A, B, E, D, C end of the third L ED is connected to second ends of the ninth resistor R9, the tenth resistor R10, the fifteenth resistor R15, the fourteenth resistor R14, the eleventh resistor R11, the twelfth resistor R12 and the thirteenth resistor R13, respectively;

a G, F, A, B, E, D, C end of the fourth L ED is connected to second ends of the ninth resistor R9, the tenth resistor R10, the fifteenth resistor R15, the fourteenth resistor R14, the eleventh resistor R11, the twelfth resistor R12 and the thirteenth resistor R13, respectively;

the DP end of the third L ED and the DP end of the fourth L ED are both floating.

Optionally, the electronic switch module J includes a twenty-sixth resistor R26, a twenty-seventh resistor R27, a twenty-eight resistor R28, a twenty-ninth resistor R29, a thirty-third resistor R30, a thirty-first resistor R31, a thirty-second resistor R32, a first inverting amplifier U2F, a second inverting amplifier U2B, a third inverting amplifier U2C, a fourth inverting amplifier U2D, an eleventh capacitor C11, a twelfth capacitor C12, a thirteenth capacitor C13, a fourteenth capacitor C14, a fifteenth capacitor C15, a second diode D2, a third diode D3, a fourth diode D4, a seventh switch K7, and a fifth triode Q5, wherein:

a first end of the twenty-sixth resistor R26 is connected to a pin P2.5 of the STCI2C5410AD of the single chip microcomputer, a second end of the twenty-sixth resistor R26 is connected to an input end of the first inverting amplifier U2F, an output end of the first inverting amplifier U2F is connected to a cathode of the second diode D2, an anode of the second diode D2 and a first end of the twenty-eighth resistor R28 are both connected to an output end of the third inverting amplifier U2C, a second end of the twenty-eighth resistor R28 is connected to one end of the eleventh capacitor C11, and the other end of the eleventh capacitor C11 is grounded;

a first end of the twenty-seventh resistor R27 is grounded, a second end of the twenty-seventh resistor R27 is connected to an input end of the second inverting amplifier U2B, an output end of the second inverting amplifier U2B is connected to an input end of the third inverting amplifier U2C, an output end of the third inverting amplifier U2C is connected to an input end of the fourth inverting amplifier U2D, an output end of the fourth inverting amplifier U2D is connected to a first end of the thirty-first resistor R31, a second end of the thirty-first resistor R31 is connected to a base of the fifth triode Q5, a collector of the fifth triode Q5 is connected to a six-volt power supply, an emitter of the fifth triode Q5 is connected to the power supply VCC12, a first end of the thirty-second resistor R32 is connected to the power supply VCC12, and a second end of the thirty-second resistor R32 is connected to an anode of the fourth diode D4, the cathode of the fourth diode D4 is grounded, and the fourth diode D4 is a light-emitting diode;

one end of the thirteenth capacitor C13 is connected to the second end of the twenty-sixth resistor R26, and the other end of the thirteenth capacitor C13 is grounded;

a first end of the twenty-seventh resistor R27 is grounded, and a second end of the twenty-seventh resistor R27 is connected to the input end of the second inverting amplifier U2B;

one end of the twelfth capacitor C12 is grounded, the other end of the twelfth capacitor C12 is connected to the first end of the twenty-ninth resistor R29, and two ends of the seventh switch K7 are respectively connected to the first end of the twenty-ninth resistor R29 and the second end of the twenty-eighth resistor R28;

a second end of the twenty-ninth resistor R29 is connected to an output end of the second inverting amplifier U2B and a negative electrode of the third diode D3, an anode of the third diode D3 is connected to a first end of the thirty-first resistor R30 and one end of the fourteenth capacitor C14, a second end of the thirty-first resistor R30 is grounded, another end of the fourteenth capacitor C14 is connected to a positive six-volt power supply, one end of the fifteenth capacitor C15 is connected to the positive six-volt power supply, and another end of the fifteenth capacitor C15 is grounded.

The electronic switch module J may control the display module L to control the voltage in the first power module K.

Optionally, the first power module K includes a single pin J2, a first chip U1, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, a thirty-third resistor R33, a thirty-fourth resistor R34, a sixth triode Q6, a fifth diode D5, a sixth diode D6, and a sixth triode Q6, wherein:

the single row pin J2 includes five pins, and the first chip U1 includes an input terminal, an output terminal, and a ground terminal.

One end of the seventh capacitor C7, one end of the eighth capacitor C8, and one pin of the single-row pin J2 are all connected to the input end of the first chip U1, one end of the ninth capacitor C9, one end of the tenth capacitor C10, and the output end of the first chip U1 are all connected to a positive six-volt power supply, and the other end of the seventh capacitor C7, the other end of the eighth capacitor C8, the other end of the ninth capacitor C9, the other end of the tenth capacitor C10, and the ground end of the first chip U1 are all grounded;

two pins of the single-row pin J2 are connected with a P2.2 pin of the single chip microcomputer STCI2C5410 AD; three pins of the single-row pin J2 are connected with the P3.7 pin of the single chip microcomputer STCI2C5410 AD;

four pins of the single-row pin J2 are connected to a first end of a thirty-fourth resistor R34, a second end of the thirty-fourth resistor R34 is connected to a base of a sixth triode Q6, a collector of the sixth triode Q6 is connected to a first end of a thirty-third resistor R33, a second end of the thirty-third resistor R33 is connected to the power source VCC12, an anode of the fifth diode D5 and an anode of the sixth diode D6 are both connected to an emitter of the sixth triode Q6, and an anode of the fifth diode D5 and a cathode of the sixth diode D6 are both grounded;

five pins of the single-row pin J2 are grounded, and the fifth diode D5 and the sixth diode D6 are light emitting diodes.

One pin of the single-row pin J2 introduces the voltage provided by the second power supply module A into the first chip U1, so that a proper voltage is provided for the whole internal magnetic resonance ultra-low voltage potential regulation and display.

Optionally, the internal magnetic resonance power supply control module a1 includes a single pin J1, a sixteenth capacitor C16, a seventeenth capacitor C17, a twentieth capacitor C20, a twenty-first capacitor C21, a thirty-eighth resistor R38, a fifty-eighth resistor R58, a seventh transistor Q7, an eighth transistor Q8, a ninth transistor Q9, and a seventh diode D7, where:

the A1 comprises a single pin J1 which is HEADER5 and comprises five pins, and the seventh diode D7 is a zener diode.

One end of the sixteenth capacitor C16, one end of the seventeenth capacitor C17, a first end of the fifty-eighth resistor R58, and a first end of the thirty-eighth resistor R38 are all connected to one pin of the single pin J1, the other end of the sixteenth capacitor C16 and the other end of the seventeenth capacitor C17 are all grounded, a second end of the fifty-eighth resistor R58 is connected to an emitter of the eighth transistor Q8, a base of the eighth transistor Q8 is connected to a collector of the seventh transistor Q7, a cathode of the seventh diode D7 and a base of the ninth transistor Q9 are all connected to a collector of the eighth transistor Q8;

a base electrode of the seventh triode Q7 and one end of the twentieth capacitor C20 are both connected to two pins of the single-pin J1, an emitter electrode of the seventh triode Q7, the other end of the twentieth capacitor C20, an anode of the seventh diode D7 and one end of the twenty-first capacitor C21 are all grounded, the other end of the twenty-first capacitor C21 and an emitter electrode of the ninth triode Q9 are both connected to the power supply VCC12, and a collector electrode of the ninth triode Q9 is connected to a second end of the thirty-eighth resistor R38;

four pins of the single-row pin J1 are grounded, and one pin, three pins and five pins of the single-row pin J1 are connected with the internal magnetic resonance ultralow voltage potential regulating and controlling module B.

The voltage provided by the second power supply module a forms an internal magnetic resonance power supply control circuit, namely the internal magnetic resonance power supply control module a1, and the two pins of the single-row pin J1 control the on-off of the seventh triode Q7, the eighth triode Q8 and the ninth triode Q9 to control the power supply of the internal magnetic resonance.

Optionally, the internal magnetic resonance ultra-low voltage potential regulation and control module B includes a chip BIT3715U4, a thirty-fifth resistor R35, a thirty-sixth resistor R36, a thirty-seventh resistor R37, a thirty-ninth resistor R39, a forty-resistor R40, a forty-first resistor R41, a forty-second resistor R41, a forty-third resistor R41, a forty-fourth resistor R41, a forty-fifth resistor R41, a forty-sixth resistor R41, a forty-seventh resistor R41, a forty-eighth resistor R41, a forty-ninth resistor R41, a fifty-fifth resistor R41, a fifty-third resistor R41, a fourth resistor R41, a fifth resistor R41, a sixth resistor R41, an eighteenth capacitor C41, a nineteenth capacitor C41, a twenty-eighth capacitor C41, a thirty-ninth capacitor C, A thirty-seventh capacitor C37, a thirty-eighth capacitor C38, a thirty-ninth capacitor C39, a fortieth capacitor C40, an eighth diode D8, a ninth diode D9, a twelfth diode D10, an eleventh diode D11, a twentieth diode D20, a twenty-first diode D21, a twenty-third diode D23, a twenty-fourth diode D24, a thirteenth diode Q10, and an eleventh triode Q11, wherein:

the chip BIT3715U4 includes sixteen pins.

A first end of the thirty-fifth resistor R35 is connected to three pins of the single-row pin J1, a second end of the thirty-fifth resistor R35 is connected to a first end of the thirty-seventh resistor R37, a first end of the thirty-sixth resistor R36 is connected to the power supply VCC12, one end of the eighteenth capacitor C18, a first end of the thirty-seventh resistor R37, and thirteen pins of the chip BIT3715U4 are all connected to a second end of the thirty-sixth resistor R36, the other end of the eighteenth capacitor C18, a second end of the thirty-seventh resistor R37, and one end of the nineteenth capacitor C19 are all grounded, and the other end of the nineteenth capacitor C19 is connected to a twelve pin of the chip BIT3715U 4;

a first end of the fifty-fifth resistor R50 is connected to an eleventh pin of the chip BIT3715U4, a second end of the fifty-fifth resistor R50, a first pin of the chip BIT3715U4 and one end of the thirty-fifth capacitor C35 are connected to a first end of the fifty-first resistor R51, another end of the thirty-fifth capacitor C35 is connected to a second pin of the chip BIT3715U4, a second end of the fifty-first resistor R51 and a first end of the forty-eighth resistor R48 are connected to a first end of the fifty-second resistor R52, a second end of the fifty-second resistor R52 is grounded, a second end of the forty-eighth resistor R48 and a first end of the forty-seventh resistor R47 are connected to a first end of the forty-ninth resistor R49, and a second end of the forty-ninth resistor R49 is grounded;

a first end of the fifty-third resistor R53, one end of the thirty-sixth capacitor C36, one end of the thirty-seventh capacitor C37 and one end of the thirty-eighth capacitor C38 are respectively connected to three pins, four pins, five pins and six pins of the chip BIT3715U4, a second end of the fifty-third resistor R53, the other end of the thirty-sixth capacitor C36, the other end of the thirty-seventh capacitor C37 and the other end of the thirty-eighth capacitor C38 are all grounded, a first end of the thirty-ninth resistor R39 is connected to six pins of the chip BIT3715U4, and a second end of the thirty-ninth resistor R39 is connected to the power source VCC 12;

one end of the twenty-second capacitor C22 is connected to the nine pin of the BIT3715U4, the other end of the twenty-second capacitor C22, the first end of the forty-second resistor R40, and the base of the thirteenth diode Q10 are all connected to the anode of the eighth diode D8, the second end of the forty-second resistor R40 and the cathode of the eighth diode D8 are all connected to one pin of the single-row pin J1, the collector of the thirteenth diode Q10 is connected to one end of the twenty-third capacitor C23, the other end of the twenty-third capacitor C23 is grounded, the emitter of the thirteenth diode Q10 is connected to the collector of the eleventh transistor Q11, the base of the eleventh transistor Q11 and the anode of the ninth diode D9 are all connected to the first end of the forty-first resistor R41, the second end of the forty-first resistor R41 and the cathode of the ninth diode D9 are all connected to the eight pin 4U 372, the emitter of the eleventh triode Q11 is grounded;

an emitter of the thirteenth polar tube Q10 and a collector of the eleventh polar tube Q11 are both connected with the internal magnetic resonance ultra-low voltage potential generating module C;

one end of the thirty-ninth capacitor C39, the first end of the fifty-fifth resistor R55 and the cathode of the twenty-third diode D23 are all connected to a fifteen pin of the chip BIT3715U4, the other end of the thirty-ninth capacitor C39, the second end of the fifty-fifth resistor R55 and one end of the forty-fourth capacitor C40 are all grounded, the anode of the twenty-third diode D23 and the anode of the twenty-fourth diode D24 are all connected to the first end of the fifty-fourth resistor R54, the second end of the fifty-fourth resistor R54 is connected to the VCC12, the other end of the forty-capacitor C40 and the first end of the fifty-sixth resistor R56 are all connected to the cathode of the twenty-fourth diode D24, the second end of the sixth resistor R56 and the cathode of the twenty-first diode D21 are all connected to the second end of the forty-seventh resistor R47;

a cathode of the twentieth diode D20 and one end of the thirty-first capacitor C31 are both connected to an anode of the twenty-first diode D21, an anode of the twentieth diode D20 is grounded, the other end of the thirty-first capacitor C31 and one end of the twenty-ninth capacitor C29 are both connected to a first end of the forty-third resistor R43, a first end of the forty-second resistor R42, a first end of the forty-third resistor R43 and one end of the twenty-eighth capacitor C28 are all grounded, and the other end of the twenty-eighth capacitor C28, a second end of the forty-second resistor R42 and a second end of the forty-third resistor R43 are all connected to a five-pin of the single-row pin J1;

one end of the thirty-first capacitor C30, the cathode of the twelfth diode D10 and the other end of the twenty-ninth capacitor C29 are all connected to the anode of the eleventh diode D11, the other end of the thirty-first capacitor C30 and the anode of the twelfth diode D10 are all grounded, the cathode of the eleventh diode D11 is connected to the first end of the forty-fourth resistor R44, and the second end of the forty-fourth resistor R44 is grounded;

ten pins of the chip BIT3715U4 are connected with the fourteenth power supply, and seven pins, fourteen pins and sixteen pins of the chip BIT3715U4 are all grounded.

After the internal magnetic resonance power supply control module A1 supplies power to the chip BIT3715U4, a fifty-third resistor R53, a thirty-sixth capacitor C36 to a thirty-eighth capacitor C38 of a peripheral circuit of the chip BIT3715U4 form an RC circuit, and PWM with different duty ratios is input into a pin 3 of the single-row pin J1, so that continuous pulses with different duty ratios of 50KHz to 90KHz are output from an eight pin and a nine pin of the chip BIT3715U4 to control the on-off of the thirteenth polar tube Q10 and the eleventh polar tube Q11.

Optionally, the internal magnetic resonance ultra-low voltage potential generating module C includes a transformer T1, a twenty-fourth capacitor C24, a twenty-fifth capacitor C25, a twenty-sixth capacitor C26, a twenty-seventh capacitor C27, a twelfth diode D12, a thirteenth diode D13, a fourteenth diode D14, a fifteenth diode D15, a sixteenth diode D16, a seventeenth diode D17, an eighteenth diode D18, a nineteenth diode D19, a second inductor L2, a fifty-ninth resistor R59, wherein:

an emitter of the thirteenth diode Q10 and a collector of the eleventh triode Q11 are both connected to the primary coil of the transformer T1, one end of the twenty-fourth capacitor C24, one end of the twenty-fifth capacitor C25, one end of the twenty-sixth capacitor C26 and one end of the twenty-seventh capacitor C27 are all connected to the primary coil of the transformer T1, and the other end of the twenty-fourth capacitor C24, the other end of the twenty-fifth capacitor C25, the other end of the twenty-sixth capacitor C26 and the other end of the twenty-seventh capacitor C27 are all grounded;

an anode of the nineteenth diode D19, an anode of the twelfth diode D12, an anode of the sixteenth diode D16, and an anode of the fifteenth diode D15 are all connected to the secondary winding of the transformer T1, a cathode of the nineteenth diode D19, a cathode of the twelfth diode D12, a cathode of the sixteenth diode D16, and a cathode of the fifteenth diode D15 are respectively connected to an anode of the eighteenth diode D18, an anode of the thirteenth diode D13, an anode of the seventeenth diode D17, and an anode of the fourteenth diode D14, and a cathode of the eighteenth diode D18, an anode of the thirteenth diode D13, a cathode of the seventeenth diode D17, and a cathode of the fourteenth diode D14 are all connected to ground;

the secondary coil of the transformer T1 is connected, and the secondary coil of the transformer T1 is connected with a load.

The transformer T1 is driven by the switching characteristics of a thirteenth polar tube Q10 and an eleventh polar tube Q11 of the internal magnetic resonance ultra-low voltage potential regulating and controlling module B, and an electric field is formed on the secondary side of the transformer T1 through the twelfth capacitor D12 and the periphery of a nineteenth capacitor D19.

According to the technical scheme, the system for treating the hypertension comprises a regulation module M for regulating and controlling the internal magnetic resonance ultralow voltage potential and displaying, a display module L for regulating and controlling countdown and internal magnetic resonance ultralow voltage potential, an electronic switch module J for controlling the regulation module M, wherein the regulation module M is connected with the display module L, the first power supply module K and the electronic switch module J, the internal magnetic resonance power supply control module A1 is connected with the internal magnetic resonance ultralow voltage potential regulation module B, the internal magnetic resonance ultralow voltage potential regulation module B is connected with the internal magnetic resonance ultralow voltage potential generation module C, the second power supply module A is used for providing voltage required by the regulation module M, the display module L, the electronic switch module J, the first power supply module K, the internal magnetic resonance power supply module A1, the internal magnetic resonance voltage regulation module B and the internal magnetic resonance voltage potential generation control module C, the regulation module A and the internal magnetic resonance power supply control module C can provide voltage required by the ultralow voltage regulation module M, the ultralow voltage, the first power supply module K, the internal magnetic resonance power supply module A4690, the internal magnetic resonance ultralow voltage regulation module K and the internal magnetic resonance ultralow voltage control module K, the internal magnetic resonance voltage generation control module K can provide the voltage for the first ultralow resonance ultralow voltage potential regulation module K, the internal magnetic resonance ultralow resonance voltage potential regulation module K, the internal magnetic resonance ultralow voltage control module K-to the internal magnetic resonance ultralow resonance voltage regulation module K, the internal magnetic resonance voltage regulation module K-to provide the whole high voltage generation control module K, the electronic switch module K-potential generation control module K, the high voltage generation control module K-low voltage generation module K, the high voltage potential generation module K-low-voltage potential generation module K for the high-low-voltage potential generation and the electronic switch module K, the high voltage resonance.

Referring to fig. 17, a device for treating hypertension, the system for treating hypertension is used for the device for treating hypertension, includes a host, the system for treating hypertension is arranged in the host, the host generates and outputs biological negative electrons, the host is connected with the biological electronic acupoint targeted irradiator, the bioelectronic acupoint targeted irradiator is an acupoint action circuit, which is described in patent CN201420269022.3, and receives negative potential generated by the internal magnetic resonance ultralow voltage potential generation module C, and the acupoint action circuit supplements negative charge to erythrocytes via channels and acupoints related to hypertension, then the membrane potential of the red blood cells is restored to a normal value of-10 mV, the charge repulsion force of the same level among the red blood cells is restored, the blood viscosity is improved, and the hypertension is recovered after the recovery at the cell level. Meanwhile, the bioelectronic acupuncture device is connected with the grounding end of the host, stimulates the related meridian points of hypertension by using the traditional Chinese medicine manipulation skill, strengthens the effect of the conduction bioelectronic on organ weak cells (such as weak red blood cells) touched by hypertension diseases, repairs the cells, recovers the normal functions of the cells, and strengthens the recovery effect of hypertension from the disease roots at the cell level.

According to the system for treating hypertension, the data analysis table of the clinical cases of reducing the drug and lowering the blood pressure in hospitals is as follows:

TABLE 1

TABLE 2

Table 1 is a data analysis table of the blood pressure reduction treatment course after drug reduction, table 2 is a data table of western medicine for reducing blood pressure, it can be seen that the inefficiency is 0%, and table 1 and table 2 are abstracted from the clinical report of the second hospital affiliated to Chongqing medical university of Hospital Authority.

The device for treating hypertension according to the present invention ablates arterial plaque and reduces the effect of tunica media thickness in arterial vessel as shown in table 3:

TABLE 3

Referring to fig. 18, for sixty samples of western medicine for controlling hypertension (pathological index ≧ 140mmHg) in treatment, the recovery is only four days from recovery treatment by using new BET (Bio eleic Trocs, abbreviated as BET) traditional Chinese medicine, and the hypertension index (pathological index ≧ 140mmHg) returns to the normal blood pressure index (136 mmHg). After the blood pressure reduction western medicines are reduced, the blood pressure reduction efficiency is 0%, and the obvious effect of normal blood pressure can be achieved without increasing the medicine amount.

The treatment mechanism of the device is as follows: the bioelectronic targeting acupoint irradiator forms-10 to-160 v to form low-voltage direct current negative electric field force, which acts on the related meridian and acupuncture points for the rehabilitation of hypertension. Such as Shenshu point, Baihui point, Sishencong point, Fengfu point, Fengchi point, Taiyang point and Ashi point, meanwhile, the biological electronic acupuncture device is used, the technical techniques of traditional Chinese medicine acupuncture, massage, scraping, pushing, massaging and the like are innovatively applied, bioelectricity acupuncture and moxibustion carding stimulation is carried out on the conception vessel, the governor vessel, the head, the neck, the chest, the abdomen and the back channel of the patient, the principle that positive and negative charges attract each other is utilized, the repulsion of the same charges is weakened due to lack of negative charges, but gather and overlap to form blood stasis and blood stain or plaque to block blood vessels, generate red blood cells for replenishing negative charges, repairing the membrane potential of the red blood cells to a normal value of-10 mV, recovering the charge repulsion of the same level among the red blood cells, improving the blood viscosity, clearing blood, removing blood stasis, activating blood circulation, ablating the plaque, at the cellular level, the hypertension and the complicating diseases of the hypertension and the cardiovascular and cerebrovascular diseases are completely recovered and cured from the disease roots.

The invention relates to a traditional Chinese medicine special rehabilitation treatment device for hypertension healing BET (biological electronegative electrons, English Bio Elie Trocs, abbreviated as BET), which breaks through the traditional technology of bionic electrotherapy factors in the electrotherapy device industry at home and abroad at present. By utilizing a positive and negative charge attraction principle and a novel electro-acupuncture stimulation method of BET negative electrons on meridian points of traditional Chinese medicine related to hypertension, the novel electro-acupuncture stimulation method directly supplies negative charges to red blood cells which are gathered and overlapped to form blood stasis and blood stains and block blood vessels due to insufficient negative charges, excessive positive charges and weakened or lost negative charge repulsion at the same level in blood of a hypertension patient, accurately restores the weakened red blood cell membrane potential to a normal value (-10mV), restores negative charge repulsion at the same level in the red blood cells, improves blood viscosity, removes the blood stasis and blood stains, unblocks blood, and promotes rehabilitation of hypertensive cardiovascular and cerebrovascular diseases from disease roots at a cell level.

According to the technical scheme, the targeted irradiator and the biological electronic acupuncture device for treating the hypertension simultaneously stimulate channels and collaterals related to the hypertension, supplement negative charges to red blood cells, restore membrane potential, recover electric charge repulsion force at the same level of the weakened red blood cells, improve blood viscosity, clear blood, and completely recover and heal the hypertensive cardiovascular and cerebrovascular diseases from disease roots at the cell level.

The foregoing is merely a detailed description of the invention, and it should be noted that modifications and adaptations by those skilled in the art may be made without departing from the principles of the invention, and should be considered as within the scope of the invention.