阅读说明：本技术 一种mos结构沟槽二极管器件及其制造方法 (MOS structure groove diode device and manufacturing method thereof ) 是由 陈晓伦 韩笑 朱涛 鞠柯 孟军 徐励远 于 2020-03-05 设计创作，主要内容包括：本发明公开了一种MOS结构沟槽二极管器件及其制造方法,包括从下至上依次设置的硅衬底、外延层,外延层上开设有依次排布原胞沟槽、原胞大沟槽、延展沟槽以及截止沟槽；原胞沟槽、原胞大沟槽、延展沟槽以及截止沟槽内侧壁依次设有二氧化硅外层以及多晶硅填充层；外延层上位于相邻的两个原胞沟槽之间的区域设有栅氧化层,栅氧化层的上方设有多晶硅层；原胞沟槽、原胞大沟槽、延展沟槽以及截止沟槽的顶部左右两侧设置有第一掺杂区以及第二掺杂区；原胞沟槽顶部的左右两侧以及原胞大沟槽靠近原胞沟槽侧设置有第三掺杂区,还包括左右设置的第一金属层以及第二金属层。本发明通过引入了沟槽MOS的分压及电场屏蔽效果,改进了器件性能,拓宽了适用领域。(The invention discloses a trench diode device with a MOS structure and a manufacturing method thereof, wherein the trench diode device comprises a silicon substrate and an epitaxial layer which are sequentially arranged from bottom to top, and a cell trench, a cell big trench, an extension trench and a stop trench which are sequentially distributed are arranged on the epitaxial layer; the inner side walls of the cell groove, the cell big groove, the extension groove and the stop groove are sequentially provided with a silicon dioxide outer layer and a polycrystalline silicon filling layer; a gate oxide layer is arranged in a region between two adjacent primitive cell trenches on the epitaxial layer, and a polycrystalline silicon layer is arranged above the gate oxide layer; the left side and the right side of the top of the cell groove, the cell big groove, the extension groove and the cut-off groove are provided with a first doping area and a second doping area; the left and right sides of the top of the cell groove and the side of the large cell groove close to the cell groove are provided with third doped regions, and the cell groove structure further comprises a first metal layer and a second metal layer which are arranged left and right. According to the invention, the partial pressure and electric field shielding effect of the groove MOS are introduced, so that the device performance is improved, and the application field is widened.)

1. A trench diode device with an MOS structure comprises a silicon substrate with a first conductivity type and an epitaxial layer with the first conductivity type, which are sequentially arranged from bottom to top, and is characterized in that at least two primitive cell trenches, a primitive cell large trench, an extension trench and a stop trench are sequentially arranged on the epitaxial layer from left to right, and the width of the primitive cell trench is smaller than that of the primitive cell large trench;

the inner side walls of the cell groove, the large cell groove, the extension groove and the stop groove are sequentially provided with a silicon dioxide outer layer and a polycrystalline silicon filling layer;

a gate oxide layer is arranged in the region between two adjacent cell grooves and between the cell groove and the large cell groove on the epitaxial layer, and a polycrystalline silicon layer of a first conduction type is arranged above the gate oxide layer;

the left side and the right side of the top of the cell groove, the cell big groove, the extension groove and the cut-off groove are provided with a first doping area and a second doping area of a second conduction type; the second doped region is positioned above the first doped region;

third doped regions of the first conductivity type are arranged on the left side and the right side of the top of the cell groove and on the side, close to the cell groove, of the large cell groove, and the third doped regions are located above the second doped regions;

a field oxide layer is arranged in the region, located on the right side of the cell large groove, of the epitaxial layer;

the first metal layer is positioned above the cell groove, the cell big groove and the extension groove, the first metal layer is in short circuit with the polycrystalline silicon filling layer of the cell groove, the cell big groove and the extension groove, and the first metal layer is in short circuit with the second doping area, the third doping area and the polycrystalline silicon layer;

the second metal layer is positioned above the cut-off groove and is in short connection with the polycrystalline silicon filling layer of the cut-off groove;

the first metal layer and the second metal layer are separated from the field oxide layer through the silicon dioxide outer layer.

2. The MOS structure trench diode device of claim 1, wherein: the depth of all the silicon grooves is 1.5-4.0 μm.

3. The MOS structure trench diode device of claim 1, wherein: the width of the primitive cell groove is 0.5-1.0 μm;

the width of the large groove of the primitive cell is 0.8-1.2 μm;

the width of the extension groove is 0.5-1.0 μm;

the width of the cut-off groove is 0.5-1.2 mu m.

4. A MOS structure trench diode device according to claim 3, wherein: when the first conductive type is P type, the second conductive type is N type;

or, when the first conductive type is N-type, the second conductive type is P-type.

5. The MOS structure trench diode device of claim 1, wherein: the distance between the groove centers of the adjacent primitive cell grooves is 1.5-4.0 μm.

6. The method for manufacturing a trench diode device of a MOS structure according to any one of claims 1 to 5, wherein: growing an epitaxial layer of a first conduction type on a silicon substrate of the first conduction type, and growing a field oxide layer on the epitaxial layer by adopting a thermal oxidation process;

coating a first photoresist layer on the field oxide layer, exposing and developing the first photoresist layer to form a pattern, etching the field oxide layer by using a dry method to form a first process window, realizing local exposure of the epitaxial layer, and removing the first photoresist layer;

growing a gate oxide layer on the exposed part of the epitaxial layer by adopting a thermal oxidation process;

depositing an in-situ doped first conductive type polycrystalline silicon layer on the outermost layer by adopting a CVD (chemical vapor deposition) process, and depositing undoped SiO (silicon dioxide) on the polycrystalline silicon layer by adopting the CVD process₂Layer of said SiO₂Depositing a second photoresist layer on the layer;

step four, forming a photoresist pattern on the second photoresist layer by adopting a photoetching process, and gradually etching SiO by adopting a dry etching process₂A layer and a polysilicon layer, the second photoresist layer being retained;

step five, using the reserved second photoresist layer and the field oxide layer as masking films, adopting an ion implantation process, wherein the ion implantation energy is 80 keV-200 keV, forming a first doped region of a second conduction type, and removing the second photoresist layer after the ion implantation process is finished;

step six, utilizing the polysilicon layer and SiO₂The layer and the field oxide layer are used as masking films, an ion implantation process is adopted, the ion implantation energy is 20 keV-80 keV, and a second doping area of a second conduction type is formed above the first doping area; finally, a rapid annealing process or a furnace tube thermal annealing process is adopted to carry out ion implantation activation and diffusion;

forming a third photoresist layer by adopting a photoetching process, masking by utilizing the third photoresist layer, forming a third doped region of the first conductivity type above the second doped region by adopting an ion implantation process, wherein the ion implantation energy is 20 keV-80 keV, and removing the third photoresist layer;

step eight, uniformly etching and removing the gate oxide layer exposed on the outermost layer by adopting a dry etching process, wherein the etching thickness is greater than that of the gate oxide layer;

using retained SiO₂The layer and the field oxide layer are used as masking films, a silicon groove etching process is adopted, and silicon grooves are etched and respectively comprise a cell groove, a large cell groove, an extension groove and a stop groove;

uniformly depositing a layer of undoped silicon dioxide outer layer on the side wall and the outermost surface of the etched silicon trench by adopting a CVD (chemical vapor deposition) process;

uniformly depositing an in-situ doped first conductive type polycrystalline silicon filling layer on the surface of the side wall of the silicon groove and the outermost surface by adopting a CVD (chemical vapor deposition) process, wherein the polycrystalline silicon filling layer fills the inside of the groove;

forming self-masking by utilizing the outer layer of the silicon dioxide, carrying out polysilicon back etching by adopting a dry etching process, and removing the polysilicon filling layer deposited in the step above the first doping area;

step ten, forming a fourth photoresist layer by adopting a photoetching process, realizing the masking of a region from the center of the large groove of the primitive cell to the side close to the extension groove, and simultaneously masking the extension groove and the stop groove;

removing the silicon dioxide outer layer and SiO in the non-masking region by utilizing an isotropic wet etching or dry etching process₂A layer;

removing the fourth photoresist layer after the completion;

step eleven, activating the third doping area and the in-situ doped polycrystalline silicon filling layer doped impurities by adopting a rapid annealing process or a furnace tube thermal annealing process;

step twelve, adopting sputtering or CVD technology to deposit a layer of metal film on the outermost surface;

and corroding the metal film by adopting a photoetching process to form a first metal layer and a second metal layer which are separated.

7. The method of manufacturing a trench diode device having a MOS structure according to claim 6, wherein: in the first step, the thickness of the field oxide layer is 0.5-1.0 μm;

in the second stepThe thickness of the gate oxide layer is

The thickness of the polysilicon layer is 0.1-0.3 μm;

SiO₂the thickness of the layer is 0.1 to 0.2 μm.

8. The method of manufacturing a trench diode device having a MOS structure according to claim 6, wherein: in the fifth step, the implantation dosage of the first doping region is within the range of 2E 12-5E 13;

in the sixth step, the implantation dosage of the second doping region is within the range of 1E 13-5E 14;

in the seventh step, the implantation dosage of the third doping region is within the range of 5E 14-5E 15.

9. The method of manufacturing a trench diode device having a MOS structure according to claim 7, wherein: step six, when a rapid annealing process is adopted, the temperature is 950-1100 ℃, and the time is 30-120S;

when the furnace tube thermal annealing process is adopted, the temperature is 900-1000 ℃ and the time is 30-60 min.

10. The method of manufacturing a trench diode device having a MOS structure according to claim 6, wherein: the depth of all the silicon grooves is 2.5-3.0 μm;

the width of the primitive cell groove is 0.8-1.0 μm;

the width of the large groove of the primitive cell is 1.0-1.2 mu m;

the width of the extension groove is 0.8-1.0 μm;

the width of the cut-off groove is 0.8-1.2 mu m.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a diode device and a manufacturing method thereof.

Background

The diode device with the MOS structure is a novel low-power-consumption diode rectifying device, and has lower forward voltage drop compared with a common PN junction diode; compared with the common Schottky diode, the Schottky diode has lower high-temperature reverse leakage, so that the Schottky diode is suitable for application occasions requiring lower forward voltage drop and lower high-temperature reverse leakage.

However, the diode device with the existing MOS structure has defects, the electrical characteristics of the diode device are similar to those of a Schottky diode, the reverse leakage and the forward voltage drop of the diode device are a pair of contradictory parameters, and the leakage of all diodes rises along with the rise of the temperature; after the balance is obtained, the reverse leakage characteristics of the diode are not as good as those of a PN junction diode, the diode has no obvious advantage over a common Schottky in forward voltage drop, and the manufacturing process complexity and the cost are much higher than those of the common PN junction or Schottky diode, so that the application occasion of a diode device with a traditional MOS structure is limited.

Disclosure of Invention

Aiming at the problems in the prior art, the invention provides a trench diode device with an MOS structure, which aims to solve the technical problem that the characteristics of low and high temperature leakage and low forward voltage cannot be realized at the same time. Therefore, the invention also provides a manufacturing method of the MOS structure groove diode device.

In order to achieve the above object, the present invention provides a trench diode device with a MOS structure, which includes a silicon substrate of a first conductivity type and an epitaxial layer of the first conductivity type sequentially arranged from bottom to top, and is characterized in that at least two cell trenches, a cell large trench, an extension trench, and a stop trench are sequentially arranged on the epitaxial layer from left to right, and the width of the cell trench is smaller than that of the cell large trench;

the inner side walls of the cell groove, the large cell groove, the extension groove and the stop groove are sequentially provided with a silicon dioxide outer layer and a polycrystalline silicon filling layer;

a gate oxide layer is arranged in the region between two adjacent cell grooves and between the cell groove and the large cell groove on the epitaxial layer, and a polycrystalline silicon layer of a first conduction type is arranged above the gate oxide layer;

the left side and the right side of the top of the cell groove, the cell big groove, the extension groove and the cut-off groove are provided with a first doping area and a second doping area of a second conduction type; the second doped region is positioned above the first doped region;

third doped regions of the first conductivity type are arranged on the left side and the right side of the top of the cell groove and on the side, close to the cell groove, of the large cell groove, and the third doped regions are located above the second doped regions;

a field oxide layer is arranged in the region, located on the right side of the cell large groove, of the epitaxial layer;

the first metal layer is positioned above the cell groove, the cell big groove and the extension groove, the first metal layer is in short circuit with the polycrystalline silicon filling layer of the cell groove, the cell big groove and the extension groove, and the first metal layer is in short circuit with the second doping area, the third doping area and the polycrystalline silicon layer;

the second metal layer is positioned above the cut-off groove and is in short connection with the polycrystalline silicon filling layer of the cut-off groove;

the first metal layer and the second metal layer are separated from the field oxide layer through the silicon dioxide outer layer.

According to the invention, through introducing the MOS structure of the groove, the low-high temperature reverse leakage characteristic of the traditional MOS structure diode device and the low forward voltage drop characteristic of the Schottky diode with the novel TMBS structure are comprehensively realized by utilizing the oxide partial pressure in the MOS structure and the electric field shielding of the PN junction of the source region between the adjacent grooves, the device performance is improved, and the application field is widened. Through the structural design of the cut-off channel, the leakage of the cut-off surface channel is further realized. The requirement of the manufacturing photoetching process is reduced through the design of the large grooves of the primitive cells; and through the design of the extension channel, the concentration of an electric field at the terminal is weakened, and the breakdown voltage is improved.

Further preferably, the first conductivity type is P-type, and the second conductivity type is N-type.

Or the first conduction type is an N type, and the second conduction type is a P type.

Further preferably, the depth of all the silicon trenches is 1.5 μm to 4.0. mu.m.

More preferably, the width of the primitive cell groove is 0.5-1.0 μm;

the width of the large groove of the primitive cell is 0.8-1.2 μm;

the width of the extension groove is 0.5-1.0 μm;

the width of the cut-off groove is 0.5-1.2 mu m.

The distance between the groove centers of the adjacent primitive cell grooves is 1.5-4.0 μm.

Preferably, the reverse operating voltage is 100V.

The depth of all the silicon grooves is 2.5-3.0 μm;

more preferably, the width of the primitive cell groove is 0.8-1.0 μm;

the width of the large groove of the primitive cell is 1.0-1.2 mu m;

the width of the extension groove is 0.8-1.0 μm;

the width of the cut-off groove is 0.8-1.2 mu m.

The distance between the groove centers of the adjacent primitive cell grooves is 2.0-2.5 mu m.

The resistivity of the epitaxial layer is 1.0-1.1 omega-cm, and the thickness is 7.0-7.5 mu m.

When the parameter is that the reverse working voltage is 100V, the resistivity and the thickness of the epitaxial layer are greatly reduced under the condition that the reverse breakdown voltage of the device is kept unchanged, and further more advantageous forward conduction voltage is obtained.

The manufacturing method of the MOS structure groove diode device is characterized by comprising the following steps:

growing an epitaxial layer of a first conduction type on a silicon substrate of the first conduction type, and growing a field oxide layer on the epitaxial layer by adopting a thermal oxidation process;

coating a first photoresist layer on the field oxide layer, exposing and developing the first photoresist layer to form a pattern, etching the field oxide layer by using a dry method to form a first process window, realizing local exposure of the epitaxial layer, and removing the first photoresist layer;

growing a gate oxide layer on the exposed part of the epitaxial layer by adopting a thermal oxidation process;

then depositing an in-situ doped first conductive type silicon crystal layer on the outermost layer by adopting a CVD (chemical vapor deposition) process, and depositing undoped SiO (silicon dioxide) on the polycrystalline silicon layer by adopting the CVD process₂Layer of said SiO₂Depositing a second photoresist layer on the layer;

step four, forming a photoresist pattern on the second photoresist layer by adopting a photoetching process, and gradually etching SiO by adopting a dry etching process₂A layer and a polysilicon layer, the second photoresist layer being retained;

step five, using the reserved second photoresist layer and the field oxide layer as masking films, adopting an ion implantation process, wherein the ion implantation energy is 80 keV-200 keV, forming a first doped region of a second conduction type, and removing the second photoresist layer after the ion implantation process is finished;

step six, utilizing the polysilicon layer and SiO₂The layer and the field oxide layer are used as masking films, an ion implantation process is adopted, the ion implantation energy is 20 keV-80 keV, and a second doping area of a second conduction type is formed above the first doping area; finally, a rapid annealing process or a furnace tube thermal annealing process is adopted to carry out ion implantation activation and diffusion;

forming a third photoresist layer by adopting a photoetching process, masking by utilizing the third photoresist layer, forming a third doped region of the first conductivity type above the second doped region by adopting an ion implantation process, wherein the ion implantation energy is 20 keV-80 keV, and removing the third photoresist layer;

step eight, uniformly etching and removing the gate oxide layer exposed on the outermost layer by adopting a dry etching process, wherein the etching thickness is greater than that of the gate oxide layer;

by retention of SiO₂The layer and the field oxide layer are used as masking films, a silicon groove etching process is adopted, and silicon grooves are etched and respectively comprise a cell groove, a large cell groove, an extension groove and a stop groove;

uniformly depositing a layer of undoped silicon dioxide outer layer on the side wall and the outermost surface of the etched silicon trench by adopting a CVD (chemical vapor deposition) process;

uniformly depositing an in-situ doped first conductive type polycrystalline silicon filling layer on the surface of the side wall of the silicon groove and the outermost surface by adopting a CVD (chemical vapor deposition) process, wherein the polycrystalline silicon filling layer fills the inside of the groove;

forming self-masking by utilizing the outer layer of the silicon dioxide, carrying out polysilicon back etching by adopting a dry etching process, and removing the polysilicon filling layer deposited in the step above the first doping area;

step ten, forming a fourth photoresist layer by adopting a photoetching process, realizing the masking of a region from the center of the large groove of the primitive cell to the side close to the extension groove, and simultaneously masking the extension groove and the stop groove;

removing the silicon dioxide outer layer and SiO in the non-masking region by utilizing an isotropic wet etching or dry etching process₂A layer;

removing the fourth photoresist layer after the completion;

step eleven, activating and activating the third doping area and the in-situ doped polycrystalline silicon filling layer doped impurities by adopting a rapid annealing process or a furnace tube thermal annealing process;

step twelve, adopting sputtering or CVD technology to deposit a layer of metal film on the outermost surface;

and corroding the metal film by adopting a photoetching process to form a first metal layer and a second metal layer which are separated.

More preferably, the silicon substrate has a resistivity of 0.001 Ω · cm to 0.02 Ω · cm.

More preferably, in the first step, the thickness of the field oxide layer is 0.5 μm to 1.0 μm.

In the second step, the thickness of the gate oxide layer is

The thickness of the polysilicon layer is 0.1-0.3 μm;

SiO₂the thickness of the layer is 0.1 to 0.2 μm.

In the fifth step, the implantation dosage of the first doping region is within the range of 2E 12-5E 13.

In the sixth step, the implantation dosage of the second doping region is within the range of 1E 13-5E 14.

In the seventh step, the implantation dosage of the third doping region is within the range of 5E 14-5E 15.

Further preferably, in the sixth step, when a rapid annealing process is adopted, the temperature is 950 ℃ to 1100 ℃ and the time is 30S to 120S;

when the furnace tube thermal annealing process is adopted, the temperature is 900-1000 ℃ and the time is 30-60 min.

Further preferably, the depth of all the silicon trenches is 1.5 μm to 4.0. mu.m.

More preferably, the width of the primitive cell groove is 0.5-1.0 μm;

the width of the large groove of the primitive cell is 0.8-1.2 μm;

the width of the extension groove is 0.5-1.0 μm;

the width of the cut-off groove is 0.5-1.2 mu m;

the distance between the groove centers of the adjacent primitive cell grooves is 1.5-4.0 μm.

Preferably, after the twelfth step, the furnace tube alloying process is finally used to alloy the metal film with the contacted silicon, so as to reduce the contact resistance.

Further preferably, the temperature of the furnace tube alloying process is 420-450 ℃ and the time is 30-60 min.

Compared with the prior art, the invention has the advantages that:

the trench MOS structure is introduced into the existing MOS structure diode, the reverse breakdown voltage of the device is improved by utilizing the oxide partial pressure in the MOS structure and the electric field shielding of the PN junction of the source region between the adjacent trenches, so that the resistivity and the thickness of an epitaxial layer can be greatly reduced under the condition of maintaining the reverse breakdown voltage of the device unchanged, and further, the more advantageous forward voltage drop is obtained. The low-high temperature leakage characteristic of the MOS structure diode and the low forward voltage drop characteristic of the TMBS structure Schottky diode are comprehensively considered; through ingenious process flow design, the adopted process is compatible with the existing MOS structure diode and TMBS structure Schottky diode, and is beneficial to industrialization and reduction of research, development and manufacturing cost.

Drawings

FIG. 1 is a schematic cross-sectional view of the present invention;

FIG. 2 is a cross-sectional view after step one of embodiment 1 of the present invention;

FIG. 3 is a cross-sectional view after step two of embodiment 1 of the present invention;

FIG. 4 is a cross-sectional view after step three of embodiment 1 of the present invention;

FIG. 5 is a cross-sectional view after step four of embodiment 1 of the present invention;

FIG. 6 is a cross-sectional view after step five of embodiment 1 of the present invention;

FIG. 7 is a cross-sectional view after step six of example 1 of the present invention;

FIG. 8 is a cross-sectional view after step seven of embodiment 1 of the present invention;

FIG. 9 is a cross-sectional view after step eight according to embodiment 1 of the present invention;

FIG. 10 is a cross-sectional view after step nine of example 1 of the present invention;

FIG. 11 is a cross-sectional view of step ten (a) of embodiment 1 of the present invention;

FIG. 12 is a cross-sectional view of step ten (b) of embodiment 1 of the present invention;

FIG. 13 is a cross-sectional view of step ten (c) of embodiment 1 of the present invention;

fig. 14 is a cross-sectional view after step twelve (a) of embodiment 1 of the present invention.

Wherein: 1 is a silicon substrate, 2 is an epitaxial layer, 3 is a field oxide layer, 4 is a gate oxide layer, 5 is a polysilicon layer, and 6 is SiO₂Layer 7 is a first photoresist, 8 is a first doping region, 9 is a second doping region, 10 is a second photoresist film, 11 is a third doping region, 12 is a cell trench, 13 is a cell large trench, 14 is an extension trench, 15 is a stop trench, 16 is an outer silicon dioxide layer, 17 is a polysilicon filling layer, 18 is a third photoresist film, 19 is an electrode metal layer, 20 is a first metal layer, and 21 is a second metal layer.

Detailed Description

The invention is further described below with reference to the accompanying drawings.