阅读说明：本技术 栅极电阻调整装置 (Grid resistance adjusting device ) 是由 高尾和人 林祐辅 于 2020-01-03 设计创作，主要内容包括：本公开的实施方式涉及栅极电阻调整装置。提供能够简易地调整栅极电阻的栅极电阻调整装置。栅极电阻调整装置具备：波形输入部,输入开关元件的导通时及截止时的漏极电压或者集电极电压、漏极电流或者集电极电流的波形；提取部,根据利用波形输入部输入的波形,提取开关元件的导通及截止所需的时间、开关元件的稳定时的漏极电流或者集电极电流；计算部,根据由提取部提取出的时间和稳定时的漏极电流或者集电极电流,计算开关元件的栅极电阻；以及设定部,对开关元件设定由计算部计算出的栅极电阻。(Embodiments of the present disclosure relate to a gate resistance adjusting apparatus. Provided is a gate resistance adjusting device capable of easily adjusting a gate resistance. The gate resistance adjusting device includes: a waveform input unit that inputs waveforms of a drain voltage or a collector voltage, a drain current, or a collector current of the switching element at the time of on and off; an extraction unit that extracts, based on the waveform input by the waveform input unit, a time required for turning on and off the switching element and a drain current or a collector current at the time of stabilization of the switching element; a calculation unit that calculates a gate resistance of the switching element based on the time extracted by the extraction unit and the drain current or the collector current at the time of stabilization; and a setting unit that sets the gate resistance calculated by the calculation unit for the switching element.)

1. A gate resistance adjusting device is provided with:

a waveform input unit that inputs a waveform of a drain voltage or a collector voltage, and a waveform of a drain current or a collector current of the switching element at least one of when the switching element is turned on and when the switching element is turned off;

an extraction unit that extracts, based on the waveform input by the waveform input unit, a time required for at least one of on and off of the switching element, and a drain current or a collector current of the switching element at a time of stabilization;

a calculation unit that calculates a gate resistance of the switching element based on the time extracted by the extraction unit and the drain current or the collector current at the time of the stabilization; and

and a setting unit that sets the gate resistance calculated by the calculation unit for the switching element.

2. A gate resistance adjusting device includes:

a noise simulation unit for simulating the noise level in the switching element and the peripheral circuit thereof;

a target waveform selection unit that selects a target waveform of at least one of a drain voltage or a collector voltage, a drain current, or a collector current of the switching element, based on a simulation result in the noise simulation unit;

an extraction unit that extracts, based on the waveform selected by the target waveform selection unit, a time required for at least one of on and off of the switching element, and a drain current or a collector current of the switching element at a time of stabilization;

a calculation unit that calculates a gate resistance of the switching element based on the time extracted by the extraction unit and the drain current or the collector current at the time of the stabilization; and

and a setting unit that sets the gate resistance calculated by the calculation unit for the switching element.

3. The gate resistance adjustment device according to claim 1 or 2,

the extraction unit extracts, based on the waveform, at least one of a DC bias voltage and a gate voltage of the switching element at a steady state, in addition to a time required for at least one of ON and OFF of the switching element, a drain current or a collector current of the switching element at a steady state,

the calculation unit calculates the gate resistance of the switching element based on at least one of the dc bias voltage and the gate voltage of the switching element at the time of stabilization, in addition to the time extracted by the extraction unit, the drain current or the collector current at the time of stabilization.

4. The gate resistance adjusting device according to any one of claims 1 to 3,

a storage unit for storing the gate resistance calculated by the calculation unit,

the setting unit reads the gate resistance stored in the storage unit and sets the switching element.

5. The gate resistance adjusting device according to any one of claims 1 to 4,

the calculation unit calculates the gate resistance of the switching element based on the information on the electrical characteristics of the switching element, in addition to the time extracted by the extraction unit and the drain current or the collector current at the time of the stabilization.

6. The gate resistance adjustment device of claim 5,

the information on the electrical characteristics includes a threshold voltage, a mutual conductance, a gate-source capacitance, and a gate-drain capacitance of the switching element.

7. The gate resistance adjusting device according to any one of claims 1 to 6,

the calculation unit calculates the gate resistance when the switching element is turned on and the gate resistance when the switching element is turned off, respectively, based on different model equations.

8. The gate resistance adjustment device of claim 7,

the calculation unit calculates the model equation based on an equivalent circuit of the switching element.

9. The gate resistance adjustment device of claim 7,

the calculation unit calculates the model equation that is fitted to the experimental waveforms when the switching element is turned on and off.

10. The gate resistance adjusting device according to any one of claims 7 to 9,

the calculation unit calculates the gate resistance from a 1 st model expression based on a temporal change in the drain current or the collector current during a 1 st period when the switching element is on, and calculates the gate resistance from a 2 nd model expression based on a temporal change in the drain voltage or the collector voltage during a 2 nd period following the 1 st period when the switching element is on,

the setting unit switches and sets the gate resistance of the switching element based on the gate resistance calculated by the calculation unit in the 1 st period and the 2 nd period when the switching element is on.

Technical Field

Embodiments of the present disclosure relate to a gate resistance adjusting apparatus.

Background

Since a power semiconductor element typified by a power MOSFET switches a large current, there is a risk that the power semiconductor element is broken when a surge voltage due to noise is superimposed on a gate voltage or a drain voltage of the power semiconductor element. In addition, the surge voltage also becomes a source of noise, and therefore, it is necessary to suppress the surge voltage as much as possible.

Therefore, a countermeasure is taken to suppress the surge voltage by adjusting the gate resistance connected to the gate of the power semiconductor element. As the gate resistance increases, the on time and off time of the power semiconductor element become longer, and the switching loss increases. On the other hand, as the gate resistance is reduced, the on time and the off time become shorter, but are susceptible to the influence of the surge voltage.

Thus, the surge voltage and the switching loss are in a trade-off relationship. Currently, the gate resistance is generally adjusted by trial and error (trial and error) while monitoring the voltage and current waveforms of the gate and drain of the power semiconductor element. The theoretical method for optimizing the gate resistance is not yet determined, and thus depends on the experience and intuition of the circuit designer. Therefore, it is a practical situation that it takes much time to adjust the gate resistance.

Disclosure of Invention

One aspect of the present disclosure provides a gate resistance adjusting device, a power supply device, a gate resistance designing device, and a gate resistance designing method, which can easily adjust a gate resistance.

According to the present embodiment, there is provided a gate resistance adjusting device including:

a waveform input unit that inputs a waveform of a drain voltage or a collector voltage, a drain current, or a collector current of at least one of an on state and an off state of the switching element;

an extraction unit that extracts, based on the waveform input by the waveform input unit, a time required for at least one of on and off of the switching element, and a drain current or a collector current of the switching element at a time of stabilization;

a calculation unit that calculates a gate resistance of the switching element based on the time extracted by the extraction unit and the drain current or the collector current at the time of the stabilization; and

and a setting unit that sets the gate resistance calculated by the calculation unit for the switching element.

Drawings

Fig. 1 is a block diagram showing a schematic configuration of a gate resistance adjusting apparatus according to embodiment 1.

Fig. 2 is a diagram showing an example of the waveform input unit.

Fig. 3 is an equivalent circuit diagram of a power converter including an equivalent circuit diagram of a power MOSFET.

Fig. 4 is a waveform diagram of the gate voltage, the drain current, and the drain voltage when the power MOSFET is on.

Fig. 5 is a waveform diagram of the gate voltage, the drain current, and the drain voltage when the power MOSFET is off.

Fig. 6 (a) is a cross-sectional view of the IGBT, and (b) is an equivalent circuit diagram of the IGBT.

Fig. 7 is a waveform diagram of the gate voltage, collector voltage, and collector current at the on and off times of the IGBT.

Fig. 8 is a block diagram showing a schematic configuration of a gate resistance adjusting apparatus according to embodiment 2.

Fig. 9 is a block diagram showing a schematic configuration of the gate resistance adjusting device according to embodiment 3.

(symbol description)

1: a gate resistance adjusting device; 2: a switching element; 3: a power supply device; 4: a waveform input section; 4 a: an input device; 5: an extraction unit; 6: a calculation section; 7: a setting unit; 8: a gate resistance design device; 9: a storage unit; 10: a detection unit; 20: an IGBT; 20 a: a depletion layer region; 20 b: an N-drift region; 21: a noise simulation unit; 22: target waveform selection unit

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following embodiments, the characteristic configurations and operations in the gate resistance adjusting device, the power supply device, and the gate resistance designing device will be mainly described, but the configurations and operations that will be omitted from the following description may exist in the gate resistance adjusting device, the power supply device, and the gate resistance designing device.

(embodiment 1)

Fig. 1 is a block diagram showing a schematic configuration of a gate resistance adjusting apparatus 1 according to embodiment 1. The gate resistance adjusting device 1 shown in fig. 1 has a function of adjusting the gate resistance of a power semiconductor element such as a power MOSFET or an IGBT. Hereinafter, the power semiconductor device will be collectively referred to as a switching device 2. The gate resistance adjusting device 1 is connected to the switching element 2 for use. The switching element 2 is provided inside the power supply device 3, for example. Therefore, the gate resistance adjusting device 1 may be incorporated in the power supply device 3. Alternatively, the gate resistance adjusting device 1 may be provided independently of the power supply device 3.

The gate resistance adjusting device 1 of fig. 1 includes a waveform input unit 4, an extraction unit 5, a calculation unit 6, and a setting unit 7. The waveform input unit 4, the extraction unit 5, and the calculation unit 6 also serve as the gate resistance designing device 8.

The waveform input unit 4 inputs a waveform of a drain voltage or a collector voltage, and a waveform of a drain current or a collector current of the switching element 2 at least one of when it is turned on and when it is turned off.

Fig. 2 is a diagram showing an example of the waveform input unit 4. A user such as a circuit designer inputs waveforms such as a drain voltage and a drain current through various input devices 4a such as a smartphone and a PC. The input waveform may be handwritten, or may be automatically converted into an approximate straight line or curved line waveform. Alternatively, several waveform candidates may be displayed, and the user may select an arbitrary waveform from among them. If the waveform of the user input is not reliable, the gate resistance R cannot be set properly_GTherefore, it is necessary to input a waveform by a person who has certain knowledge of waveforms of a drain voltage and a drain current which are desired at the time of on and off.

A tool for inputting the waveform of the drain voltage and the drain current by the user may be prepared in advance, and the waveform may be input by the user using the tool. For example, the waveform may be input by application software (hereinafter referred to as APP) of a smartphone or the like held by the user. In this case, when the APP is started, two-dimensional coordinates with time on the horizontal axis and voltage or current on the vertical axis may be displayed, and the user may input a waveform using a pen tool prepared in advance using the two-dimensional coordinates.

The extraction unit 5 in fig. 1 extracts, based on the waveform input by the waveform input unit 4, the time required for at least one of the on and off states of the switching element 2 and the drain current or the collector current at the time of stabilization of the switching element 2. The specific information extracted by the extraction section 5 is not limited to the above time and drain current (or collector current). For example, a dc bias voltage, a drain voltage or a collector voltage, a gate voltage at the time of stabilization, a gate current, or the like may be extracted. As described later, the information extracted by the extraction unit 5 depends on the parameters of the model formula used by the calculation unit 6.

The calculation unit 6 calculates the gate resistance R of the switching element 2 based on the time extracted by the extraction unit 5 and the drain current or the collector current at the time of stabilization_G. The calculation unit 6 may calculate the gate resistance R of the switching element 2 based on the information on the electrical characteristics of the switching element 2, in addition to the time extracted by the extraction unit 5 and the drain current or the collector current at the time of stabilization_G. Here, the information on the electrical characteristics may include the threshold voltage V of the switching element 2_thG, mutual conductance_mGate-source capacitance and gate-drain capacitance.

More specifically, the calculation unit 6 may calculate the gate resistance R at the time of turning on the switching element 2 based on different model expressions_GAnd gate resistance R at the time of turning off of the switching element 2_G. The model expression can also be calculated from the equivalent circuit of the switching element 2. Further, a model equation may be generated by fitting experimental waveforms at the on and off times of the switching element 2.

The calculation unit 6 may calculate the gate resistance R from the 1 st model expression based on the temporal change of the drain current or the collector current during the 1 st period when the switching element 2 is on_GIn a 2 nd period following the 1 st period when the semiconductor device is turned on, the gate resistance R is calculated according to a 2 nd model expression based on a time change of the drain voltage or the collector voltage_G. In addition, the calculation unit 6 may calculate the gate resistance R from the 3 rd model expression based on the temporal change of the drain voltage or the collector voltage in the 3 rd period when the switching element 2 is turned off_GIn a 4 th period following the 3 rd period at the time of turning-off, the gate resistance R is calculated according to a 4 th model expression based on a time change of the drain current or the collector current_G。

The setting unit 7 sets the gate resistance R calculated by the calculation unit 6 to the switching element 2_G. As described above, the calculation unit 6 divides the switching element 2 into the 1 st period and the 2 nd period when the switching element 2 is turned on, and calculates the gate resistances R different from each other_GIn the case of (1), the setting unit 7 sets the gate resistance R to be switched between the 1 st period and the 2 nd period_G. Similarly, the calculation unit 6 divides the switching element 2 into the 3 rd period and the 4 th period when the switching element is turned off, and calculates different gate resistances R_GIn the case of (1), the setting unit 7 sets the gate resistance R to be switched between the 3 rd period and the 4 th period_G。

The gate resistance adjusting device 1 of fig. 1 may include a storage unit 9. The storage unit 9 stores the gate resistance R calculated by the calculation unit 6_G. The gate resistance R stored in the storage unit 9 is read by the setting unit 7_GAnd set to the switching element 2.

Next, the operation of the gate resistance adjusting device 1 according to embodiment 1 will be described. Fig. 3 is an equivalent circuit diagram of a power converter including an equivalent circuit diagram of a power MOSFET. As shown in the figure, the power MOSFET is equivalently provided with a gate resistance R_GGate-drain capacitance C_GDAnd a gate-source capacitance C_GS. In addition, equivalent circuits other than those shown in fig. 3 may be considered as the equivalent circuit of the power MOSFET, and the components constituting the equivalent circuit may be changed.

Fig. 4 is a waveform diagram of the gate voltage, the drain current, and the drain voltage when the power MOSFET is on. Period t of fig. 4₁Is the period during which the gate voltage starts to rise. During this period, the gate exceeds the threshold voltage of the power MOSFET. Next, period t₂Is the period during which the drain current starts to increase. During a period t₁～t₂In the middle, the drain voltage remains in a high voltage state. Period t₃Is the period during which the drain voltage starts to decrease. During this period, the drain current peaks and then decreases. The conduction period of the power MOSFET isPeriod t₂And t₃. During the period t of passing₃When the drain current becomes a stable current I_LThe drain voltage becomes a stable voltage V_on. In addition, the gate voltage is slightly delayed to become a stable voltage V_GA。

The user inputs waveforms of the drain voltage, the drain current, and the like in fig. 4 via the waveform input unit 4. The gate resistance adjusting device 1 and the gate resistance designing device 8 of the present embodiment can automatically adjust the gate resistance R when the waveform shown in fig. 4 is inputted_G. The calculation unit 6 calculates the gate resistance R using a model equation_G. The method of generating the model equation will be described below.

The period t in fig. 4 is determined by the following equation (1)₁Gate voltage V of_GS. t is time, V_GAIs the gate voltage C in the steady state when the switching element is ON (ON)_GSIs the capacitance between the gate and the source, C_GDIs the gate-drain capacitance.

If (1) is defined as t₁When the formula is modified, the following formula (2) is obtained.

The period t in fig. 4 is obtained by the following expression (3)₂The drain current of (1). g_mIs the transconductance, V, of power MOSFETs_thIs the threshold voltage of the power MOSFET.

If (3) is provided, t is t₂When the formula is modified, the following formula (4) is obtained.

After modifying equation (4), the gate resistance R is expressed by equation (5) below_G。

The expression (5) is the period t during which the power MOSFET is on₂The model formula (4). From the right side of the expression (5), it can be seen that the gate resistance R of the expression (5) is calculated_GRequiring a gate-source capacitance C_GSGate-drain capacitance C_GDG, mutual conductance_mStable gate voltage V_GAThreshold voltage V of power MOSFET_thDrain current at steady state I_LPeriod t₂Length of (d).

The period t in fig. 4 is expressed by the following expression (6)₃Of the gate voltage of (1). I is_LIs the drain current at steady state.

The period t in fig. 4 is expressed by the following expression (7)₃Of the gate current.

During a period t₃In, V_GS＝V_GPTherefore, expression (7) can be modified to expression (8) below.

When the two sides of equation (8) are integrated with time t, equation (9) below is obtained.

If (9) is provided, t is t₃When the formula is modified, the following formula (10) is obtained.

When the expression (10) is modified, the gate resistance R can be expressed by the following expression (11)_G。

The expression (11) is the period t when the power MOSFET is on₃The model formula (4). From the right side of equation (11), the gate resistance R of equation (11) is calculated_GRequiring a DC bias voltage V to be applied when the power MOSFET is on_DCDrain voltage V at steady time when ON (ON)_onGate-drain capacitance C_GDStable gate voltage V_GAThreshold voltage V of power MOSFET_thG, mutual conductance_mDrain current at steady state I_LPeriod t₃Length of (d). The extraction unit 5 extracts at least a part of these parameters from the waveform input by the user using the waveform input unit 4. The extraction unit 5 may extract a partial parameter (g) based on the electrical characteristics of the power MOSFET to be used_m、V_thEtc.).

Fig. 5 is a waveform diagram of the gate voltage, the drain current, and the drain voltage when the power MOSFET is off. Period t of fig. 5₄Is the period during which the gate voltage starts to decrease. Period t₅Is the period during which the drain voltage starts to rise. During a period t₄～t₅In a steady state drain current I_L. Period t₆Is the period during which the drain current starts to decrease. During this period, the gate voltage is lower than the threshold voltage. In addition, the drain voltage is in the period t₆Peaks in and then begins to decrease. During a period t₆After the lapse of the time, the drain voltage becomes a voltage V of a steady state_DC。

The following equation (12) is used to determine the period t in FIG. 5₄Of the gate voltage of (1).

If (12) is used, t is t₄When the formula is modified, the following formula (13) is obtained.

The period t in fig. 5 is determined by the following equation (14)₅The gate voltage of (c).

The period t in fig. 5 is determined by the following equation (15)₅The gate current of (1).

Here, the following expression (16) holds.

Substituting formula (15) into formula (16)_GWhen the two sides of expression (16) are integrated at time t, expression (17) below is established.

If (17) is provided, t is t₅When the formula is modified, the following formula (18) is obtained.

When the formula (18) is modified, the gate resistance R can be expressed by the following formula (19)_G。

The expression (19) is the period t when the power MOSFET is turned off₅The model formula (4). From the right side of the expression (19), it can be seen that the gate resistance R of the expression (19) is calculated_GThe gate-drain capacitance C is required_GDDC bias voltage V_DCStabilized drain voltage V_onThreshold voltage V of power MOSFET_thG, mutual conductance_mDrain current at steady state I_LPeriod t₅Length of (d).

The period t in fig. 5 is obtained by the following expression (20)₆The gate voltage of (c).

The period t in fig. 5 is determined by the following equation (21)₆The drain current of (1).

If (21) is given, t is t₆When the formula is modified, the following formula (22) is obtained.

When the formula (22) is modified, the gate resistance R can be expressed by the following formula (23)_G。

The expression (23) is the period t when the power MOSFET is turned off₆The model formula (4). From the right side of the expression (23), it can be seen that the gate resistance R of the expression (23) is calculated_GRequiring a gate-source capacitance C_GSGate-drain capacitance C_GDG, mutual conductance_mThreshold voltage V of power MOSFET_thDrain current at steady state I_LPeriod t₆Length of (d).

Thus, in the above example, when the power MOSFET is turned on, the period t is set to be longer₂And t₃Middle and gate resistance R_GThe model formulas of the components are different; at the time of cut-off, during a period t₅And t₆Middle and gate resistance R_GThe model of (2) is different. Therefore, when conducting, the setting unit 7 is in the period t₂And t₃Middle switching grid resistance R_G(ii) a When turned off, the setting unit 7 sets the period t₅And t₆Middle switching grid resistance R_G。

The gate resistance adjusting device 1 of the present embodiment can also be applied to a case where the switching element 2 is the IGBT 20. Fig. 6 (a) is a cross-sectional view of the IGBT20, and fig. 6 (b) is an equivalent circuit diagram of the IGBT 20. As shown in fig. 6 (a), the IGBT20 includes a gate, an emitter, and a collector, and a depletion region (depletion region)20a and an N-drift region 20b are provided between the gate and the collector. As shown in fig. 6 (b), the IGBT20 equivalently includes: capacitance C between grid and emitter_geGate-collector capacitance C_gcGate-emitter capacitance C_ceAnd a diffusion capacitor C_DChannel resistance R_chAnd a drift resistance R after conductivity modulation_MD。

Fig. 7 is a waveform diagram of the gate voltage, collector voltage, and collector current at the time of on and off of the IGBT 20. Period t of fig. 7₁～t₃Is the on period, the period t₄～t₆Is the cutoff period.

During a period t₂In (5), the gate resistance R at the time of conduction is represented by the following expression (24)_GDuring a period t₃In (5), the gate resistance R at the time of conduction is expressed by the formula (25)_G。

C of formula (25) is represented by formula (26)_GC. It is composed ofIn (A) is the dielectric constant of the semiconductor, A_GDIs a cross-sectional area between the gate and drain electrodes, q is a basic charge, N_BIs the carrier density in the drift layer.

In addition, during the period t₄In (5), the gate resistance R at the time of off is represented by the following formula (27)_G。

The extraction unit 5 extracts the gate resistance R from the waveform inputted by the user through the waveform input unit 4_GThe values of the parameters on the right side of the equation (1). The calculation unit 6 substitutes the values of the parameters extracted by the extraction unit 5 into the gate resistance R_GTo calculate the gate resistance R_G. The gate resistance R calculated by the calculating part 6 is calculated as required_GStored in the storage unit 9. When storing the information in the storage section 9, it is preferable to store the gate resistance R in correspondence with the waveform information inputted by the user_GThe value of (c). Accordingly, when a similar waveform is input by the user later, the corresponding gate resistance R can be read from the storage unit 9 without recalculating by the calculation unit 6_GAnd set.

In the above description, the generation of the gate resistance R for calculation from the equivalent circuit of the switching element 2 is described_GAnd substituting the generated model expression into the parameter value of the waveform input by the user to calculate the gate resistance R_GExamples of (3).

For calculating the gate resistance R_GThe model equation (2) may be generated from the equivalent circuit of the switching element 2 as described above, or a method of generating a model equation fitting the shape of the waveform input by the user may be considered. For example, a model equation to be fitted to a waveform input by a user can be expressed by, for example, the following equations (28) to (31).

(28) The expression is the period t when the power MOSFET is on₂The model equation (1) and the equation (29) are the off-time period t₃The model equation (1) and equation (30) are the off-time period t₅The model equation (1) is the period t at the time of cutoff₆The right side C, D, E, F, K, L of each formula are fitting parameters, which are set so as to fit the waveform input by the user.

Gate resistance R using gate resistance adjusting device 1 of the present embodiment_GThe adjustment of (b) can be performed either after the switching element 2 is mounted to the power supply device 3 or at a design stage before the switching element 2 is mounted to the power supply device 3. Adjusting the gate resistance R after mounting the switching element 2 to the power supply device 3_GIn this case, for example, all the components in the gate resistance adjusting device 1 may be mounted in the housing of the power supply device 3, or some of the components in the gate resistance adjusting device 1, for example, the waveform input unit 4 may be provided at a place independent from the housing of the power supply device 3. Specifically, the waveform input unit 4 in the gate resistance adjustment device 1 may be an APP of a smartphone held by the user. In this case, the power supply apparatus 3 needs to be provided with a wireless communication function of starting the APP and transmitting a waveform input by the user to the gate resistance adjustment apparatus 1 in the power supply apparatus 3.

On the other hand, the gate resistance R is performed at the design stage before the switching element 2 is mounted on the power supply device 3_GIn the case of (3), the user can use the methodThe gate resistance adjusting device 1 of the embodiment is used as the gate resistance designing device 8. In this case, the necessary components of the gate resistance designing device 8 are the waveform input unit 4, the extraction unit 5, and the calculation unit 6. The gate resistance R calculated by the calculation unit 6 is calculated as necessary_GThe setting may be automatically or manually set at a desired timing by storing the data in the storage unit 9.

Thus, in embodiment 1, the gate resistance R of the switching element 2 is adjusted by the user_GSince the waveform of the drain voltage or the collector voltage, the drain current or the collector current is input, the extraction unit 5 extracts the adjustment gate resistance R from the input waveform_GThe values of the required parameters are substituted into the model expression, and the gate resistance R is calculated by the calculating part 6_G. Thus, the complicated gate resistance R can be easily performed_GAnd (4) adjusting. In particular, the user can set the optimum gate resistance R by inputting only the waveform of the drain voltage or the like_GTherefore, the user can adjust the gate resistance R without trial and error three times_GLabor and time of the user can be saved.

(embodiment 2)

In embodiment 2, the waveform inputted by the user is matched to set the gate resistance R_G。

Fig. 8 is a block diagram showing a schematic configuration of the gate resistance adjusting apparatus 1 according to embodiment 2. The gate resistance adjusting device 1 of fig. 8 includes: a waveform input unit 4, a storage unit 9, a search unit 10, and a setting unit 7. The waveform input unit 4, the storage unit 9, and the search unit 10 also serve as the gate resistance designing device 8.

The waveform input unit 4 is the same as the waveform input unit 4 of fig. 1. The storage unit 9 stores a plurality of waveforms and gate resistances R corresponding to the waveforms_GAnd are stored correspondingly. The storage unit 9 stores waveforms of the drain voltage or the collector voltage, the drain current, or the collector current of at least one of the on-time and the off-time of the switching element 2, which are input by the waveform input unit 4. The waveform input unit 4 may be used for inputting a waveform, or may be used for inputting a waveform by a simulation apparatus or a user, not shownThe waveform obtained as a result of the experiment and the corresponding gate resistance R_GAnd are stored correspondingly.

When the user inputs waveforms of, for example, a drain voltage and a drain current by using the waveform input unit 4, the search unit 10 searches the storage unit 9 for a waveform similar to the inputted waveform. When an approximate waveform is searched, the setting unit 7 reads the gate resistance R corresponding to the waveform from the storage unit 9_GAnd setting is performed.

As a method for the search unit 10 to search for the waveform, various methods are conceivable. For example, image information indicating the shape of the waveform may be stored in the storage unit 9 in advance, the matching process between the shape of the waveform input by the user and the image information of the waveform stored in the storage unit 9 may be performed, and the gate resistance R corresponding to the most matched waveform may be read_G。

Alternatively, the following method may be employed: the storage unit 9 stores in advance a parameter value for characterizing the waveform, for example, calculates the gate resistance R_GThe parameter value of the model (2) is obtained by extracting the parameter value from the waveform inputted by the user, comparing the parameter values with each other, and reading the gate resistance R corresponding to the parameter value having the highest degree of coincidence_G。

Thus, in embodiment 2, the waveform and the gate resistance R set or calculated in the past are used_GThe most suitable grid resistance R for the waveform newly input by the user is searched_GAnd set so that it is not necessary to calculate the gate resistance R every time the user inputs a waveform_GEasy to perform gate resistance R_GAnd (4) adjusting.

(embodiment 3)

In embodiment 3, the gate resistance R is performed based on the result of the noise simulation_GAutomatic adjustment of (2).

Fig. 9 is a block diagram showing a schematic configuration of the gate resistance adjusting apparatus 1 according to embodiment 3. The gate resistance adjusting device 1 of fig. 9 includes: a noise simulation unit 21, a target waveform selection unit 22, an extraction unit 5, a calculation unit 6, and a setting unit 7.

Noise simulation unit 21 for switching element 2 and its peripheral circuitThe noise simulation is performed by simulating the magnitude of noise, mainly the amplitude of surge voltage, surge current, and current vibration, in the power supply device 3 provided with the switching element 2. In general, the gate resistance R is increased to suppress the amplitude of surge voltage, surge current, and current vibration_GThat is, but the gate resistance R is increased more_GThe longer the on-time and off-time of the switching element 2 become, the larger the switching loss will increase. Thus, in order to adjust the gate resistance R_GNoise such as surge voltage becomes an important factor.

The target waveform selecting unit 22 selects a target waveform of at least one of the drain voltage or the collector voltage, the drain current, or the collector current, based on the simulation result in the noise simulation unit 21. Here, the waveform is selected so that the switching loss can be suppressed within an allowable range while avoiding the breakdown of the switching element 2. The correspondence relationship between the noise and the waveform set in the past may be tabulated and held, and when a waveform is selected, the waveform may be selected by referring to the table.

The processing of the extracting unit 5, the calculating unit 6, and the setting unit 7 is the same as that of embodiment 1. For example, the extracting unit 5 extracts the adjustment gate resistance R based on the waveform selected by the target waveform selecting unit 22_GThe required information includes, for example, a time required for at least one of on and off of the switching element 2, a drain current or a collector current when the switching element 2 is stable, and the like. The calculation unit 6 calculates the gate resistance R based on the model equation_G。

As described above, in embodiment 3, the waveform of the drain voltage, the drain current, and the like is automatically selected based on the result of the noise simulation, and therefore the waveform input unit 4 in embodiment 1 and embodiment 2 is not required. Therefore, the gate resistance R can be adjusted by completely automated processing without inputting a waveform by the user himself_G。

The above embodiments can be summarized as the following embodiments.

Technical solution 1

A gate resistance adjusting device is provided with:

a waveform input unit that inputs a waveform of a drain voltage or a collector voltage, a drain current, or a collector current of at least one of an on state and an off state of the switching element;

an extraction unit that extracts, based on the waveform input by the waveform input unit, a time required for at least one of on and off of the switching element, and a drain current or a collector current of the switching element at a time of stabilization;

a calculation unit that calculates a gate resistance of the switching element based on the time extracted by the extraction unit and the drain current or the collector current at the time of the stabilization; and

and a setting unit that sets the gate resistance calculated by the calculation unit for the switching element.

Technical solution 2

A gate resistance adjusting device includes:

a noise simulation unit for simulating the noise level in the switching element and the peripheral circuit thereof;

a target waveform selection unit that selects a target waveform of at least one of a drain voltage or a collector voltage, a drain current, or a collector current of the switching element, based on a simulation result in the noise simulation unit;

an extraction unit that extracts, based on the waveform selected by the target waveform selection unit, a time required for at least one of on and off of the switching element, and a drain current or a collector current of the switching element at a time of stabilization;

a calculation unit that calculates a gate resistance of the switching element based on the time extracted by the extraction unit and the drain current or the collector current at the time of the stabilization; and

and a setting unit that sets the gate resistance calculated by the calculation unit for the switching element.

Technical solution 3

According to the gate resistance adjusting device described in claim 1 or 2,

the extraction unit extracts, based on the waveform, at least one of a direct-current bias voltage and a gate voltage of the switching element at a steady state, in addition to a time required for at least one of on and off of the switching element, a drain current or a collector current of the switching element at a steady state,

the calculation unit calculates the gate resistance of the switching element based on at least one of the dc bias voltage and the gate voltage of the switching element at the time of stabilization, in addition to the time extracted by the extraction unit, the drain current or the collector current at the time of stabilization.

Technical solution 4

According to the gate resistance adjusting device of any one of claims 1 to 3,

a storage unit for storing the gate resistance calculated by the calculation unit,

the setting unit reads the gate resistance stored in the storage unit and sets the switching element.

Technical solution 5

According to the gate resistance adjusting device of any one of claims 1 to 4,

the calculation unit calculates the gate resistance of the switching element based on the information on the electrical characteristics of the switching element, in addition to the time extracted by the extraction unit and the drain current or the collector current at the time of the stabilization.

Technical scheme 6

According to the gate resistance adjusting device of claim 5,

the information on the electrical characteristic includes: a threshold voltage, a mutual conductance, a gate-source capacitance, and a gate-drain capacitance of the switching element.

Technical scheme 7

According to the gate resistance adjusting device of any one of claims 1 to 6,

the calculation unit calculates the gate resistance when the switching element is turned on and the gate resistance when the switching element is turned off, respectively, based on different model equations.

Technical solution 8

According to the gate resistance adjusting device described in claim 7,

the calculation unit calculates the model equation from an equivalent circuit of the switching element.

Technical solution 9

According to the gate resistance adjusting device described in claim 7,

the calculation unit calculates the model equation that is fitted to the experimental waveforms when the switching element is turned on and off.

Technical means 10

According to the gate resistance adjusting device of any one of claims 7 to 9,

the calculation unit calculates the gate resistance from a 1 st model expression based on a temporal change in the drain current or the collector current during a 1 st period when the switching element is on, and calculates the gate resistance from a 2 nd model expression based on a temporal change in the drain voltage or the collector voltage during a 2 nd period following the 1 st period when the switching element is on,

the setting unit switches and sets the gate resistance of the switching element based on the gate resistance calculated by the calculation unit in the 1 st period and the 2 nd period when the switching element is on.

Technical means 11

According to the gate resistance adjusting device of any one of claims 7 to 9,

the calculation unit calculates the gate resistance based on a 3 rd model expression based on a temporal change in the drain voltage or the collector voltage during a 3 rd period when the switching element is turned off, and calculates the gate resistance based on a 4 th model expression based on a temporal change in the drain voltage or the collector voltage during a 4 th period following the 3 rd period when the switching element is turned off,

the setting unit switches and sets the gate resistance of the switching element based on the gate resistance calculated by the calculation unit in the 3 rd period and the 4 th period during the off state.

Technical means 12

A gate resistance adjusting device is provided with:

a waveform input unit that inputs a waveform of a drain voltage or a collector voltage, a drain current, or a collector current of at least one of an on state and an off state of the switching element;

a storage unit that stores a plurality of waveforms in association with gate resistances corresponding to the waveforms;

a search unit that searches the storage unit based on the waveform input by the waveform input unit and outputs the corresponding gate resistance; and

and a setting unit that sets the gate resistance output from the search unit for the switching element.

Technical means 13

A power supply device is provided with:

a switching element; and

a gate resistance adjusting device for controlling a gate voltage after setting a gate resistance of the switching element,

the gate resistance adjusting device includes:

a waveform input unit that inputs a waveform of a drain voltage or a collector voltage, a drain current, or a collector current of at least one of an on state and an off state of the switching element;

an extraction unit that extracts, based on the waveform input by the waveform input unit, a time required for at least one of on and off of the switching element, and a drain current or a collector current of the switching element at a time of stabilization;

a calculation unit that calculates a gate resistance of the switching element based on the time extracted by the extraction unit and the drain current or the collector current at the time of the stabilization; and

and a setting unit that sets the gate resistance calculated by the calculation unit for the switching element.

Technical means 14

A gate resistance designing device is provided with:

a waveform input unit that inputs a waveform of a drain voltage or a collector voltage, a drain current, or a collector current of at least one of an on state and an off state of the switching element;

an extraction unit that extracts, based on the waveform input by the waveform input unit, a time required for at least one of on and off of the switching element, and a drain current or a collector current of the switching element at a time of stabilization; and

and a calculation unit that calculates a gate resistance of the switching element based on the time extracted by the extraction unit and the drain current or the collector current at the time of the stabilization.

Technical means 15

A gate resistance design method includes:

inputting a waveform of a drain voltage or a collector voltage, a drain current, or a collector current of at least one of an on state and an off state of the switching element;

extracting a time required for at least one of on and off of the switching element, and a drain current or a collector current at a time of stabilization of the switching element, based on the input waveform; and

and calculating a gate resistance of the switching element based on the extracted time and the drain current or collector current at the stable time.

Although several embodiments of the present disclosure have been described, these embodiments are merely illustrative and are not intended to limit the scope of the invention. These new embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.