阅读说明：本技术 控制开关的控制器和方法及包括计算机可读介质的装置 (Controller and method for controlling switch and apparatus including computer readable medium ) 是由 林淑芳 于 2020-01-03 设计创作，主要内容包括：公开了一种用于控制功率因数校正(PFC)电路的开关的控制器和方法以及包括计算机可读介质的装置。该控制器包括第一节点,该第一节点被配置成接收指示功率因数校正电路的输入电压的第一信号。该控制器还包括处理电路,该处理电路被配置成基于第一信号来确定通过PFC电路的一个或更多个电容器的电流的值。该处理电路还被配置成基于电流的值来确定开关的接通时间并且基于接通时间来对开关进行切换。(A controller and method for controlling switching of a Power Factor Correction (PFC) circuit and an apparatus including a computer readable medium are disclosed. The controller includes a first node configured to receive a first signal indicative of an input voltage of a power factor correction circuit. The controller also includes a processing circuit configured to determine a value of a current through one or more capacitors of the PFC circuit based on the first signal. The processing circuit is also configured to determine an on-time of the switch based on the value of the current and switch the switch based on the on-time.)

1. A controller for controlling the switching of a power factor correction, PFC, circuit, the controller comprising:

a first node configured to receive a first signal indicative of an input voltage of the PFC circuit;

a processing circuit configured to:

determining a value of a current through one or more capacitors of the PFC circuit based on the first signal at least in part by taking a derivative of the first signal;

determining an on-time of the switch based on the value of the current; and

switching the switch based on the on-time.

2. The controller according to claim 1, wherein the controller is a microprocessor,

wherein the on-time of the switch is a desired on-time of the switch,

wherein the processing circuit is further configured to determine an actual on-time based on the desired on-time using an inner control loop, an

Wherein the processing circuit is configured to switch the switch based on the actual on-time.

3. The controller of claim 1, further comprising a second node configured to receive a second signal indicative of a voltage drop across a load current path of the switch,

wherein the processing circuit is further configured to detect one or more local minimum portions of the second signal, an

Wherein the processing circuit is configured to determine the on-time at least in part by selecting a local minimum portion of the one or more detected local minimum portions based on the first signal.

4. The controller of claim 3, wherein the processing circuit is configured to switch the switch at least in part by turning on the switch during the selected local minimum portion.

5. The controller of claim 3, wherein the processing circuit is configured to detect the one or more local minimum portions at least in part by detecting one or more zero crossings of the second signal.

6. The controller of claim 1, wherein the processing circuit is configured to extract the waveform of the current through the one or more capacitors based on an input voltage of the PFC circuit at least in part by taking a derivative of the first signal.

7. The controller of claim 1, wherein the processing circuit is configured to control the switch to closely match an input current of the PFC circuit to the input voltage.

8. The controller of claim 1, wherein the processing circuit is configured to determine the on-time based on the value of the current and further based on an output value of a proportional-integral control loop or an output value of a proportional-integral-derivative control loop.

9. The controller of claim 1, wherein the processing circuit is configured to determine the on-time based on a value of the current and further based on an inductance of an inductor of the PFC circuit.

10. The controller of claim 1, wherein the first node is configured to receive the first signal from an output node of a rectifier circuit coupled to the PFC circuit.

11. The controller according to claim 1, wherein the controller is a microprocessor,

wherein the processing circuit is configured to determine an on-time of the switch within a control loop, and

wherein the processing circuit is further configured to compare, within the control loop, the output voltage of the PFC circuit to a target value within the control loop.

12. The controller of claim 11, wherein the processing circuit is further configured to:

determining, within the control loop, an error value based on comparing the output voltage of the PFC circuit to the target value; and is

Within the control loop, a control voltage is determined based on integrating the error value.

13. A method for controlling switching of a power factor correction, PFC, circuit, the method comprising:

receiving a first signal indicative of an input voltage of the PFC circuit;

determining a value of a current through one or more capacitors of the PFC circuit based on the first signal at least in part by taking a derivative of the first signal;

determining an on-time of the switch based on the value of the current; and

switching the switch based on the on-time.

14. The method of claim 13, wherein the first and second light sources are selected from the group consisting of,

wherein the on-time of the switch is a desired on-time of the switch,

wherein the method further comprises using an inner control loop to determine an actual on-time based on the desired on-time, an

Wherein the switch is switched based on the actual on-time.

15. The method of claim 13, further comprising:

receiving a second signal indicative of a voltage drop across a load current path of the switch; and

detecting one or more local minimum portions of the second signal,

wherein determining the on-time comprises selecting a local minimum portion of the one or more detected local minimum portions based on the first signal.

16. The method of claim 15, wherein switching the switch comprises turning on the switch during the selected local minimum portion.

17. The method of claim 13, further comprising: extracting a waveform of the current through the one or more capacitors based on an input voltage of the PFC circuit at least in part by taking a derivative of the first signal.

18. An apparatus comprising a computer-readable medium having stored thereon executable instructions configured to be executable by a processing circuit to cause the processing circuit to:

receiving a first signal indicative of an input voltage of a power factor correction, PFC, circuit;

determining a value of a current through one or more capacitors of the PFC circuit based on the first signal at least in part by taking a derivative of the first signal;

determining an on-time of a switch of the PFC circuit based on the value of the current; and

switching the switch based on the on-time.

19. The apparatus of claim 18, wherein the instructions further cause the processing circuit to:

receiving a second signal indicative of a voltage drop across a load current path of the switch; and

detecting one or more local minima of the second signal,

wherein the instructions to determine the on-time comprise instructions to select a local minimum portion of the one or more detected local minimum portions based on the first signal.

20. The apparatus of claim 18, wherein the instructions further cause the processing circuit to extract the waveform of the current through the one or more capacitors based on an input voltage of the PFC circuit at least in part by taking a derivative of the first signal.

Technical Field

The present disclosure relates to power converters, and more particularly, to techniques and circuits associated with switch-mode power converters.

Background

Devices that receive power from a power source, such as a power grid, battery, or generator, may include a Power Factor Correction (PFC) circuit. A device capable of power factor correction can increase the efficiency of a power supply by making the load that the power supply "sees" appear to be more resistive than capacitive or inductive, thereby reducing the reactive power. The power factor of the load is based on the instantaneous voltage and the instantaneous current. For a power factor of one, the phase lag between the ac input voltage and the corresponding ac input current is zero.

The PFC circuit may be coupled to an input of another power converter (e.g., a flyback converter) and an output of the rectifier. The PFC circuit together with other power converters may form a Switched Mode Power Supply (SMPS). The PFC circuit may include a flyback converter topology or a boost converter topology. To increase the power factor, the controller may control the switching operation of the PFC circuit such that the input current more closely follows the input voltage to reduce the phase lag between the input voltage and the input current. For PFC circuits, the controller may use quasi-resonant switching where the switching frequency is not defined by the clock. The switching frequency range may vary with input voltage and electrical load.

Disclosure of Invention

The present disclosure describes a control technique for a Power Factor Correction (PFC) circuit that includes a switch and one or more capacitors. The control technique may include determining a current through one or more capacitors. The control technique may also include determining an on-time for the switch and switching the switch based on the determined on-time.

In some examples, a controller controls a switch of a power factor correction circuit, wherein the controller comprises: a first node configured to receive a first signal indicative of an input voltage of a power factor correction circuit. The controller further comprises: a processing circuit configured to determine a value of a current through one or more capacitors of the PFC circuit based on the first signal. The processing circuit is also configured to determine an on-time of the switch based on the value of the current and switch the switch based on the on-time.

In some examples, a method includes controlling a switch of a Power Factor Correction (PFC) circuit and receiving a first signal indicative of an input voltage of the PFC circuit. The method also includes determining a value of a current through one or more capacitors of the PFC circuit based on the first signal. The method also includes determining an on-time of the switch based on the value of the current and switching the switch based on the on-time.

In some examples, an apparatus includes a computer-readable medium having stored thereon executable instructions configured to be executable by a processing circuit to cause the processing circuit to receive a first signal indicative of an input voltage of a Power Factor Correction (PFC) circuit. The instructions also cause the processing circuit to determine a value of a current through one or more capacitors of the PFC circuit based on the first signal. The instructions also cause the processing circuit to determine an on-time of a switch of the PFC circuit based on the value of the current and switch the switch based on the on-time.

The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.

Drawings

Fig. 1 is a conceptual block diagram of a system including a Power Factor Correction (PFC) circuit in accordance with one or more aspects of the present disclosure;

FIGS. 2A and 2B are exemplary graphs of input voltage and current through one or more capacitors;

fig. 3 is a circuit diagram of a system including a rectifier circuit and a filter circuit according to one or more aspects of the present disclosure;

FIG. 4 is a phasor diagram of inductor current, capacitive current and input current;

fig. 5 is a conceptual block diagram of a control loop for determining the on-time of a switch in a PFC circuit according to one or more aspects of the present disclosure;

fig. 6 and 7 are timing diagrams illustrating operation of a PFC circuit according to one or more aspects of the present disclosure;

fig. 8 is a flow diagram illustrating an example process for controlling a PFC circuit in accordance with one or more aspects of the present disclosure.

Detailed Description

This disclosure describes techniques for determining an on-time for a switch based on a current through one or more capacitors of a PFC circuit. One or more capacitors may be disposed as electromagnetic interference (EMI) filters at the input of the PFC circuit. By determining the on-time of the switch based on the current using the functions and control loops described herein, the controller may achieve better shaping of the input current relative to the input voltage.

The controller may use a digital differentiator to extract the waveform of the input capacitive current from the input voltage signal sampled by the controller. With the current shaping techniques described herein, the controller can more closely match the input current to the input voltage, thereby improving power factor, particularly at light loads.

The techniques of this disclosure may be used to mitigate problems arising in critical conduction mode (CrCM), also referred to as boundary mode. These problems may include higher switching losses caused by higher switching frequencies when operating under CrCM under light loads. The controller may use the control scheme described herein to limit the switching frequency to a range that can be a frequency law. The controller may select a higher number of quasi-resonances (QR) to increase the switching period, thereby reducing the switching frequency. By operating in the QR mode with a QR number higher than one (e.g., QR2, QR3, etc.), the controller may reduce switching losses and increase power factor, particularly for light load conditions.

Fig. 1 is a conceptual block diagram of a system 100 including a Power Factor Correction (PFC) circuit 140 according to one or more aspects of the present disclosure. The system 100 includes a filter circuit 110, a rectifier circuit 120, a filter circuit 130, a PFC circuit 140, an output stage 150, a load 160, and a controller 170. The system 100 may be configured to receive power from the power source 102 at an input node coupled to the filter circuit 110. The power supply 102 may include a power grid (e.g., mains power) that supplies power to the system 100.

The filter circuits 110 and 130 may be configured to filter out high frequency noise from the power received by the system 100. The filter circuits 110 and 130 may include one or more capacitors and one or more inductors. The filter circuits 110 and 130 may operate to reduce noise generated by the rectifier circuit 120 and the PFC circuit 140 from flowing back to the power supply coupled to the filter circuits. The filter circuits 110 and 130 may be referred to herein as part of the PFC circuit 140 such that one or more capacitors in the filter circuits 110 and 130 are referred to as part of the PFC circuit 140.

The rectifier circuit 120 may be configured to convert an Alternating Current (AC) signal to a half-wave signal. For example, the system 100 may receive an AC signal having a sinusoidal waveform and output a half-wave sinusoidal AC signal. The rectifier circuit 120 may include four rectifier diodes. The rectified signal generated by the rectifier circuit 120 may include a signal labeled v_gIs marked v_FFOf the DC component of (a). The controller 170 may receive a signal indicative of the instantaneous component of the rectified signal and extract a DC component from the received signal. For example, the controller 170 may pass the received signal through a two-stage low pass filter to extract the DC component of the rectified signal. Additionally or alternatively, the controller 170 may perform a fourier transform to extract a DC component from the received signal.

The PFC circuit 140 is configured to receive a signal from the filter circuit 130. The PFC circuit 140 may operate to more closely match the current of the received signal to the voltage of the received signal. PFC circuit 140 may be designed to have a power factor as close to unity as possible, where the power factor is calculated as the active power divided by the total power drawn by rectifier circuit 120. For light loads, an example power factor target may be 85%, 90%, or 95%, where light loads may be defined as twenty percent of the power of the rated load. If the rated load is 240 watts, then twenty percent of the light load will be 48 watts. As described herein, the controller 170 may control the switch 142 to closely match the input current to the input voltage, where "closely match" means that the PFC circuit 140 has a power factor of at least 85%, at least 90%, or at least 95% at a load of 20% of the rated load.

PFC circuit 140 includes a switch 142 controlled by a controller 170. The PFC circuit 140 may also include an inductor, a diode, and an output capacitor. Additional example details of the operation of PFC circuits may be found in commonly assigned U.S. patent No. 9,455,623 entitled "Power Factor Correction Circuit and Method" issued on 27/9/2016 and commonly assigned U.S. patent No. 9,502,981 entitled "Enhanced Power Factor Correction" issued on 22/11/2016, the entire contents of both of which are incorporated herein by reference. In some examples, the PFC circuit 140 may have a similar arrangement to the PFC circuit shown in the above-referenced U.S. patent.

The switch 142 may be a power switch such as, but not limited to, any type of Field Effect Transistor (FET) such as a metal oxide semiconductor FET (mosfet), a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a High Electron Mobility Transistor (HEMT), a gallium nitride (GaN) based transistor, or another element that uses voltage for its control. The switch 142 may comprise various material compounds such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or any other combination of one or more semiconductor materials. The switch 142 may include an n-type transistor or a p-type transistor and the switch 142 may be a power transistor. In some examples, the switch 142 may also include other analog devices such as diodes and/or thyristors. The switch 142 may further include a freewheel diode connected in parallel with the transistor for preventing reverse breakdown of the transistor.

The switch 142 may include three terminals: two load terminals and one control terminal. For a MOSFET switch, the switch 142 may include a drain terminal, a source terminal, and a gate terminal. For a BJT switch, the control terminal of switch 142 may be the base terminal. Based on the voltage at the control terminal, current may flow through a load current path extending between the load terminals of the switch 142. Thus, current may flow through the switch 142 based on the signal passed to the switch 142 by the gate driver 190.

The output stage 150 may include a DC/DC converter such as a flyback converter, a resonant mode converter, a forward converter, a half-bridge converter, and/or another type of converter that receives the output of the PFC circuit 140. The output stage 150 may be configured to generate an output signal for the load 160. In some examples, the output stage 150 converts the high output voltage (e.g., 385 volts or 400 volts) received from the PFC circuit 140 to a lower voltage level such as twelve volts or five volts.

The load 160 may include a resistive load, a capacitive load, and/or an inductive load. Examples of inductive loads may include actuators, motors and pumps used in one or more of heating, air conditioning, water supply, fans or other systems including inductive loads. In some examples, the load 160 includes a capacitive load that may receive power from the output stage 150 through, for example, an inverter circuit. Examples of capacitive loads may include lighting elements such as xenon arc lamps. In further examples, the load 160 may be a combination of resistive, inductive, and capacitive loads.

The controller 170 is configured to control the operation of the switch 142. In some examples, the controller 170 may be a combination controller configured to also control the operation of one or more switches of the output stage 150. Controller 170 may include nodes 172, 174, 176, and 178 for receiving signals from system 100. The controller 170 may also include processing circuitry 180, a gate driver 190, and a memory 192. In higher power applications, the controller 170 may be configured to pass control signals to a gate driver external to the controller 170.

Node 172 of controller 170 may be configured to receive a first signal indicative of the input voltage of PFC circuit 140. The rectifier circuit 120 may generate an input voltage for the PFC circuit 140. Nodes 174, 176, and 178 of controller 170 may receive the following signals: a signal indicative of a current through the switch 142, a signal indicative of a voltage drop across a load current path of the switch 142, and/or a signal indicative of a voltage level of an output signal generated by the PFC circuit 140. The processing circuit 180 may be configured to detect one or more local minimum portions of the received signal. The processing circuit 180 may detect the local minimum portion by detecting a zero crossing of the received signal or by detecting that the received signal exceeds another threshold level. The processing circuit 180 may be configured to determine the on-time at least in part by selecting one of the detected local minimum portions based on the received signal. Processing circuitry 180 may turn on switch 142 during the selected portion of the local minimum.

The processing circuit 180 is configured to determine a value of a current through one or more capacitors of the PFC circuit 140 based on the first signal received by the node 172. One or more capacitors of PFC circuit 140 may be part of filter circuit 110 and/or filter circuit 130, but referred to as part of PFC circuit 140. Processing circuitry 180 may use equation (1) based on total capacitance C of one or more capacitors_totAnd the input voltage v of the PFC circuit 140_g(t) to determine the current i_ctot(t) of (d). The input current to the filter circuit 110 may be equal to the inductor current plus the capacitive current. Capacitive current i_ctot(t) may be equal to the sum of all currents through the input EMI capacitors. As shown in equation (1), the derivation of the input voltage will give a value proportional to the capacitive current.

The processing circuit 180 may use equation (2) to determine the DC equivalent v of the input voltage based on the inductance L of the inductor in the PFC circuit 140_FFOutput v of the voltage controller_controlAnd a proportionality constant K for balancing a gain difference between the reference inductor current and the sampled average inductor current₁To determine the desired on-time of the switch 142. Thus, processing circuit 180 may be based on current (C)_totMultiplied by v_gDerivative of) and the first signal (v)_g) To determine the desired on-time.

The processing circuit 180 may use equation (3) to base the desired on-time, off-time t_offAnd a switching period t_swTo determine the actual on-time t of the switch 142_on. For QR mode greater than QR1, on-time and offThe sum of the times may be different from the switching period. Processing circuitry 180 may determine the actual on-time based on the desired on-time using an internal control loop that may be an integrator or proportional-integral control as shown in fig. 5 (e.g., blocks 542, 552, and 554).

The processing circuit 180 may be configured to switch the switch 142 based on the value of the actual on-time. For example, processing circuitry 180 may select a QR mode (e.g., QR1, QR2, or QR3) based on the measured switching frequency. Processing circuitry 180 may cause gate driver 190 to turn on switch 142 during a local minimum portion of the value corresponding to the on-time.

The processing circuit 180 may be configured to control a parameter or characteristic of a signal generated by the gate driver 190. In some examples, the processing circuit 180 may be configured to generate a lower power control signal and the gate driver 190 may be configured to convert the lower power control signal to a driver signal having a higher power. Processing circuitry 180 and gate driver 190 may be combined into a single integrated circuit or a single controller (e.g., controller 170). Alternatively, the processing circuit 180 and the gate driver 190 may be built on separate circuits, chips, or devices.

The memory 192 may be configured to store any value or any signal described herein, such as an on time, an off time, a switching frequency, a current, a capacitance, a target value, an error value, and/or any other parameter or value. In some examples, memory 192 may store program instructions that may include one or more program modules that may be executed by processing circuitry 180. When executed by the processing circuitry 180, such program instructions may cause the processing circuitry 180 to provide the functionality of the processing circuitry 180 ascribed herein.

Fig. 2A and 2B are exemplary diagrams of an input voltage 200 and a current 250 through one or more capacitors. In the example of fig. 2A, the input voltage 200 is a rectified half-sine waveform. The input voltage 200 mayTo be the output signal generated by the rectifier circuit and/or the input signal received by the PFC circuit. The input voltage 200 may be represented by the variable v in equations (1) and (2) above_gAnd the DC value 210 may be represented by the variable v in equation (2) above_FFTo indicate.

The controller may receive the signal indicative of the input voltage 200 through, for example, a voltage divider circuit that reduces the input voltage 200 from tens or hundreds of volts to a range of two, three, four, or five volts. The controller may include an analog-to-digital converter (ADC) that converts the received signal to a digital value. The controller may apply a low pass filter, such as a two-stage low pass filter, to the received signal to determine the DC value 210. The low pass filter may eliminate or reduce harmonic components of the input voltage 200.

In the example of fig. 2B, current 250 is a portion of a sinusoidal waveform having an amplitude that varies every half cycle. Current 250 may be the sum of the currents through one or more capacitors in the filter circuit of the PFC circuit. Current 250 can be represented by variable i in equation (1) above_ctot(t) is shown. Linear approximation 260 is a straight line approximating the amplitude of current 250 for each half-cycle.

The period of the waveform shown in fig. 2A and 2B may be twice the frequency of the AC power source. The AC power supplied by the mains may have a frequency of fifty hertz or sixty hertz. In contrast, the switching frequency for the switches in the PFC circuit may be in the range of one khz to one megahertz. The switching frequency is typically operated above twenty kilohertz otherwise the EMI filter would be very large to filter low frequencies. To increase the power factor, particularly at light loads, the controller may estimate the current 250 to compensate for the current 250.

In some examples, the controller may estimate the current 250 using a linear approximation 260. For example, the controller starts a counter or timer when a sensing signal received by the controller exceeds a threshold. The controller may include a comparator for comparing the current 250 to a threshold. The threshold value may be adjusted by a base parameter and a gain parameter. The base parameter corresponds to a base value of the comparator threshold. The gain parameter sets the slope of the linear approximation 260 and the controller may apply the comparator threshold to the capacitive current compensation. Linear approximation 260 is a simple implementation of the sinusoidal waveform of current 250. However, linear approximation 260 may not fully compensate for current 250 and may introduce current distortion.

Fig. 3 is a circuit diagram of a system including a rectifier circuit 320 and filter circuits 310 and 330 according to one or more aspects of the present disclosure. The filter circuits 310 and 330 and the rectifier circuit 320 are shown as passive circuits, but may include active components in some examples. For example, the diodes of the rectifier circuit 320 may include parallel switches to reduce voltage drop when the diodes are conducting. In operation, the filter circuit 310 receives power from the power supply 302. The rectifier circuit 320 may generate a rectified signal based on the first filtered signal from the filter circuit 310. The filter circuit 330 may filter the rectified signal and pass the second filtered signal to a PFC circuit, which is not shown in fig. 3.

Filter circuits 310 and 330 include capacitors 360, 362, 364, and 366. In some examples, filter circuits 310 and 330 include more or fewer than four capacitors. Filter circuits 310 and 330 may be arranged in different configurations or combinations, and capacitors 360, 362, 364, and 366 and inductors 314 and 334 may be arranged in different locations. The filter circuits 310 and 330 may function to reduce EMI and other noise reflected back to the power supply 302. The currents 370, 372, 374, and 376 through the capacitors 360, 362, 364, and 366 may constitute reactive power flow rather than real power flow, which may reduce the power factor if the controller does not compensate for the currents 370, 372, 374, and 376.

Each of the filter circuits 310 and 330 includes a passive capacitor-inductor-capacitor (C-L-C) configuration before and after the diode bridge of the rectifier circuit 320. the voltage drop across the diode bridge of the rectifier circuit 320 may be insignificant compared to the AC input voltage generated by the power supply 302, which may be 90VAC to 264 VAC.

The controller may also determine the value of the current through capacitors 360, 362, 364, and 366 based on the equivalent capacitance and the voltage across the diode bridge of rectifier circuit 320. In some examples, the controller receives a voltage signal from the output node 322, where the voltage signal is indicative of the input voltage received by the PFC circuit. The current through capacitors 360, 362, 364, and 366 is the sum of currents 370, 372, 374, and 376. The controller may determine an estimate of the sum of currents 370, 372, 374, and 376 by taking the derivative of the voltage level of the rectified signal generated by rectifier circuit 320 and multiplying the equivalent capacitance by the derived voltage level, as shown in equation (1) above.

In the circuit arrangement shown in fig. 3, the input current 304 may be equal to the currents 370 and 372 through the capacitors 360 and 362 plus the output current 350 of the rectifier circuit 320, as shown in equation (4). Equation (4) also shows that input current 304 equals output current 352 plus total current i through capacitors 360, 362, 364, and 366_Ctot. Equations (5) and (6) show the calculation of the currents through capacitors 360, 362, 364, and 366 and the equivalent capacitances C of capacitors 360, 362, 364, and 366, respectively_totAnd (4) calculating.

i₃₀₄＝i₃₅₀+i₃₇₀+i₃₇₂＝i₃₅₂+i₃₇₀+i₃₇₂+i₃₇₄+i₃₇₆＝i₃₅₂+i_Ctot(4)

i_Ctot＝i₃₇₀+i₃₇₂+i₃₇₄+i₃₇₆(5)

C_tot＝C₃₆₀+C₃₆₂+C₃₆₄+C₃₆₆(6)

Fig. 4 is a phasor diagram of inductor current, capacitive current and input current. The inductor current is also referred to as real or active current and is shown in the x-axis dimension. The capacitive current is also referred to as a virtual current or reactive current and is shown in the y-axis dimension. The input current is the sum of the real and reactive currents such that the input current is between the real and reactive axes. The input current has a phase angle between the input current and the real axis (x-axis). The phase angle is a phase shift in the input current.

The power factor is equal to the distortion factor multiplied by the displacement factor. Distortion factor equal to I₁Rms divided by I_inRms, wherein I₁RMS is the Root Mean Square (RMS) current of a fifty hertz signal or a sixty hertz signal. I is_inRMS is the RMS value of the input current. The displacement factor is the cosine of the phase angle. The effect of phase angle on power factor is important for the control of the PFC circuit. The larger the phase angle, the lower the power factor. The effect on power factor may be particularly pronounced at light loads, since the capacitive current may be kept constant while the real current is reduced. Thus, at light loads, the phase angle and power factor may be increased.

Under heavy load 440 conditions, the capacitive current 422 flowing through one or more capacitors may be significantly less than the active current 424 flowing into the PFC circuit. Vector 420 represents the total current based on currents 422 and 424. Thus, under heavy load 440, the phase shift between the input current and the input voltage, represented by angle 402, is relatively small. Thus, in the example of fig. 4, the power factor under heavy load 440 is relatively high due to the high magnitude of active current 424.

At light load 430, the capacitive current 412 flowing through the one or more capacitors may be more significant relative to the active current 414 flowing into the PFC circuit under heavy load 440. Vector 410 represents the total current based on currents 412 and 414. Thus, under light load 430, the phase shift between the input current and the input voltage, represented by angle 400, is relatively large. Thus, in the example of fig. 4, the power factor under heavy load 440 is higher than the power factor under light load 430.

Fig. 5 is a conceptual block diagram of a control loop for determining the on-time of a switch in a PFC circuit according to one or more aspects of the present disclosure. Controller 570 may implement control loops in the digital domain, the analog domain, and/or the hybrid digital/analog domain. Controller 570 may implement digital multi-mode PFC control for QR conduction mode operation. Each of the blocks and circles shown in fig. 5 is a functional block in which the controller 570 calculates an output value based on an input value.

At voltage controller 512, controller 570 may determine control voltage 520 (v)_control) Proportional to the output power of the PFC circuit. The voltage controller 512 may be a Proportional Integral (PI) controller or a PI derivative (PID) controller. At multiplier 522, controller 570 may feed forward 524 (v) the control voltage 520, the input voltage_FF) Is multiplied by a constant 526 based on the clock period of the controller 570. The input voltage feedforward 524 includes a sampled rectified AC input voltage (v)_g) DC equivalent value (v) of_FF). The inductor current with input voltage feed forward is referenced as equation (7).

The average inductor current in the switching period is given by equation (8). In equation (8), v_gIs a rectified AC input voltage v_controlIs a control voltage 520, K₁Is a proportionality constant, v, for balancing the gain difference between the reference inductor current and the sampled average inductor current_FFIs the DC equivalent value, t, of the sampled rectified AC input voltage_onIs the on-period, t, of the PFC MOSFET_offIs the off period, t, of the PFC MOSFET_swIs the measured variable switching period and L is the boost inductance.

To achieve good input current shaping, the controller 570 may apply equation (9). The controller 570 may calculate the desired on-time 540 such that the average inductor current follows the inductor current reference. Controller 570 may calculate the difference between the output value of multiplier 522 and term 534 based on the current flowing through one or more capacitors.

The controller 570 may use the internal feedback controller 552 and the feedback block 554 to cause the effective on-time 556 to follow the desired on-time 540. At the adder 542, the controller 570 may calculate an error value 550 as the difference between the effective on-time 556 and the desired on-time 540. At block 562, the controller 570 may determine the actual on-time 564 by multiplying the quantized on-time 560 by the clock period. Block 562 may be a mathematical model of a Pulse Width Modulation (PWM) operation. The controller 570 may quantize the on-time T_on560 to block 562 to generate the actual on-time 564 (t)_on). The actual on-time 564 may not necessarily be calculated by the controller 570 because the PWM hardware unit has a time unit equal to the inverse of the switching frequency. In some examples, the controller 570 may generate the actual on-time 564 by multiplying the quantized on-time 560 by a clock period. Quantized on-time 560 controls the controller clock T_clkMay be digital values and the voltages are quantized with respect to the reference voltage and resolution of the ADCs of controller 570. For example, the quantized on-time 560 may have a digital value of one thousand, the clock period may be twenty nanoseconds, and the actual on-time 564 may have a value of twenty microseconds. Equation (10) is similar to equation (9) but equation (10) includes a quantization time instead of an actual time.

The controller 570 may use an inner control loop to achieve good input current shaping. Good input current shaping means that the controller 570 switches the switches of the PFC circuit so that the input current drawn by the PFC circuit closely matches the input voltage. The inner control loop includes an adder 542, an inner feedback controller 552, and a feedback block 554. Using the inner control loop, the controller 570 can cause the effective on-time to follow the desired on-time. The controller 570 may use an integrator to ensure that the following error is zero. Thus, the internal feedback controller 552 is typically an integrator or PI control (proportional operation makes the control faster than using an integrator alone).

The controller 570 may implement a digital differentiator using equations (11) and (12), where i_s(t) is the current through one or more capacitors. V_gIs a rectified AC input voltage v_gNumerical representation of, T_svIs the execution rate or sampling rate, and K_dIs the differentiator gain. The last term of equation (12) may compensate for the current through one or more capacitors. In some examples, the digital differentiator may have a high frequency pole to filter out switching noise.

The controller 570 may be configured to determine the bus voltage 580 at block 572 based on the actual on-time 564. Example values of bus voltage 580 include 380 volts or 390 volts. Block 572 may be an equivalent device (plant) model representing QRM boost PFC. The block 572 may not necessarily be part of an implementation of the controller 572. The plant model may be used to design the controller 570 for stable closed loop operation. The controller 570 may feed the quantized on-time 560 to the PWM driver to generate the actual on-time 564 for driving the MOSFET in the PFC circuit. The controller 570 may turn the PFC circuit on and off according to the actual on-time 564 and the QR number to regulate the bus voltage 580 and ensure good input current shaping. The controller 570 may model this switching behavior as a device model in block 572.

The PWM driver may send the actual on-time and on-instances to the gate driver, which will then turn the switch on and off to regulate the bus voltage 580 and ensure good input current shaping. At block 582, the controller 570 may apply the resistor divider ratio to the bus voltage 580 to calculate a scaled value 590 of the bus voltage 580.

At adder 502, controller 570 may calculate error value 510 based on target bus voltage 500 and scaled value 590 of bus voltage 580. The target bus voltage 500 may be a command for a desired bus voltage amplitude, such as 380 volts or 400 volts. The controller 570 may compare the scaled value 590 to the target value 500 to determine the error value 510. For example, the controller 570 may subtract the scaled value 590 from the target value 500 at the adder 502. The controller 570 may determine the control voltage 520 at least in part by integrating the error value 510.

Fig. 6 and 7 are timing diagrams illustrating operation of a PFC circuit according to one or more aspects of the present disclosure. The controller may operate the PFC circuit in Discontinuous Current Mode (DCM) such that the inductor current of the PFC circuit drops to zero and remains zero for at least a short delay time. The output current of the PFC circuit may be equal to an inductor current of the PFC circuit during a period in which a switch of the PFC circuit is turned off. DCM differs from Continuous Current Mode (CCM) where the inductor current does not drop to zero during the switching period.

Fig. 6 includes four timing diagrams illustrating: (1) a gate voltage for a switch of the PFC circuit; (2) a current through a load current path of the switch; (3) an output current of the PFC circuit; and (4) the voltage across the load current path of the switch. Current flowing through the load current path of the switch may energize an inductor of the PFC circuit. The output current of the PFC circuit may charge an output capacitor of the PFC circuit. The inductor current may be a superposition or sum of the current through the switch and the output current. Thus, the inductor current may have a triangular waveform that increases from zero (e.g., during period 600) and then decreases to zero (e.g., during period 622).

Marked as T_swMay be defined as the duration of one switching cycle and is equal to the inverse of the switching frequency. The switching period may be divided into an on time 600 and an off time 602. The turn-off time may be divided into a fall time 622 followed by a delay time 624. During the falling time 622, the current is outputDecreasing from a maximum value to zero. During the subsequent delay time 624, the output current remains at or near zero magnitude.

At time 650, the controller may turn off (e.g., switch) the switches of the PFC circuit by reducing the gate voltage of the switches to zero or near zero. The controller may determine when to turn off the switch based on several parameters such as the rectified voltage received by the PFC circuit, the current through the switch, and the output current of the PFC circuit. At time 650, the voltage across the load current path of the switch rapidly rises to a level that depends on the AC half cycle, as shown in equation (13). When the voltage level across the load current path approaches a constant level, the voltage rings or oscillates during period 630.

Prior to time 650, the inductor current of the PFC circuit is sunk by the load current path of the switch. After time 650, the inductor current of the PFC circuit is conducted by the diode of the PFC circuit, which is shown in the output current waveform. The voltage across the load current path then slowly decreases until time 652. Between time 650 and time 652, the output current of the PFC circuit decreases to zero and the load path current equals zero. When the output current reaches zero at time 652, the voltage across the switch begins to oscillate while the output current remains at zero.

The first minimum value of the voltage across the switch may be approximately zero volts during time period 624. The amplitude of the oscillation then gradually decays, undergoing local minima 632, 634 and 636. Local minima 632, 634, and 636 can also be referred to as valleys or troughs. The controller may turn on (e.g., toggle) the switch at time 654 by increasing the gate voltage of the switch to initiate a new on-period 600. The controller may include a gate driver to generate and communicate a drive signal to a controller terminal of the switch. The controller may determine when to turn on the switch by determining a local minimum of the voltage across the switch. In the example of fig. 6, the controller selects the third local minimum to turn on the switch.

The controller may detect a local minimum of the voltage drop across the load current path of the switch by detecting an override of a threshold value, such as zero volts or any other threshold level. In some examples, the controller may determine a period of oscillation of the voltage across the switch between time 652 and time 654, where period 660 may represent half of the period of oscillation. In an example where the controller selects the QR3 mode, the controller may determine an override of the threshold level 670 and start a timer. When the timer reaches one-quarter of the period of oscillation, the controller may turn on the switch, which will correspond to the third local minimum 636. By turning on the switch at a local minimum, the controller reduces switching losses compared to turning on the switch when the voltage drop across the switch is high.

The controller may use an auxiliary winding in the PFC inductor to detect the local minimum. The controller may measure an inverted buck value of the inductor voltage. When the MOSFET in the PFC circuit is turned on, the inductor voltage may equal the instantaneous rectified input voltage, which is a positive voltage. When the MOSFET is turned off, the inductor voltage may be equal to the input voltage minus the output voltage (negative voltage). Since the auxiliary winding provides an inverted voltage value, the auxiliary winding has a negative voltage when the MOSFET is on and the auxiliary winding has a positive voltage when the MOSFET is off. The controller may clamp the positive voltage to a positive limit and the controller may clamp the negative voltage to a small negative voltage. When the voltage at the Zero Crossing Detection (ZCD) pin exceeds a threshold near zero, the controller may increase the latency of one quarter of the oscillation period to reach the valley point. The oscillation period may be a resonant oscillation period and the controller may measure the oscillation period. The controller may use a fixed value for the oscillation period.

The controller may select an nth local minimum to turn on the switch, where N is an integer equal to or greater than 1. The local minimum of the voltage across the switch is also referred to as the "quasi-resonant" (QR) turn-on condition. The QR switch may reduce switching losses for operation of the PFC circuit by increasing the switching period 604. In the example where the controller sets N equal to 1, DCM is referred to as critical conduction mode (CrCM) or Boundary Conduction Mode (BCM). Thus, BCM or CrCM is a special case of DCM. During QR operation, the controller may adjust on-time 600 and time 656 (e.g., when the controller turns off the switch). In some examples, the controller may determine the on-time 600 using a value that varies based on the AC half-cycle for QR operation. For CrCM operation or BCM operation, the on-time may have a constant value or near constant value throughout the AC half-cycle.

For QR1 operation, the controller may turn on the switch during local minimum 632. Thus, the off time for the switch is equal to the sum of the time period 622 and the time period 660. Marked t in the above equation_on+t_offMay be equal to the sum of time periods 600, 622, and 660. For QR2 operation, the controller may turn on the switch during local minimum 634. For QR3 operation, the controller may turn on the switch during local minimum 636. The controller may detect the first local minimum value based on the voltage exceeding the threshold level. The controller may then count the number of valleys until the selected number is reached. The controller may be configured to set the timer to turn on the switch near the selected local minimum.

Fig. 7 shows a waveform for a QR1 switch, where a controller turns the switch on during a first local minimum of the voltage drop across the switch. Referring back to the example shown in fig. 6, the local minimum 632 is the first local minimum in the voltage drop across the switch. Using a switching scheme with constant on-time and QR1 may result in good performance of the PFC circuit. Thus, a power factor close to unity can be achieved with this switching scheme.

Returning to the example shown in fig. 7, the average inductor current 714 is proportional to the input voltage 700 and is in phase. Inductor current 710 ranges from zero to a maximum inductor current 712 for each switching cycle. The maximum inductor current 712 ranges from a maximum value at time 740 to zero at time 742. Fig. 7 depicts eleven switching cycles for each period of the input voltage 700, but there may be any number of switching cycles for each period, such as hundreds or thousands of switching cycles. The rise time for inductor current 710 is equal to pulse duration 720, and pulse duration 720 is the on time for the switches of the PFC circuit.

The switching frequency 730 varies over a relatively wide range based on the input voltage 700 and the load provided by the PFC circuit. For example, switching frequency 730 ranges from a minimum value at time 740 to a maximum value at time 742. High switching frequencies may be undesirable because of lower efficiency due to electromagnetic interference and high switching losses. It may be desirable to reduce the switching frequency, particularly during low line, heavy load conditions.

The controller of the present disclosure may improve the power factor at light loads for PFC circuits in QRM or CrCM operation. In CrCM or QRM operation, a method of compensating for the capacitive current through the EMI capacitor may work if there is input voltage feed forward where the reference inductor current is available. CrCM control may be obtained from QRM control by fixed QR1 operation. The controller may operate with a varying on-time in each AC half-cycle rather than a constant on-time as in normal CrCM control.

The low power factor at light loads may be caused by the current flowing through the EMI capacitor at the input of the PFC circuit. Thus, to improve the power factor, instead of setting the inductor current reference equal to the input current minus the capacitive current, the modified inductor current reference is set equal to the input current so that the inductor current reference reflects the true current flowing in the PFC circuit. To approximate the capacitive current, the controller may use a digital differentiator to extract the capacitive current waveform. To achieve good current shaping, the controller may set the average inductor current in the switching cycle equal to the modified inductor current reference to obtain the desired on-time, as shown in equation (9). By having the effective on-time follow the desired on-time, the controller can determine the on-time to regulate the output voltage and achieve good current shaping. Due to QR operation and the varying switching frequency, the actual on-time varies during each AC half-cycle.

Fig. 8 is a flow diagram illustrating an example process for controlling a PFC circuit in accordance with one or more aspects of the present disclosure. The technique of fig. 8 is described with reference to the controller 170 shown in fig. 1, however other components, such as the controller 570 shown in fig. 5, may also illustrate a similar technique.

In the example of fig. 8, the controller 170 receives a first signal at node 172 indicative of the input voltage of the PFC circuit 140 (800). The controller 170 may receive a first signal from an output node of the rectifier circuit 120. The controller 170 may receive the first signal through a voltage divider circuit that reduces a voltage level of the input voltage from several tens or hundreds of volts to two or three volts. The input voltage may be a voltage signal received by the rectifier circuit 120, a voltage signal generated by the rectifier circuit 120, and/or a voltage signal received by the PFC circuit 140.

In the example of fig. 8, the processing circuit 180 determines a value of a current through one or more capacitors of the PFC circuit 140 based on the first signal (802). One or more capacitors may be disposed in filter circuits 310 and 330 and/or rectifier circuit 320 as shown in fig. 3 (e.g., capacitors 360, 362, 364, and 366). The controller 170 may convert the first signal received at the node 172 into a digital value using an ADC. The controller 170 may determine the current by taking a derivative of the first signal. For example, the controller 170 may differentiate the digital value of the first signal and multiply the differentiated value by the total capacitance of the one or more capacitors to calculate the current.

In the example of fig. 8, processing circuit 180 determines an on-time for switch 142 based on the value of the current (804). The processing circuit 180 may determine the desired on-time of the switch 142 based on the current and also based on the DC component of the first signal received at the node 172. Processing circuit 180 may use an integrator (e.g., internal feedback controller 552) to determine the actual on-time of switch 142. Processing circuit 180 may be configured to determine which local minimum to use as a trigger to turn on switch 142.

In the example of fig. 8, the processing circuit 180 switches the switch 142 based on the on-time (806). The processing circuit 180 may cause the gate driver 190 to pass an enable signal to a control terminal of the switch 142, where the enable signal has a voltage sufficient to turn on the switch 142. Processing circuitry 180 may use the determined on-time to calculate a local minimum during which switch 142 is turned on.

The following numbered examples illustrate one or more aspects of the present disclosure.

Example 1 a controller to control a switch of a power factor correction circuit, wherein the controller includes a first node configured to receive a first signal indicative of an input voltage of the power factor correction circuit. The controller also includes a processing circuit configured to determine a value of a current through one or more capacitors of the PFC circuit based on the first signal. The processing circuit is further configured to determine an on-time of the switch based on the value of the current and switch the switch based on the on-time.

Example 2. according to the controller of example 1, the on-time of the switch is a desired on-time of the switch, and the processing circuit is further configured to determine the actual on-time based on the desired on-time using the inner control loop. The processing circuit is further configured to switch the switch based on the actual on-time.

Example 3. the controller according to examples 1-2, or any combination thereof, the switch is a first switch, and the controller is configured to control operation of the first switch, control operation of a second switch of the power converter, wherein the power converter is coupled to the PFC circuit.

Example 4. the controller of examples 1-3, or any combination thereof, further comprising a second node configured to receive a second signal indicative of a voltage drop across a load current path of the switch. The processing circuit is further configured to detect one or more local minimum portions of the second signal. The processing circuit is configured to determine the on-time at least in part by selecting a local minimum portion of the one or more detected local minimum portions based on the first signal.

Example 5. the controller of example 4, the processing circuit configured to switch the switch at least in part by turning on the switch during the selected local minimum portion.

Example 6. the controller according to examples 4 and 5, or any combination thereof, the processing circuit is configured to detect the one or more local minimum portions at least in part by detecting one or more zero crossings of the second signal.

Example 7. the controller of examples 1-6 or any combination thereof, the processing circuit configured to determine the value of the current through the one or more capacitors at least in part by taking a derivative of the first signal.

Example 8 the controller of example 7, the processing circuit configured to extract a waveform of current through the one or more capacitors based on the input voltage of the PFC circuit at least in part by taking a derivative of the first signal.

Example 9. the controller according to examples 7 to 8, or any combination thereof, the processing circuit is configured to control the switch to closely match the input current of the PFC circuit to the input voltage.

Example 10. the controller of examples 1 to 9, or any combination thereof, the processing circuit configured to determine the on-time based on a value of the current and further based on an output value of the PI control loop or an output value of the PID control loop.

Example 11. the controller of examples 1 to 10, or any combination thereof, the processing circuit configured to determine the on-time based on a value of the current and also based on an inductance of an inductor of the PFC circuit.

Example 12. the controller of examples 1-11, or any combination thereof, the first node is configured to receive the first signal from an output node of a rectifier circuit coupled to the PFC circuit.

Example 13. the controller according to examples 1 to 12, or any combination thereof, the processing circuit is configured to determine an on-time of the switch within the control loop. The processing circuit is further configured to compare, within a control loop, the output voltage of the PFC circuit to a target value within the control loop.

Example 14. the controller of examples 1-13 or any combination thereof, the processing circuit further configured to determine an error value within the control loop based on comparing the output voltage of the PFC circuit to a target value. The processing circuit is further configured to determine a control voltage based on integrating the error value within the control loop.

Example 15. a method for controlling switching of a PFC circuit. The method comprises the following steps: a first signal indicative of an input voltage of a PFC circuit is received, and a value of a current through one or more capacitors of the PFC circuit is determined based on the first signal. The method also includes determining an on-time of the switch based on the value of the current, and switching the switch based on the on-time.

Example 16. according to the method of example 15, the on-time of the switch is a desired on-time of the switch, and the method further comprises using an internal control loop to determine the actual on-time based on the desired on-time. The switch is switched based on the actual on-time.

Example 17. the method of examples 15 to 16, or any combination thereof, further comprising: a second signal indicative of a voltage drop across a load current path of the switch is received, and one or more local minimum portions of the second signal are detected. Determining the on-time includes selecting a local minimum portion of the one or more detected local minimum portions based on the first signal.

Example 18. the method of examples 15 to 17, or any combination thereof, switching the switch includes turning on the switch during the selected local minimum portion.

Example 19. the method of examples 15 to 18, or any combination thereof, determining the value of the current through the one or more capacitors includes taking a derivative of the first signal. The method also includes extracting a waveform of a current through one or more capacitors based on an input voltage of the PFC circuit at least in part by taking a derivative of the first signal.

An apparatus comprising a computer readable medium having stored thereon executable instructions configured to be executable by a processing circuit to cause the processing circuit to receive a first signal indicative of an input voltage of a PFC circuit. The instructions also cause the processing circuit to determine a value of a current through one or more capacitors of the PFC circuit based on the first signal. The instructions also cause the processing circuit to determine an on-time of a switch of the PFC circuit based on the value of the current and switch the switch based on the on-time.

Example 21 the apparatus of example 20, the instructions further cause the processing circuit to receive a second signal indicative of a voltage drop across a load current path of the switch, and detect one or more local minimum portions of the second signal. The instructions for determining the on-time include instructions for selecting a local minimum portion of the one or more detected local minimum portions based on the first signal.

The present disclosure attributes functionality to controllers 170 and 570 and processing circuitry 180. The controllers 170 and 570 and the processing circuitry 180 may include one or more processors. The controllers 170 and 570 and the processing circuit 180 may comprise any combination of integrated circuits, discrete logic circuits, analog circuits such as one or more microprocessors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), and/or Field Programmable Gate Arrays (FPGAs). In some examples, the controllers 170 and 570 and the processing circuitry 180 may include components such as any combination of one or more microprocessors, one or more DSPs, one or more ASICs, or one or more FPGAs, as well as other discrete or integrated logic circuitry and/or analog circuitry.

The techniques described in this disclosure may also be implemented or encoded in an article of manufacture that includes a non-transitory computer-readable storage medium, such as memory 192. Exemplary non-transitory computer readable storage media may include RAM, ROM, programmable ROM (prom), erasable programmable ROM (eprom), electrically erasable programmable ROM (eeprom), flash memory, a hard disk, a compact disc ROM (CD-ROM), a floppy disk, a magnetic cassette, magnetic media, optical media, or any other computer readable storage device or tangible computer readable medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or propagated signal. In some examples, a non-transitory storage medium may store data that can change over time (e.g., in RAM or cache).

Various examples have been described. These examples and other examples are within the scope of the following claims.