阅读说明：本技术 用于监测电路的装置和方法 (Apparatus and method for monitoring a circuit ) 是由 陈宏� 于 2018-11-15 设计创作，主要内容包括：提供了用于监测电路的装置,其中在两个电路位置处的信号转变之间的相对定时变化被标识,从而标识电路特性的变化。两个电路位置处的信号被多次采样,以生成第一采样信号和第二采样信号,并且第一采样信号和第二采样信号被进行比较来标识电路特性的变化。装置可以例如用于监测具有由脉宽调制电路驱动的栅极的晶体管。在脉宽调制电路输出和晶体管端子处的转变之间的相对定时变化用于标识晶体管特性的变化。这避免了对准确定时测量的需求,原因是它基于状态值的多次瞬时测量。在测量之间不需要准确的定时,并且实际上,实际定时可以是随机的。(Apparatus is provided for monitoring a circuit in which relative timing changes between signal transitions at two circuit locations are identified, thereby identifying changes in circuit characteristics. The signals at the two circuit locations are sampled a plurality of times to generate a first sampled signal and a second sampled signal, and the first sampled signal and the second sampled signal are compared to identify a change in a circuit characteristic. The apparatus may for example be used to monitor a transistor having a gate driven by a pulse width modulation circuit. The relative timing changes between the pulse width modulation circuit output and the transitions at the transistor terminals are used to identify changes in transistor characteristics. This avoids the need for measurement in the alignment determination, since it is based on multiple instantaneous measurements of state values. No accurate timing is required between measurements and, in fact, the actual timing may be random.)

1. An apparatus for monitoring a circuit, comprising:

a first input (40) adapted to receive a first signal from the circuit;

a second input (42; 42') adapted to receive a second signal from the circuit, the second signal originating from a location in the circuit different from the location of the first signal;

a controller (36) adapted to determine a change in relative timing between transitions of the signal at the first input (40) and the second input (42; 42') to identify a change in a characteristic of the circuit;

wherein the controller (36) is adapted to:

sampling the signals at the first input (40) and the second input (42; 42') a plurality of times to generate a first sampled signal and a second sampled signal;

comparing the first sampled signal and the second sampled signal; and

identifying a characteristic change of the circuit based on the comparison result.

2. The apparatus of claim 1, wherein the controller is adapted to:

counting occurrences of particular values of the paired first and second sampled signals within a time window; and

identifying a characteristic change of the circuit based on the count.

3. The apparatus of claim 2, wherein the sampled signal values comprise binary values and the particular values counted comprise:

01 and/or 10; or

00 and/or 11.

4. The apparatus of claim 2 or 3, wherein the controller (36) is adapted to:

obtaining the probability of the specific value; and

identifying a characteristic change of the circuit based on the probability.

5. The apparatus according to any of the preceding claims, wherein the controller (36) is adapted to perform the sampling at random or pseudo-random instants.

6. The apparatus of any preceding claim, further comprising a voltage divider between one or both of the first and second inputs and the controller.

7. The apparatus of any preceding claim, for monitoring a circuit comprising a transistor, wherein a gate of the transistor is driven by a pulse width modulation circuit (30) through a gate driver circuit (28), wherein:

the first input (40) is adapted to receive an output of the pulse width modulation circuit (30); and is

The second input (42) is adapted to receive a signal at a terminal of the transistor.

8. The apparatus of claim 7, wherein:

the second input (42) is adapted to receive an output of the gate driver circuit (28) at the gate of the transistor; or

The transistor has an input and an output, wherein the coupling between the input and the output is controlled by the gate, and wherein the second input (42') is adapted to receive a signal at the output of the transistor.

9. A transistor circuit, comprising:

a transistor (18) having a gate;

a gate driver circuit (28);

a pulse width modulation circuit (30), the pulse width modulation circuit (30) for providing a drive signal to the gate of the transistor through the gate driver circuit (28); and

apparatus as claimed in any preceding claim, for monitoring the transistor, wherein the first input (40) is coupled to an output of the pulse width modulation circuit (30) and the second input (42) is coupled to a terminal of the transistor.

10. A switched mode power supply comprising:

an energy storage unit (20); and

the transistor circuit of claim 9, for controlling energy transfer from a power supply input (10) to the energy storage unit and from the energy storage unit to an output load (26).

11. An L ED lighting driver, comprising:

the switched mode power supply of claim 10; and

a controller (32), the controller (32) for controlling the pulse width modulation circuit of the transistor circuit.

12. A lighting circuit, comprising:

l ED lighting driver according to claim 11, and

l ED arrangement (26), the L ED arrangement (26) being driven by the L ED lighting driver.

13. A method for monitoring a circuit, comprising:

(60) receiving a first signal from the circuit;

(62) receiving a second signal from the circuit, the second signal originating from a location in the circuit that is different from a location of the first signal; and

(64) determining a change in relative timing between transitions of the first signal and the second signal to identify a change in a characteristic of the circuit,

wherein determining the change comprises:

(65) sampling the first signal and the second signal a plurality of times to generate a first sampled signal and a second sampled signal;

(66) comparing the first sampled signal and the second sampled signal; and

(67) identifying a characteristic change of the circuit based on the comparison result.

14. The method of claim 13, comprising:

counting occurrences of particular values of the paired first and second sampled signals within a time window; and

identifying a characteristic change of the circuit based on the count.

15. A computer program comprising computer program code means adapted to perform the method of any of claims 13 to 14 when said program is run on a computer.

Technical Field

The present invention relates to apparatus and methods for monitoring circuits, such as circuits including power MOSFETs.

Background

Typically, the circuit performs a conversion function between input and output. If the circuit characteristics change (e.g., due to component aging or failure), the transformation function will change. Within such circuits, transistors are widely used to implement local functions at a certain location in the path between the input and output of the overall circuit. This local function may be critical to the overall circuit operation.

The use of pulse width modulation to control transistors is also widely used. It enables digital signals to be applied to the transistors to implement analog control functions (e.g., because the high switching speed of the digital signals has been effectively filtered out).

Power transistors (e.g., power MOSFETs) are, for example, critical components in switch mode power supplies such as those used in L ED drivers.

Unfortunately, there is no efficient way to perform real-time assessment of the health of a transistor. The known method is based, for example, on measuring temperature and voltage conditions, but the method is not sufficiently reliable. Temperature and voltage are not the only indicators of transistor performance, but they are a result of transistor performance characteristics and many other factors. Therefore, it is not straightforward to reliably indicate the state of health of a transistor based on temperature and voltage.

To ensure that transistors operate in safe regions, design engineers must use high-rated components to provide large design margins and verify their performance in reliability tests. This is expensive both in money and time. This problem applies generally to circuit designs, and is not specific to transistor circuits.

Accordingly, there is a need for a monitoring circuit and method that can be used in real time to assess the performance of a circuit (e.g., a circuit having transistors) that may be subject to changes in component characteristics. For example, monitoring means that a warning can be provided before a catastrophic failure.

Disclosure of Invention

The invention is defined by the claims.

One concept of the present invention is: changes in signal timing within a circuit are monitored, in particular by comparing signals at two circuit locations, where the circuit function between the two circuit locations may have a variable delay. These timing variations are caused by variations in circuit characteristics.

According to an example of an aspect of the present invention, there is provided an apparatus for monitoring a circuit, the apparatus comprising:

a first input adapted to receive a first signal from a circuit;

a second input adapted to receive a second signal from the circuit, the second signal originating from a location in the circuit different from the location of the first signal;

a controller adapted to determine relative timing changes between signal transitions at the first and second inputs, thereby identifying a change in a characteristic of the circuit;

wherein the controller is adapted to:

sampling a signal a plurality of times at a first input and a second input to generate a first sampled signal and a second sampled signal;

comparing the first sampled signal and the second sampled signal; and

a change in the circuit characteristic is determined based on the comparison result.

The monitoring circuit is used to determine timing differences (particularly changes in those timing differences) caused by the delay that exists between two circuit locations. The change in delay may be used to identify a change in circuit characteristics. This may, for example, enable a warning to be provided before the circuit breaks down or otherwise fails. The change in the characteristic is determined by comparing sampled signals from the first and second inputs. The result of the comparison depends on the time delay (between the signals at the first and second inputs) caused by the circuit, but this time delay does not need to be measured by a timer.

The controller may be adapted to:

counting occurrences of particular values of the paired first and second sampled signals within a time window; and

a change in the circuit characteristic is identified based on the count.

The method involves counting occurrences of particular value pairs. For example, for a binary signal, the two values will be different when the signal at the first input is not synchronous with the signal at the second input, due to the delay between the transitions between the two signals. This delay is a characteristic of the circuit being monitored (e.g., the delay between the ideal transistor gate signal and the actual gate signal that reaches the gate and thus propagates to the transistor output). If the count for a given time window changes, it means that the delay has changed. By simply counting the occurrences of a particular value pair, an accurate timer is not required.

The sampled signal values may comprise binary values, and the particular values counted include:

01 and/or 10; or

00 and/or 11.

If the signals on the first and second inputs are generally the same and any difference indicates a delay, then the 01 and/or 10 values are monitored. If the signals on the first and second inputs are generally in anti-phase form with each other and any condition in which they are the same indicates a delay, the 00 and/or 11 values are monitored.

It is assumed that the first value of the pair is for the first input and the second value of the pair is for the second input.

For the case where the signals at the two inputs are the same, the 01 signal indicates the delay for the signal at the second input to fall from 1 to 0, and the 10 signal indicates the delay for the signal at the second input to rise from 0 to 1.

For the case where the signals at the two inputs are inverted, the 00 signal indicates a delay for the signal at the second input to rise from 0 to 1, and the 11 signal indicates a delay for the signal at the second input to fall from 1 to 0.

By using a sampling method, the actual delay does not need to be measured, but is analyzed based on a statistical method by which the count value represents the actual delay.

Thus, the results of the analysis are not time-based, but relative to the time between two signal transitions.

The controller may be adapted to:

obtaining the probability of a specific value; and

changes in circuit characteristics are identified based on the probabilities.

The count value may thus be used to represent a probability (and thus equivalent to the fraction of time during which there is an undesired signal pair, and in turn equivalent to a time delay).

The time window may comprise at least 1000 samples (e.g., at least 5000 samples) and/or the time window may comprise at least 100 cycles of the signal at the first input and the second input.

Statistical methods for a large number of samples of a large number of signal pulses enable identification of small changes in circuit performance, which correspond to small changes in circuit characteristics.

The controller may be adapted to perform the sampling at random or pseudo-random times.

By using random sampling it is ensured that the timing of the sampling instants is not synchronized with the timing of the signals on the first and second inputs.

The apparatus may further comprise a voltage divider between one or both of the first input and the second input and the controller. This serves to enable the two signals to be compared in a binary manner, i.e. to generate an input suitable for use in a comparator.

Apparatus, for example for monitoring a circuit comprising a switched mode semiconductor device such as a transistor, wherein the gate of the transistor is driven by a pulse width modulation circuit by means of a gate driver circuit, wherein:

the first input is adapted to receive an output of the pulse width modulation circuit; and is

The second input is adapted to receive a signal at a terminal of the transistor.

The monitoring circuit is used to determine timing differences (particularly variations in those timing differences) arising from delays introduced by the gate driver and optionally by the transistors themselves. The pulse width modulation circuit delivers the ideal gate voltage, but after passing through the gate driver and optionally also the transistor, an imperfect gate voltage reaches the transistor gate, or an imperfect output signal reaches the transistor output. This imperfection is a result of the gate driver itself in combination with the transistor characteristics. Thus, changes in relative timing can be used to identify changes in transistor characteristics. This may for example enable a warning to be provided before the transistor breaks down or otherwise fails.

In one example, the second input is adapted to receive an output of the gate driver circuit at a gate of the transistor. This example only enables monitoring at the input side of the transistor and is therefore easy to implement.

In another example, the transistor has an input and an output, wherein the coupling between the input and the output is controlled by the gate, and wherein the second input is adapted to receive a signal at the output of the transistor. This provides monitoring at the output of the transistor (e.g., the source of the MOSFET).

In both cases, the present invention does not require an accurate determination of the actual delay value and therefore does not require accurate timing measurements.

The present invention also provides a transistor circuit comprising:

a transistor having a gate;

a pulse width modulation circuit for supplying a drive signal to a gate of the transistor through the gate driver circuit; and

the monitoring device for monitoring a transistor as defined above, wherein the first input is coupled to an output of the pulse width modulation circuit and the second input is coupled to a terminal of the transistor.

The transistor circuit includes a monitoring circuit for monitoring the health of the transistor. The transistor is, for example, a power transistor such as a power MOSFET (which means, for example, a power rating of greater than 10 watts).

The invention also provides a switched mode power supply comprising:

an energy storage unit; and

a transistor circuit as defined above for controlling the transfer of energy from the power supply input to the energy storage unit and from the energy storage unit to the output load.

The switched mode power supply may be any type of converter (e.g., a buck converter, a boost converter, or a buck-boost converter). The energy storage unit may be an inductor or a capacitor. Switched mode power supplies are widely used in high power electronic circuits.

The present invention also provides an L ED lighting driver, the L ED lighting driver comprising:

a switched mode power supply as defined above; and

and the controller is used for controlling the pulse width modulation circuit of the transistor circuit.

The present invention also provides a lighting circuit comprising:

l ED lighting driver as defined above, and

l ED arrangement driven by L ED lighting driver.

The invention thus enables real-time transistor monitoring in switched mode power supplies used in, for example, L ED lighting drivers.

The invention also provides a method for monitoring a circuit, the method comprising:

receiving a first signal from a circuit;

receiving a second signal from the circuit, the second signal originating from a location in the circuit that is different from a location of the first signal; and

determining relative timing changes between transitions of the first signal and the second signal, thereby identifying changes in circuit characteristics,

wherein determining the change comprises:

sampling the first signal and the second signal for a plurality of times to generate a first sampled signal and a second sampled signal;

comparing the first sampled signal and the second sampled signal; and

a change in the circuit characteristic is determined based on the comparison result.

The monitoring method determines timing differences caused by delays introduced by the circuit. The delay is associated with a change in circuit characteristics.

The method can comprise the following steps:

counting occurrences of particular values of the paired first and second sampled signals within a time window; and

a change in the circuit characteristic is determined based on the count.

The method can comprise the following steps:

obtaining the probability of a specific value; and

changes in circuit characteristics are identified based on the probabilities.

The time window comprises, for example, at least 1000 samples (e.g., at least 5000 samples) and/or at least 100 periods of the first and second signals.

The sampling is performed, for example, at random or pseudo-random times.

The invention may be implemented at least in part in software.

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter.

Drawings

Examples of the invention will now be described in detail with reference to the accompanying drawings, in which:

FIG. 1 shows L ED drivers;

FIG. 2 shows the driver circuit of FIG. 1 in more detail;

FIG. 3 shows an equivalent circuit representing various parasitic resistances and capacitances of the transistors and the gate driver;

FIG. 4 illustrates the operation of the circuit; and

fig. 5 illustrates a method for monitoring a transistor.

Detailed Description

The present invention will be described with reference to the accompanying drawings.

It should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the devices, systems and methods, are intended for purposes of illustration only and are not intended to limit the scope of the invention. These and other features, aspects, and advantages of the apparatus, systems, and methods of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings. It should be understood that the figures are merely schematic and are not drawn to scale. It should also be understood that the same reference numerals are used throughout the figures to indicate the same or similar parts.

The present invention provides an apparatus for monitoring a circuit in which relative timing changes between signal transitions at two circuit locations are identified, thereby identifying changes in circuit characteristics. The signals at two circuit locations are sampled a plurality of times to generate a first sampled signal and a second sampled signal, and the first sampled signal and the second sampled signal are compared to identify a change in a circuit characteristic. The apparatus may for example be used to monitor a transistor having a gate driven by a pulse width modulation circuit. The relative timing changes between the transitions at the pulse width modulation circuit output and the transistor terminals are used to identify changes in transistor characteristics. This avoids the need for measurement in the alignment determination, since it is based on multiple instantaneous measurements of the state values. No accurate timing is required between measurements and, in fact, the actual timing may be random.

The present invention relates generally to monitoring of circuits, and in particular where the circuits have a transfer function by which an input signal (e.g., a binary signal) is routed to an output in a delayed or pulse edge shaped manner, the delay or pulse edge shaping being related to a circuit characteristic. The signal routed to the output may be an inverted version or a non-inverted version of the signal at the input. The delay or edge shaping changes in accordance with aging or other changes in the circuit characteristics so that monitoring changes in the delay can be used as an indicator of circuit degradation, damage, aging or end of life.

The invention will be described in connection with a preferred application in which the circuit is used to monitor a transistor circuit, in particular where the transistor has a gate drive signal in the form of a pulse width modulated signal the invention will furthermore be described with reference to a preferred application of the invention in an L ED driver.

Figure 1 shows an L ED driver, L ED driver comprising a mains input 10, the mains input 10 powering a diode bridge rectifier 12 by means of a fuse 14, a metal oxide varistor 15 is used to suppress (absorb) any inrush current at the AC or DC input.

The output of the rectifier is stored across a smoothing capacitor 16 and is provided to one main terminal (source or drain) of a power transistor 18-in this example the other main terminal is connected to an energy storage device in the form of an inductor 20 and a flyback diode 22-an output capacitor 24 is provided in parallel with an output load 26, the output load 26 being an L ED arrangement in this example.

Transistor 18 has an input (e.g., a drain) at the output of the rectifier and an output (e.g., a source) coupled to the energy storage device, where the coupling between the drain and the source (i.e., the on-state of the transistor) is controlled by the gate.

Transistor 18, inductor 20, diode 22 and output capacitor 24 function as a buck converter. The transistors operate at a duty cycle to change the charge and discharge phases of the circuit, thereby changing the conversion rate.

There are also other possible switch-mode power converters (e.g., boost converters or buck-boost converters) that use a main switching transistor controlled with a pulse width modulated signal.

The gate of transistor 18 is provided with a signal generated by a gate driver circuit 28. The input to the gate driver circuit is provided by a pulse width modulation circuit (oscillator) 30. The duty cycle of the pulse width modulated signal is controlled by feedback, e.g. based on the output voltage at the load. This provides a regulated output voltage. Likewise, the output current may be regulated. Fig. 1 shows a general feedback comparator 32 for comparing an output signal with a reference value 34. The comparator 32 serves as a controller for controlling the pulse width modulation circuit. It may be more complex than the simple comparator shown and for example comprise a control integrated circuit.

Within the above range, the circuit is conventional.

The present invention is implemented by the controller 36. The controller 36 has a first input 40 and a second input 42, the first input 40 receiving the output of the pulse width modulation circuit 30 and the second input 42 receiving a signal at a terminal of the transistor. In this way, the effect of transistor characteristics on a previously ideal pulse width modulated signal can be detected.

Fig. 1 shows two possible implementations. The first implementation is based on the controller receiving the output of the gate driver circuit 28 (i.e., the signal at the gate of transistor 18). This is shown by the solid line 42. Another alternative is to use a signal at the output of the transistor, e.g. the source (but it could equally be the drain, depending on the type and connection of the transistor). This alternative is shown as dashed line 42'.

The controller determines the relative timing changes between the signal transitions at the first input 40 and the second input 42 to identify changes in the characteristics of the transistor 18.

The controller 36 may be an existing controller of the L ED driver, in which case the invention may be implemented as a change in driver software only.

Fig. 2 shows the driver circuit 28 in more detail. It is used to transfer the PWM signal from PWM circuit 30 to transistor 18 for better on/off control. Essentially, it comprises a level shifting resistor divider circuit (resistors R1, R2) with zener diodes U1 and U2 for threshold setting and a pull down resistor-diode arrangement R3, D1.

Transistor 18 has a stray capacitance that typically ranges from a few hundred picofarads to tens of nanometers farads depending on the transistor design. The various parasitic resistances and capacitances may be represented by the equivalent circuit of fig. 3, in which there is a series gate resistance R and a parallel gate capacitance Cg.

The series gate resistance R is a combination of a resistance Rd representing the driver circuit 28 and an actual gate resistance Rg of the transistor. The capacitance Cg is the total input capacitance of the transistor. Rg and Cg are the basic parameters of a transistor, and any variation in transistor characteristics will affect both parameters.

By observing the changes in Rg and Cg, the state change of the transistor can be determined. However, measuring these parameters in real time with high accuracy is challenging.

The invention is based on the recognition that: the RC network of fig. 3 will affect the signal phase as the pulse signal passes through it, and these changes in signal phase can be used as indicators of changes in transistor characteristics. The phase lag is accurately determined by the RC value. Thus, variations in the RC value will have different phase effects on the signal being processed. Thus, there is a relationship between the state of the transistor and the signal phase shift.

The PWM circuit uses an application specific integrated circuit to generate the PWM signal and has an ideal square wave with sharp rising and falling edges. When the PWM signal passes through the RC network equivalent circuit, the rising and falling edges of the signal will change slightly. By comparing the signals before and after the RC network, variations in the gate resistance and gate capacitance Rg and Cg of the transistor can be observed when the resistance Rd is fixed.

The controller 36 reads the signals at the two inputs (which together form part of the I/O port) in a binary fashion at random times to detect the state of the two pins as shown. Each input thus has a state "1" or "0". The read operation of the controller is random so that it is not synchronized with the periodic PWM signal. In this way, all possible combinations of pin states can be derived, since the read operation can occur at any phase of the PWM signal.

Fig. 4 shows the operation of the circuit and is based in particular on using a transistor gate for the second input.

The top graph 50 shows the timing instants at which the controller 36 reads the signals on the two inputs, in the set of arrows. The controller may make a binary decision simply based on the threshold level to which the signal is compared. The threshold level may be between the voltage rails, but this is not required. Since only the variation in relative timing is of concern, the threshold value does not matter as long as the same index is used to distinguish between 1 and 0 each time.

The second graph shows the input V to the controller received from the pulse width modulator circuit 30_PWM。

The third graph shows an input Vgl received from the transistor gate to the controller when the transistor has the first set of characteristics.

The fourth graph shows an input Vg2 received from the transistor gate to the controller when the transistor has the second set of characteristics.

Signal V_PWMIs an ideal pulse signal with sharp edges. In this method, it is used as a reference signal.

Due to transistor decay between the third and fourth curves, the gate capacitance Cg increases, for example, from Cg1 to Cg 2. As shown, the rising and falling edges change.

The controller 36 reads four possible signal pairs, namely 10, 11, 00 and 01. The phase lag causes some read signal change. In particular, the signals "10" and "01" are closely related to the rise time delay caused by the RC equivalent circuit.

For the five timing instants shown, the readings are:

Vgl：10 11 00 11 01

Vg2：10 11 01 11 01

thus, it can be seen that the delay results in an additional occurrence of the 01 value.

If the controller is running for a given period of time, a probability of "10" or "01" can be derived. For example, the controller may read two pin states 10,000 times. The value "10" may occur 50 times. In subsequent analysis, the number of "10" values may become 60. This represents a change in the Rg and Cg values of the transistor. The larger the value of Rg and/or Cg, the larger the switching losses and therefore the higher thermal risk that may be catastrophic for the transistor.

In this way, the performance of the transistor can be monitored in real time and an alarm can be provided. Additionally, the solution is low cost and highly reliable since no complex hardware is required.

The method may be based on counting 01 values or 10 values or both. These situations arise when the ideal gate signal is not synchronized with the actual gate signal arriving at the gate. If the count changes (within a given time window) it indicates that the delay has changed. By simply counting the occurrences of word values, an accurate timer is not required.

The 01 signal indicates, for example, a delay for the actual gate signal to fall from 1 to 0, and the 10 signal indicates a delay for the actual gate signal to rise from 0 to 1. The actual delay need not be measured but is analyzed on the basis of statistical methods by which the count value represents the actual delay.

For example, for a 50kHz PWM signal, 5000 samples may be randomly acquired in a 5 second window. More generally, the time window comprises, for example, at least 1000 samples and may comprise at least 100 pulse width modulated signal periods.

As mentioned above, the example waveform of fig. 4 is based on connection 42 of fig. 1, but the same method can be applied to the transistor source using connection 42'. In the latter case, the output voltage of the transistor is typically much higher than the gate voltage, so that a voltage divider can be used in the controller 36 so that the signals can be compared again. There may be a voltage divider associated with one or both inputs of the controller.

The above example is based on a circuit where the signal at the second input (i.e. the local circuit output) should follow the signal at the first input (i.e. the local circuit input). Thus, the local circuit portion (i.e., transistor) being monitored has a pass-through characteristic. The local circuit portions being monitored may be inverted with respect to each other if they have inverted transfer characteristics. In this case, 00 and/or 11 values may be monitored. The 00 signal indicates a delay for the signal at the second input to rise from 0 to 1, and the 11 signal indicates a delay for the signal at the second input to fall from 1 to 0.

Thus, more generally, a particular sample value pair or indeed a particular set of sample value pairs (e.g., 01, 10, 01 and 10,00, 11 or 00 and 11) is monitored. The values to be monitored are related to the application and the circuit function.

Fig. 5 shows a method for monitoring a circuit, comprising:

(60) receiving a first signal from a circuit;

(62) receiving a second signal from the circuit, the second signal originating from a location in the circuit different from a location of the first signal; and

(64) changes in relative timing between transitions of the first signal and the second signal are determined to identify changes in circuit characteristics.

Determining the change includes:

(65) sampling the first signal and the second signal for a plurality of times to generate a first sampled signal and a second sampled signal;

(66) comparing the first sampled signal and the second sampled signal; and

(67) a change in the circuit characteristic is identified based on the comparison.

The circuit is, for example, a transistor circuit in which the gate of a transistor is driven by a gate driver circuit using a pulse width modulation circuit. The first signal is then received from the output of the pulse width modulation circuit and the second signal is received from a terminal of the transistor (e.g., the output of the gate driver circuit at the gate of the transistor, or the output terminal of the transistor).

As described above, embodiments utilize a controller. The controller may be implemented in a number of ways, using software and/or hardware, to perform the various functions required. A processor is one example of a controller that employs one or more microprocessors that are programmed using software (e.g., microcode) to perform the required functions. However, the controller may be implemented with or without a processor, and may also be implemented as a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions.

Examples of controller components that may be employed in various embodiments of the present disclosure include, but are not limited to, conventional microprocessors, Application Specific Integrated Circuits (ASICs), and Field Programmable Gate Arrays (FPGAs).

In various implementations, a processor or controller may be associated with one or more storage media (e.g., volatile and non-volatile computer memory such as RAM, PROM, EPROM, and EEPROM). The storage medium may be encoded with one or more programs that, when executed on one or more processors and/or controllers, perform the desired functions. Various storage media may be fixed within the processor or controller or may be removable such that the program or programs stored thereon may be loaded into the processor or controller.

The invention can be applied to any circuit in which a change in the transfer function to be monitored is monitored. The first and second inputs being monitored may be connected to any pair of circuit nodes having a fixed relationship (e.g., a fixed delay or an inverse with a fixed delay) between the signals that are normally expected. The first and second inputs may be at the input and output of a single critical component (e.g., a transistor in the above example) with a larger overall circuit, for example, or may be at the input and output of an arrangement of multiple components.

The invention is of particular interest for transistors that operate using duty cycle control of their gate signals. The PWM signal defining the duty cycle has, for example, a switching frequency in the kHz range (e.g., 1kHz to 1 MHz). The transistors may form part of any circuit (most typically a low pass filter implemented at the output) to smooth out high frequency ripple so that the basic analog output function is implemented using digital PWM control. This is the case for a switched mode power supply or a switched mode power converter, but such a function is also used in other circuits.

The invention is of particular interest for power transistors with operating powers of more than 10W, for example. The consequent heating in such devices increases the risk of thermal breakdown or electrical shock, which can be prevented by the monitoring described above.

Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims shall not be construed as limiting the scope.