阅读说明：本技术 一种建立光学数据校正模型的方法 (Method for establishing optical data correction model ) 是由 王康 罗招龙 于 2020-03-25 设计创作，主要内容包括：本发明提供一种建立OPC模型的方法,先利用测试掩模板将测试图形转移至晶圆,在晶圆上形成实际图形并获得测试部分实际图形得到的晶圆数据,然后通过仿真软件模拟所述测试图形获得所述测试图形的仿真数据,再将所述仿真数据和所述晶圆数据进行拟合,采用拟合后的仿真数据建立OPC模型。本发明提供的建立OPC模型的方法,将部分实际图形的晶圆数据与测试图形的整体仿真数据进行拟合,通过拟合数据建立OPC模型,避免花费长时间去获取大量的晶圆数据,缩短建模时间,提高研发效率。(The invention provides a method for establishing an OPC model, which comprises the steps of firstly transferring a test pattern to a wafer by using a test mask plate, forming an actual pattern on the wafer and obtaining wafer data obtained by the actual pattern of a test part, then simulating the test pattern by using simulation software to obtain simulation data of the test pattern, fitting the simulation data and the wafer data, and establishing the OPC model by using the fitted simulation data. According to the method for establishing the OPC model, the wafer data of part of the actual graph is fitted with the overall simulation data of the test graph, the OPC model is established through the fitting data, the phenomenon that a large amount of wafer data are obtained in a long time is avoided, the modeling time is shortened, and the research and development efficiency is improved.)

1. A method for building an OPC model, comprising:

designing a test pattern, and manufacturing a test mask plate according to the test pattern;

transferring the test pattern to a wafer by using the test mask plate, forming an actual pattern on the wafer, and acquiring wafer data obtained by testing part of the actual pattern;

simulating the test pattern through simulation software to obtain simulation data of the test pattern; and the number of the first and second groups,

and fitting the simulation data and the wafer data, and establishing an OPC model by adopting the fitted simulation data.

2. The method of claim 1, wherein fitting the simulation data to the wafer data comprises:

comparing the wafer data of part of the actual graph with the simulation data of the test graph corresponding to part of the actual graph to obtain data deviation; and the number of the first and second groups,

and correcting the simulation data of the test pattern based on the data deviation.

3. The method of claim 1, wherein the simulation data has a data size greater than that of the wafer data.

4. The method of claim 1, wherein the simulation data corresponds to a pattern structure of a type larger than a pattern structure of the wafer data.

5. The method of claim 1, wherein the wafer data of the actual pattern is partially acquired by a scanning electron microscope for measuring the feature size.

6. The method for establishing the OPC model according to any one of claims 1 to 5, wherein after the OPC model is established by using the fitted simulation data, the method further comprises the following steps: and verifying the OPC model.

7. The method for establishing the OPC model according to claim 6, wherein the method for verifying the OPC model comprises:

carrying out OPC model processing on the test pattern to obtain a simulation pattern;

verifying the simulation graph; if the verification fails, fitting the simulation data and the wafer data again to establish an OPC model; and if the verification is passed, determining that the simulation graph is correct.

8. The method for creating OPC models in accordance with claim 7, wherein the verifying the simulation graph comprises:

testing the other part of the actual graph to obtain wafer data which does not participate in the simulation data fitting;

comparing the wafer data which does not participate in the simulation data fitting with the corresponding simulated graphic data; if the comparison result is consistent, the verification is confirmed to be passed; and if the comparison results are inconsistent, confirming that the verification is not passed.

Technical Field

The invention relates to the technical field of integrated circuit optical data processing, in particular to a method for establishing an OPC model.

Background

As integrated circuits continue to evolve, and manufacturing techniques continue to evolve toward smaller dimensions, photolithographic processes have become a major bottleneck limiting the evolution of integrated circuits to smaller feature sizes. In the deep submicron semiconductor manufacturing process, the feature size is far smaller than the wavelength of the light source, due to the nature of the light wave and the problem of the actual projection exposure system, there is a diffraction limit or a serious energy loss caused by the nonlinear filtering of the imaging system, i.e. an Optical Proximity Effect (OPE), which inevitably causes distortion phenomena such as corner rounding, line end recession, line width inconsistency or ripple in the process of transferring the pattern on the reticle to the wafer, and if the distortion phenomena are not eliminated, the distortion phenomena will cause image distortion (distor) on the wafer (wafer), especially for the process stage below 0.18 μm, the distortion effects will be very large, and even cause the failure of the whole manufacturing technology.

In order to compensate for the effect of OPE, a designer needs to directly modify a target pattern based on a design rule and then perform a mask plate making operation. This Correction process is called lithography Proximity Correction (OPC), and for example, a line tail is modified into a pattern such as a hammerhead (hammer head). The graph after the OPC processing is affected by the OPE, a graph close to the originally designed target graph is formed on the wafer, that is, the design target of the OPC is achieved, and the lithographic graph after the photolithography is as close as possible to the target graph actually desired by the user. In the prior art, the wafer data required by the OPC process is obtained manually by using a scanning electron microscope (CDSEM) for feature size measurement, which consumes a lot of time and is inefficient as a whole. Therefore, further improvements to the above methods are needed to address the above drawbacks.

Disclosure of Invention

The invention provides an OPC model and a method for establishing the OPC model, which are used for shortening the time for establishing the OPC model and improving the research and development efficiency.

In order to achieve the above object, the present invention provides a method for establishing an OPC model, comprising:

designing a test pattern, and manufacturing a test mask plate according to the test pattern;

transferring the test pattern to a wafer by using the test mask plate, forming an actual pattern on the wafer, and acquiring wafer data obtained by testing part of the actual pattern;

simulating the test pattern through simulation software to obtain simulation data of the test pattern; and the number of the first and second groups,

and fitting the simulation data and the wafer data, and establishing an OPC model by adopting the fitted simulation data.

Optionally, the process of fitting the simulation data and the wafer data includes:

comparing the wafer data of part of the actual graph with the simulation data of the test graph corresponding to part of the actual graph to obtain comparison deviation; and the number of the first and second groups,

and correcting the simulation data of the test pattern based on the comparison deviation.

Optionally, the data size of the simulation data is larger than the data size of the wafer data.

Optionally, the type of the graph structure corresponding to the simulation data is greater than the type of the graph structure of the wafer data.

Optionally, a scanning electron microscope for measuring the characteristic dimension is used to obtain the wafer data of part of the actual pattern.

Optionally, after the OPC model is established by using the fitted simulation data, the method further includes: and verifying the OPC model.

Optionally, the method for verifying the OPC model includes:

carrying out OPC model processing on the test pattern to obtain a simulation pattern;

verifying the simulation graph;

if the verification fails, fitting the simulation data and the wafer data again to establish an OPC model;

and if the verification is passed, determining that the simulation graph is correct.

Optionally, the method for verifying the simulation graph includes:

testing the other part of the actual graph to obtain wafer data which does not participate in the simulation data fitting;

comparing the wafer data which does not participate in the simulation data fitting with the corresponding simulated graphic data; if the comparison result is consistent, the verification is confirmed to be passed; and if the comparison results are inconsistent, confirming that the verification is not passed.

The invention also provides an OPC model which is established by adopting any one of the methods for establishing the OPC model.

In summary, the present invention provides an OPC model and a method for establishing an OPC model, in which a test mask is used to transfer a test pattern to a wafer, an actual pattern is formed on the wafer, wafer data obtained by the actual pattern of a test portion is obtained, then simulation is performed on the test pattern by a simulation software to obtain simulation data of the test pattern, and then the simulation data is fitted with the wafer data, and the OPC model is established by using the fitted simulation data. According to the method for establishing the OPC model, the wafer data of part of the actual graph is fitted with the overall simulation data of the test graph, the OPC model is established by adopting the fitted simulation data, so that the phenomenon that a large amount of wafer data is obtained in a long time is avoided, the modeling time can be shortened, and the research and development efficiency is improved. And the invention verifies the OPC model after the OPC model is established, thereby ensuring the accuracy of the OPC model.

Drawings

FIG. 1 is a flow chart of a prior art method of building an OPC model;

FIG. 2 is a flowchart of a method for establishing an OPC model according to an embodiment of the present invention;

FIG. 3 is a graph illustrating data fitting in a method for establishing an OPC model according to an embodiment of the present invention;

FIG. 4a is a diagram illustrating a test pattern with a dense line array structure according to an embodiment of the present invention;

FIG. 4b is a diagram illustrating an independent line array structure in a test pattern according to an embodiment of the present invention;

FIG. 4c is a diagram illustrating a test pattern with a periodic line array structure according to an embodiment of the present invention;

FIG. 4d is a diagram illustrating an embodiment of a test pattern in which the pattern structure is an array of independent line terminals;

FIG. 4e is a diagram illustrating an end point of a test pattern having a dense line array structure according to an embodiment of the present invention.

Detailed Description

The method for establishing the OPC model according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and drawings, it being understood, however, that the concepts of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. The drawings are in simplified form and are not to scale, but are provided for convenience and clarity in describing embodiments of the invention.

The terms "first," "second," and the like in the description are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method. Although elements in one drawing may be readily identified as such in other drawings, the present disclosure does not identify each element as being identical to each other in every drawing for clarity of description.

Fig. 1 is a flowchart of a method for creating an OPC model in the prior art, and as shown in fig. 1, the method includes the steps of designing a test pattern, manufacturing a test mask according to the test pattern, performing photolithography on a wafer using the test mask to form an actual pattern on the wafer, obtaining wafer data (such as line width data) of the actual pattern, manufacturing an OPC model according to the wafer data, performing OPC processing on the test pattern, verifying the OPC model, outputting the OPC model when the OPC model passes verification, manufacturing the mask, and re-creating the OPC model according to the wafer data if the OPC model fails verification.

In order to solve the problems, the invention provides a method for establishing an OPC model, which comprises the steps of firstly transferring a test pattern to a wafer by using a test mask plate, forming an actual pattern on the wafer and obtaining wafer data of a part of the actual pattern, simulating the test pattern by using simulation software to obtain simulation data of the test pattern, fitting the simulation data and the wafer data, and establishing the OPC model by using the fitted data. According to the method for establishing the OPC model, the wafer data of part of the actual graph is fitted with the overall simulation data of the test graph, the OPC model is established by adopting the fitted simulation data, so that the phenomenon that a large amount of wafer data is obtained in a long time is avoided, the modeling time is shortened, and the research and development efficiency is improved.

Fig. 2 is a flowchart of a method for establishing an OPC model according to this embodiment, and referring to fig. 2, the method for establishing an OPC model according to the present invention includes:

the method comprises the following steps: designing a test pattern, and manufacturing a test mask plate according to the test pattern;

step two: transferring the test pattern to a wafer by using the test mask plate, forming an actual pattern on the wafer, and acquiring wafer data obtained by testing part of the actual pattern;

step three: simulating the test pattern through simulation software to obtain simulation data of the test pattern; and the number of the first and second groups,

step four: and fitting the simulation data and the wafer data, and establishing an OPC model by adopting the fitted simulation data.

The method for establishing the OPC model according to the present embodiment will be described in more detail with reference to fig. 2, fig. 3, and fig. 4a to 4 e.

First, a first step is executed, a test pattern is designed, a test mask is manufactured according to the test pattern, as shown in fig. 4a to 4e, a pattern structure of the test pattern includes at least one of a dense line array structure (L D), an independent line array structure (L I), a periodic line array structure (TP), an independent line endpoint array structure (T2T L D) and a dense line endpoint array structure (T2T L I), the dense line array structure (L D) and the independent line array structure (L I) are both linear array structures, the periodic line array structure (TP) is a periodically-varying parallel linear array structure, W70 means that a line Width (Width) of a line is 70nm, W80 means that a line Width (Width) of a line is 80nm, and so on, W70S70 means that a line Width (Width) of a line is 70nm and an isolation Width (Spacer) between lines is 70nm, W70S70 means that a line Width (spach) of a line is 70nm and an isolation Width (spaber) between lines is 70nm, W70S is 70nm, and the isolation data amount of the array structures is smaller than that of the other through hole array structures (54 a) and the periodic line array structures (b) of the dense line array structures (54 a) and the periodic line array structures (b) of the wafer array structures are included in the periodic line array structures, and the periodic line array structures of the periodic line array structures (42D) and the periodic line array structures of the periodic line structures of the wafer structures (tpt structures, and the periodic line structures are included in the periodic line structures of the invention, and the periodic line array structures of the wafer array structures, and the periodic line structures of the wafer structures, and the wafer structures of the wafer.

And then, executing a second step, transferring the test pattern to a wafer by using the test mask plate, thereby forming an actual pattern on the wafer, and acquiring wafer data obtained by testing part of the actual pattern. Specifically, first, a mask layer (for example, a photoresist layer) is formed on the wafer; then, a photoetching process is carried out by utilizing the test mask plate to form a patterned mask layer; then, etching the wafer by using the patterned mask layer as an etching mask so as to form the actual pattern on the wafer; and finally, removing the patterned mask layer and acquiring the wafer data of part of the actual graph. Illustratively, the wafer data of a portion of the actual pattern may be acquired by a scanning electron microscope (CDSEM) for feature size measurement.

The simulation software is S-L itho software, and simulation data of all pattern structures on the test pattern can be quickly obtained according to the test pattern through S-L itho software, the S-L itho software is used for developing a photoetching process for manufacturing an integrated circuit, has mature implementation experience, and can obtain simulation data of the test pattern (actual pattern) transferred on a wafer according to the property (such as diffraction and interference) of light and the simulation of an actual projection exposure system, namely, the acquisition of the simulation data considers the pattern distortion caused by Optical Proximity Effect (OPE), and simulates the pattern distortion caused by the OPE through software, so that the obtained simulation data is similar to the wafer data on the test pattern (actual pattern) transferred on the wafer as much as possible.

It should be noted that, in this embodiment, step S02 and step S03 do not have a sequence, that is, forming an actual pattern on a wafer and obtaining wafer data of the actual pattern and obtaining simulation data of the test pattern by simulating the test pattern with simulation software may be performed simultaneously or sequentially, and a specific sequence is not limited.

Then, the fourth step is executed, the simulation data and the wafer data are fitted, an OPC model is established by using the fitted simulation data, wherein the process of fitting the simulation data and the wafer data comprises the steps of firstly, comparing the wafer data of a part of the actual graph with the simulation data of the test graph corresponding to a part of the actual graph to obtain data deviation, and correcting the simulation data of the test graph based on the data deviation, wherein in the embodiment, a lot of time is consumed for obtaining the wafer data of the test graph transferred on the wafer by using a scanning electron microscope (CDSEM) through characteristic dimension measurement, whereas in the embodiment, a lot of time is consumed for obtaining the wafer data of the test graph transferred on the wafer by using simulation data corresponding to a part of the test graph (865) which can be directly and quickly obtained from the test graph through S-L itho software, and then, data deviation is obtained by comparing the wafer data with simulation data corresponding to a part of the test graph transferred on the wafer data which can be considered to be formed on the wafer, and then correcting the simulation data of the test graph based on the data of the wafer data of the test graph, as a non-limiting example, a part of the test graph transferred on the wafer is obtained by using a TP array (735) and a compact wafer structure obtained by comparing the wafer structure obtained by using a representative pattern array (3635) and a compact array (3635) which can be obtained by using a compact array (3635) which can obtain a compact array (L and a compact array of a compact array structure obtained by using a compact array (3648) which can be obtained by using a compact array of a compact array structure (p) which is obtained by using a compact array structure (p) array structure (cd) which is obtained by using a compact array structure (cd) and a compact array structure (cd) which can be obtained by using a compact array structure (3635 and a compact array structure (cd) which can be obtained by using a compact array structure (cd) which can be.

In this embodiment, wafer data corresponding to the dense line array structure (L D) and the independent line array structure (L I) are compared with simulation data to obtain a data deviation, which may be a difference between the wafer data corresponding to the test pattern and the simulation data, and the remaining simulation data are fitted according to the difference, for example, the simulation data obtained by software is more fit to the actually measured wafer data by adding or subtracting the difference, so as to improve the accuracy of the established OPC model to a certain extent.

Fig. 3 is a graph of data fitting in the method of establishing an OPC model according to the present embodiment, in which the abscissa is a space pitch (Spacer) and the ordinate is a line Width (Width), as shown in fig. 3, line widths of pattern units W90S90, W90S100, …, W90S1000, and W90S2000 in a test pattern are simulated by using S-L ith software, so as to obtain simulation data, line Width data (wafer data) of pattern units W90S90 and W90S2000 in an actual pattern on a wafer is measured and obtained, simulation data corresponding to W90S90 and W90S2000 is compared with wafer data, so as to obtain a data deviation, for example, a difference between corresponding simulation data and wafer data, and then all simulation data are corrected according to the difference, for example, simulation data of pattern units W90S90, W90S100, …, W90S1000, and W90S2000 are integrated with simulation data, so as to obtain corrected simulation data, and then, after a simulation data is created according to the corrected simulation data, a simulation data is created, wherein the simulation data of a pattern unit W90S90, a simulation data of a pattern unit W90S90, a simulation line Width array, a simulation data of a simulation structure (TP-tr array, a simulation data of a simulation line array, a simulation structure, a simulation line Width array, a simulation line Width data of a simulation structure (TP array, a simulation structure, a simulation line Width data of a simulation structure of a wafer structure (TP-tr array, a simulation line structure of a wafer array, a simulation line array of a wafer structure of a wafer array (TP array of a wafer structure (TP array of a wafer structure (T-tr array, a wafer array of a wafer array, a wafer structure of a wafer array of a wafer.