Synchronous circuit, synchronous method thereof and display device

文档序号：1339606 发布日期：2020-07-17 浏览：11次中文

阅读说明：本技术 一种同步电路及其同步方法、显示装置 (Synchronous circuit, synchronous method thereof and display device ) 是由唐大伟黄继景杨志明吴琼卢尧于 2020-04-15 设计创作，主要内容包括：一种同步电路及其同步方法、显示装置,所述同步电路包括：输入相位延迟子电路、第1至第N+1个数据帧头累加子电路、判决子电路,所述输入相位延迟子电路设置为对第二数据端输入的第二信号进行相位延迟后通过所述N个输出端输出延迟信号；所述第K个数据帧头累加子电路设置为：当所述第K个数据帧头累加子电路的输入端的输入数据与第一数据相等时,进行一次计数,通过所述输出端输出第K个计数结果,计数次数到达N次后重新开始计数；所述判决子电路设置为,将输入的第1至第N个计数结果分别与第N+1个计数结果进行比较,当第n个计数结果与第N+1个计数结果相等时,将通过节点A<Sub>n</Sub>输入的所述延迟信号通过第一输出端输出作为同步信号。(A synchronization circuit, a synchronization method thereof and a display device are provided, wherein the synchronization circuit comprises: the input phase delay sub-circuit is set to output delay signals through the N output ends after carrying out phase delay on a second signal input by a second data end; the Kth data frame header accumulation sub-circuit is set as follows: when the input data of the input end of the Kth data frame header accumulation sub-circuit is equal to the first data, counting once, outputting a Kth counting result through the output end, and restarting counting after the counting times reach N times; the decision sub-circuit is set to compare the 1 st to Nth counting results with the (N + 1) th counting result respectively, and when the N-th counting result is equal to the (N + 1) th counting resultWill pass through node A n The input delay signal is output as a synchronization signal through a first output terminal.)

1. A synchronization circuit, comprising: inputting a phase delay sub-circuit, a1 st to an N +1 th data frame header accumulation sub-circuit and a decision sub-circuit, wherein N is more than or equal to 2, wherein:

the first input terminal of the input phase delay sub-circuit is coupled to the second data terminal, the input phase delay sub-circuit includes N output terminals, the N output terminals are respectively coupled to the node A_mM is 1 to N; the input phase delay sub-circuit is configured to: after phase delay is carried out on a second signal input by a second data end, delay signals are output through the N output ends, and the phase delay amount of the delay signals of different output ends is different;

an input terminal of the Kth data frame header accumulation sub-circuit is coupled to the node A_KK is 1 to N +1, and the output end of the Kth data frame header accumulation sub-circuit is coupled to the node B_K(ii) a The node A_N+1Coupled to the first data terminal; the Kth data frame header accumulation sub-circuit is set as follows: when the input data of the input end of the Kth data frame header accumulation sub-circuit is equal to the first data, counting once, outputting a Kth counting result through the output end, and restarting counting after the counting times reach N times;

the decision sub-circuit is coupled to the node A_KAnd the node B_KThe decision sub-circuit is configured to compare the 1 st to nth counting results with the N +1 th counting result respectively, and when the nth counting result is equal to the N +1 th counting result, the node A will be passed_nSaid delaying of the inputThe late signal is output as a synchronization signal through a first output terminal.

2. The synchronization circuit of claim 1, wherein the decision sub-circuit comprises a1 st to nth data output decision sub-circuit, wherein:

the first input end of the jth data output decision sub-circuit is coupled to the node B_jThe second input terminal is coupled to the node B_N+1The third input terminal is coupled to the node A_jThe fourth input end is coupled with the first output end of the j +1 th data output judgment sub-circuit, and j is 1 to N-1; the first input terminal of the Nth data output decision sub-circuit is coupled to the node B_NThe second input terminal is coupled to the node B_N+1A third input terminal coupled to the node A_NThe fourth input terminal is coupled to the first data terminal; the data output decision sub-circuit is arranged to: and comparing the signal of the first input end of the data output judgment sub-circuit with the signal of the second input end of the data output judgment sub-circuit, and selecting the signal of the third input end to be output through the first output end when the two are the same.

3. The synchronous circuit of claim 1, wherein the input phase delay sub-circuit comprises N sets of D flip-flops, wherein the input terminal of the 1 st set of D flip-flops is the first input terminal of the input phase delay sub-circuit, wherein the input terminal of the m-th set of D flip-flops is coupled to the output terminal of the m-1 st set of D flip-flops, wherein the clock input terminal of each D flip-flop is coupled to the first clock signal terminal, and wherein the N output terminals of the N sets of D flip-flops are the N output terminals of the input phase delay sub-circuit.

4. The synchronization circuit of claim 1, wherein the Kth DATA FRAG ACCUMULATION SUB-circuit comprises: a Kth accumulator, a Kth frame header memory, a 2 Kth-1 gating device, a 2 Kth gating device and an N + K group of D triggering devices, wherein,

the input end of the K frame header storage is the input end of the K data frame header accumulation sub-circuit, and the output end of the (N + K) th group D trigger is the output end of the K data frame header accumulation sub-circuit;

the output end of the Kth frame header memory is coupled to the second input end of the 2K-1 gate, the first input end of the 2K-1 gate is coupled to a first voltage end, the output end of the 2K-1 gate is coupled to the enable end of the N + K D group flip-flop, the clock input end of the N + K D group flip-flop is coupled to a first clock signal end, the input end of the N + K D group flip-flop is coupled to the output end of the 2K gate, the first input end of the 2K gate is coupled to a second voltage end, the second input end of the 2K gate is coupled to the output end of the K accumulator, the second input end of the K accumulator is coupled to a first voltage end, and the first input end of the K accumulator is coupled to the gate end of the 2K-1 gate, the gate end of the 2K gate, And the output end of the N + K group D trigger.

5. The synchronous circuit of claim 2, wherein the mth data output decision sub-circuit comprises an mth comparator, a 2N + m +1D flip-flop, and a 2N + m +2 gate, wherein:

the output end of the mth comparator is coupled to the input end of the 2N + m +1D trigger, the clock input end of the 2N + m +1D trigger is coupled to a first clock signal end, and the output end of the 2N + m +1D trigger is coupled to the gating end of the 2N + m +2 gating device;

a first input end of the mth comparator is a first input end of the mth data output decision sub-circuit, a second input end of the mth comparator is a second input end of the mth data output decision sub-circuit, a first input end of the 2N + m +2 gate is a third input end of the mth data output decision sub-circuit, a second input end of the 2N + m +2 gate is a fourth input end of the mth data output decision sub-circuit, and an output end of the 2N + m +2 gate is a first output end of the mth data output decision sub-circuit.

6. The synchronization circuit of claim 1,

the decision sub-circuit is also set to output comparison results obtained by comparing the 1 st to nth counting results with the N +1 st counting results through the 2 nd to N +1 th output ends respectively;

the synchronization circuit further includes a data output buffer sub-circuit, a first input terminal of the data output buffer sub-circuit is coupled to a first output terminal of the decision sub-circuit, a second input terminal of the data output buffer sub-circuit is coupled to the first data terminal, a 3 rd input terminal to an N +2 th input terminal of the data output buffer sub-circuit are coupled to a 2 nd to an N +1 th output terminal of the decision sub-circuit, respectively, a clock input terminal of the data output buffer sub-circuit is coupled to a second clock signal terminal, and the data output buffer sub-circuit is configured to: buffering signals input from the first input terminal and the second input terminal, converting the signal input from the first input terminal to a preset clock domain and then outputting the signal through a first output terminal, converting the signal input from the second input terminal to the preset clock domain and then outputting the signal through a second output terminal, and determining whether synchronization is completed according to the comparison result input by the decision sub-circuit and outputting the enable signal through a third output terminal.

7. The synchronization circuit of claim 6, wherein the data output buffer sub-circuit comprises a 3N + 2D flip-flop, a 3N + 3D flip-flop, a 3N +4D flip-flop, a 3N +3 strobe, through a 4N strobe, wherein,

the clock input ends of the 3N + 2D group of triggers, the 3N + 3D group of triggers and the 3N +4D group of triggers are coupled with a second clock signal end;

the first input ends of the 3N +3 th gate to the 4N gate are coupled with a first voltage end;

the output end of the 3N + k gate is coupled to the second input end of the 3N + k +1 gate, k is 3 to N-1, and the output end of the 4N gate is coupled to the position end of the 3N +4D trigger;

an input end of the 3N +2 group D flip-flop is a first input end of the data output cache sub-circuit, an output end of the 3N +2 group D flip-flop is a first output end of the data output cache sub-circuit, an input end of the 3N +3 group D flip-flop is a second input end of the data output cache sub-circuit, an output end of the 3N +3 group D flip-flop is a second output end of the data output cache sub-circuit, and an output end of the 3N +4 group D flip-flop is a third output end of the data output cache sub-circuit; the first input end of the 3N +3 th gate, the gate ends from the 3N +3 th gate to the 4N th gate, and the input end of the 3N +4D flip-flop are the 3 rd input end to the N +2 th input end of the data output buffer sub-circuit, respectively.

8. The synchronization circuit according to claim 6 or 7,

the input phase delay sub-circuit comprises N groups of D triggers, wherein the input end of the 1 st group of D triggers is the first input end of the input phase delay sub-circuit, the input end of the mth group of D triggers is coupled with the output end of the m-1 st group of D triggers, the clock input end of each D trigger is coupled with the first clock signal end, and the N output ends of the N groups of D triggers are N output ends of the input phase delay sub-circuit;

the Kth data frame header accumulation sub-circuit comprises: a Kth accumulator, a Kth frame header memory, a 2 Kth-1 gating device, a 2 Kth gating device and an N + K group of D triggers, wherein K is 1 to N +1,

the decision sub-circuit comprises 1 st to Nth data output decision sub-circuits, and the first input end of the jth data output decision sub-circuit is coupled with the node B_jThe second input terminal is coupled to the node B_N+1The third input terminal is coupled to the node A_jThe fourth input end is coupled with the first output end of the j +1 th data output judgment sub-circuit, and j is 1 to N-1; the first input terminal of the Nth data output decision sub-circuit is coupled to the node B_NThe second input terminal is coupled to the node B_N+1A third input terminal coupled to the node A_NThe fourth input terminal is coupled to the first data terminal; the data output decision sub-circuit is arranged to: comparing the signal of the first input end of the data output judgment sub-circuit with the signal of the second input end of the data output judgment sub-circuit, and selecting the signal of the third input end to be output through the first output end when the two are the same;

the mth data output decision sub-circuit comprises an mth comparator, a 2N + m +1D trigger and a 2N + m +2 gate, wherein:

9. The synchronization circuit of any of claims 1 to 7, wherein N is 4, and an output signal of the m-th output terminal of the input phase delay sub-circuit is phase-delayed by 90 x m degrees with respect to the second signal.

10. The synchronous circuit according to any one of claims 1 to 7, wherein a frequency of the first clock signal at the first clock signal terminal is N times a frequency of the second clock signal at the second clock signal terminal.

11. A display device, comprising: a display substrate, a readout circuit and a synchronization circuit according to any of claims 1-10, wherein the readout circuit is coupled to the display substrate, the synchronization circuit is coupled to the readout circuit, and the synchronization circuit is configured to receive a data signal output by the readout circuit, synchronize the data signal and output the synchronized data signal to the readout circuit.

12. A synchronization method for a synchronization circuit, applied in a synchronization circuit according to any of claims 1 to 10, comprising:

the input phase delay sub-circuit respectively outputs delay signals to the 1 st to Nth data frame header accumulation sub-circuits through the N output ends after performing phase delay on a second signal input by a second data end, and respectively outputs the delay signals to the first to Nth data frame header accumulation sub-circuits, and the phase delay amount of output signals of different output ends is different;

when the input delay signal is equal to the first data, each of the 1 st to nth data frame header accumulation sub-circuits counts once, respectively outputs the 1 st to nth counting results to the decision sub-circuit, and resets and recounts after the counting times reach N times; the (N + 1) th data frame header accumulation sub-circuit counts once when the first signal of the first data end is equal to the first data and outputs an (N + 1) th counting result to the decision sub-circuit;

the decision sub-circuit compares the 1 st to nth counting results with the (N + 1) th counting result, and outputs the delay signal input to the nth data frame header accumulation sub-circuit as a synchronization signal when the nth counting result is equal to the (N + 1) th counting result.

Technical Field

The present disclosure relates to display technologies, and more particularly, to a synchronization circuit, a synchronization method thereof, and a display device.

Background

In a high-resolution PIN (photodiode) panel, multiple pieces of readout ic (readout circuit) are used, and data of the multiple pieces of readout ic may have time delay, which causes non-uniformity of pixels, and needs to be improved.

Disclosure of Invention

The embodiment of the application provides a synchronization circuit, a synchronization method thereof and a display device, which can eliminate time delay and realize signal synchronization.

In one aspect, an embodiment of the present application provides a synchronization circuit, including: inputting a phase delay sub-circuit, a1 st to an N +1 th data frame header accumulation sub-circuit and a decision sub-circuit, wherein N is more than or equal to 2, wherein:

the first input terminal of the input phase delay sub-circuit is coupled to the second data terminal, the input phase delay sub-circuit includes N output terminals, the N output terminals are respectively coupled to the node A_mM is 1 to N; the input phase delay sub-circuit is set to output delay signals through the N output ends after phase delay is carried out on a second signal input by a second data end, and the phase delay amount of the delay signals of different output ends is different;

the decision sub-circuit is coupled to the node A_KAnd the node B_KThe decision sub-circuit is configured to compare the 1 st to nth counting results with the N +1 th counting result respectively, and when the nth counting result is equal to the N +1 th counting result, the node A will be passed_nThe input delay signal is output as a synchronization signal through a first output terminal. N is one of 1 to N.

In an exemplary embodiment, the decision sub-circuit includes a1 st to nth data output decision sub-circuit, wherein:

In an exemplary embodiment, the input phase delay sub-circuit includes N sets of D flip-flops, the input terminal of the 1 st set of D flip-flops is the first input terminal of the input phase delay sub-circuit, the input terminal of the m-th set of D flip-flops is coupled to the output terminal of the m-1 st set of D flip-flops, the clock input terminal of each D flip-flop is coupled to the first clock signal terminal, and the N output terminals of the N sets of D flip-flops are the N output terminals of the input phase delay sub-circuit.

In an exemplary embodiment, the kth data frame header accumulation sub-circuit includes: a Kth accumulator, a Kth frame header memory, a 2 Kth-1 gating device, a 2 Kth gating device and an N + K group of D triggering devices, wherein,

In an exemplary embodiment, the mth data output decision sub-circuit includes an mth comparator, a 2N + m +1D flip-flop, and a 2N + m +2 gate, wherein:

In an exemplary embodiment, the decision sub-circuit is further configured to output comparison results obtained by comparing the 1 st to nth count results with the N +1 st count results through the 2 nd to N +1 th output terminals, respectively;

In an exemplary embodiment, the data output buffer sub-circuit includes a 3N + 2D group flip-flop, a 3N + 3D group flip-flop, a 3N +4D group flip-flop, a 3N +3 th gate through a 4N gate, wherein,

the clock input ends of the 3N + 2D group of triggers, the 3N + 3D group of triggers and the 3N +4D group of triggers are coupled with a second clock signal end;

the first input ends of the 3N +3 th gate to the 4N gate are coupled with a first voltage end;

the output end of the 3N + k gate is coupled to the second input end of the 3N + k +1 gate, k is 3 to N-1, and the output end of the 4N gate is coupled to the position end of the 3N +4D trigger;

In an exemplary embodiment, the input phase delay sub-circuit includes N sets of D flip-flops, where the input terminal of the 1 st set of D flip-flops is the first input terminal of the input phase delay sub-circuit, the input terminal of the m-th set of D flip-flops is coupled to the output terminal of the m-1 st set of D flip-flops, the clock input terminal of each D flip-flop is coupled to the first clock signal terminal, and the N output terminals of the N sets of D flip-flops are the N output terminals of the input phase delay sub-circuit;

the mth data output decision sub-circuit comprises an mth comparator, a 2N + m +1D trigger and a 2N + m +2 gate, wherein:

In an exemplary embodiment, N is 4, and the output signal of the mth output terminal of the input phase delay sub-circuit is phase-delayed by 90 × m degrees with respect to the second signal.

In an exemplary embodiment, a frequency of the first clock signal terminal is N times a frequency of the second clock signal terminal.

In another aspect, an embodiment of the present application provides a display device, including: the display device comprises the synchronous circuit, a display substrate and a reading circuit, wherein the reading circuit is coupled with the display substrate, the synchronous circuit is coupled with the reading circuit, and the synchronous circuit is configured to receive a data signal output by the reading circuit, synchronize the data signal and output the data signal to the reading circuit.

In another aspect, an embodiment of the present application provides a synchronization method for a synchronization circuit, where the synchronization method is applied to the synchronization circuit, and the method includes:

Compared with the related art, the synchronization circuit provided by the embodiment of the application comprises: the input phase delay sub-circuit 1, the 1 st to the (N + 1) th data frame header accumulation sub-circuit, and the decision sub-circuit, through carrying on a plurality of phase delays of different delay quantity to a signal, and through counting the frame header data, find out the delay signal synchronous with another signal from it, thus realize the signal synchronization.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.

Fig. 1 is a schematic structural diagram of a synchronization circuit according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a synchronous circuit according to another embodiment;

FIG. 3 is a schematic diagram of a synchronous circuit according to yet another embodiment;

FIG. 4 is a schematic diagram of a synchronous circuit according to yet another embodiment;

FIG. 5 is a schematic diagram of an input phase delay sub-circuit according to one embodiment;

FIG. 6 is a schematic diagram of a header accumulation sub-circuit according to an embodiment;

FIG. 7 is a schematic diagram of a data output decision sub-circuit according to an embodiment;

FIG. 8 is a schematic diagram of a data output buffer sub-circuit according to an embodiment;

fig. 9 is a schematic diagram of a synchronization circuit according to an embodiment (N-4);

FIG. 10 is a simulation diagram of an input phase delay sub-circuit according to an embodiment;

FIG. 11 is a schematic diagram illustrating an embodiment of a data frame header accumulation sub-circuit and a data output decision sub-circuit;

FIG. 12 is a schematic diagram of two signals with a 90 degree delay according to one embodiment;

FIG. 13 is a diagram of two signals with a 180 degree delay according to one embodiment;

FIG. 14 is a schematic diagram of two signals with a 270 degree delay according to an embodiment;

FIG. 15 is a signal diagram illustrating two signals with a 360 degree delay according to an embodiment;

FIG. 16 is a flow chart of a synchronization method of a synchronization circuit according to an embodiment of the present application;

fig. 17 is a schematic view of a display device according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled," and the like, are not restricted to physical or mechanical couplings, but may include electrical connections, whether direct or indirect.

The reason why the delay of the plurality of readout ics occurs is mainly that when the sampling rate of the readout ics is 200MHz, the difference of the PCB (printed circuit Board) wiring and the wiring delay inside the processor chip are not negligible, which causes the data phases of the plurality of readout ics to be inconsistent. In the embodiment of the application, a synchronization circuit and a driving method thereof are provided, and a display device synchronizes a plurality of readout ics, eliminates data delay among the plurality of readout ics, and solves the problem of pixel imbalance caused by the non-synchronization of the readout ics.

Fig. 1 is a schematic structural diagram of a synchronization circuit according to an embodiment of the present disclosure. As shown in fig. 1, an embodiment of the present application provides a synchronization circuit, which may include: an input phase delay sub-circuit 1, a1 st to an N +1 th data frame header accumulation sub-circuit 2₁To 2_N+1And, a decision sub-circuit 3, N being greater than or equal to 2, wherein:

in this embodiment, the first input terminal 1-i1 of the input phase delay sub-circuit 1 is coupled to the second data terminal i _ din1, the input phase delay sub-circuit 1 includes N output terminals 1-o 1-1-oN, the N output terminals are coupled to the node A respectively₁～A_NI.e. the output 1-om is coupled to the node A_mM is 1 to N; the input phase delay sub-circuit 1 is configured to perform phase delay on a second signal input by a second data terminal i _ din1 and output the second signal through the N output terminals, where phase delay amounts of output signals of different output terminals are different;

the Kth data frame header accumulation sub-circuit 2_KInput terminal 2 of_K-i1 is coupled to node A_KThe Kth data frame header accumulation sub-circuit 2_KOutput terminal 2 of_K-o1 is coupled to node B_K(ii) a K is 1 to N +1, node A_N+1Is coupled to the first data terminal i _ din 0; header accumulation subcircuit 2 of the data frame_KThe method comprises the following steps: when the header of the data frame adds sub-circuit 2_KInput terminal 2 of_KI1, when the input data is equal to the first data, a count is made, passing through the header accumulation subcircuit 2_KOutput terminal 2 of_K-o1 outputs the counting result, and counting is restarted after the counting times reach N times; first, theThe data is, for example, frame header data of the second signal of the second data end or frame header data of the first signal of the first data end. When N is 4, the counting method is, for example: the initial value of the count is 0, when the input data of the input end of the data frame header accumulation sub-circuit is equal to the first data, the count is carried out once, namely the count value is added with 1, and when the count reaches 3, the count is cleared and the count is restarted.

The decision sub-circuit 3 is coupled to the node A_KAnd the node B_KThe decision sub-circuit 3 is configured to compare the 1 st to nth counting results with the N +1 th counting result, respectively, and when the nth counting result is equal to the N +1 th counting result, the node a will be passed_nThe input delay signal is output as a synchronization signal through a first output terminal.

When the first signal and the second signal need to be synchronized, the first signal is used as a reference and coupled to the first data terminal i _ din0, and the second signal is coupled to the second data terminal i _ din1, so that synchronization is achieved.

In an exemplary embodiment, N is, for example, 2ⁿAnd n is 1 or more. For example, N is 4 or 8. In other embodiments, N may be other values.

The synchronous circuit that this application embodiment provided includes: an input phase delay sub-circuit 1, a1 st to an N +1 th data frame header accumulation sub-circuit 2₁To 2_N+1And a decision sub-circuit for performing signal synchronization by performing a plurality of phase delays of different delay amounts on one signal and by counting frame header data to find a delayed signal synchronized with another signal therefrom.

Fig. 2 is a schematic structural diagram of a decision sub-circuit 3 according to an embodiment. As shown in fig. 2, the decision sub-circuit 3 includes 1 st to nth data output decision sub-circuits 3₁To 3_NWherein:

the jth data output decision sub-circuit 3_jFirst input terminal 3_j-i1 coupling node B_jSecond input terminal 3_j-i2 coupling node B_N+1A third input terminal 3_j-i3 coupling node A_jFourth input terminal 3_j-i4 is coupled to the j +1 th data output decision sub-circuit 3_j+1First output terminal 3_j-o1, j is 1 to N-1; first input terminal 3 of the Nth data output decision sub-circuit_N-i1 coupling node B_NSecond input terminal 3_N-i2 coupling node B_N+1A third input terminal 3_N-i3 is coupled to the node A_NFourth input terminal 3_N-i4 is coupled to the first data terminal i _ din 0; the data output decision sub-circuit is arranged to: and comparing the signal of the first input end of the data output judgment sub-circuit with the signal of the second input end of the data output judgment sub-circuit, and selecting one of the signals of the third input end and the fourth input end to output through the first output end according to the comparison result. Wherein, when the signal of the first input end is the same as the signal of the second input end, the signal of the third input end is output through the first output end; and when the signal of the first input end is different from the signal of the second input end, the signal of the fourth input end is output through the first output end.

Fig. 2 is an exemplary structure of a decision sub-circuit, and those skilled in the art will readily understand that the implementation of the sub-circuit is not limited thereto as long as the function thereof can be realized.

Fig. 3 is a schematic structural diagram of a synchronization circuit according to another embodiment. As shown in FIG. 3, the synchronization circuit provided in this embodiment may include an input phase delay sub-circuit 1, a1 st to an N +1 th data frame header accumulation sub-circuit 2₁To 2_N+1And a decision sub-circuit 3, N being greater than or equal to 2. The coupling manner of each sub-circuit may be the coupling manner of the embodiment shown in fig. 1, and is not described again. In this embodiment, the decision sub-circuit 3 may be further configured to output the comparison result.

The decision sub-circuit 3 is further configured to output comparison results obtained by comparing the 1 st to nth counting results with the N +1 st counting results through the 2 nd to N +1 th output ends respectively;

as shown in fig. 3, in this embodiment, the synchronization circuit may further include a data output buffer sub-circuit 4, a first input terminal 4-i1 of the data output buffer sub-circuit 4 is coupled to the first output terminal of the decision sub-circuit, a second input terminal 4-i2 of the data output buffer sub-circuit 4 is coupled to the first data terminal i _ din0, a 3 rd input terminal 4-i3 to an N +2 th input terminal 4-i (N +2) of the data output buffer sub-circuit 4 are respectively coupled to the 2 nd output terminal to the N +1 th output terminal of the decision sub-circuit, a clock input terminal of the data output buffer sub-circuit 4 is coupled to the second clock signal terminal i _ clk, and the data output buffer sub-circuit 4 is configured to: buffering signals input from the first input terminal 4-i1 and the second input terminal 4-i2, converting the signals input from the first input terminal 4-i1 into a preset clock domain and outputting the signals through the first output terminal 4-o1, converting the signals input from the second input terminal 4-i2 into the preset clock domain and outputting the signals through the second output terminal 4-o2, and determining an enable signal whether synchronization is completed according to the comparison result input from the decision sub-circuit and outputting the enable signal through the third output terminal 4-o 3.

Fig. 4 is a schematic structural diagram of a synchronization circuit according to another embodiment. In this embodiment, the synchronization circuit may include an input phase delay sub-circuit 1, and a1 st to N +1 th data frame header accumulation sub-circuit 2₁To 2_N+1And, a decision sub-circuit 3, the decision sub-circuit 3 including the 1 st to Nth data output decision sub-circuit 3₁To 3_N。

As shown in fig. 4, in this embodiment, the synchronization circuit may further include a data output buffer sub-circuit 4, and a first input terminal 4-i1 of the data output buffer sub-circuit 4 is coupled to the 1 st data output decision sub-circuit 3₁First output terminal 3₁O1 (i.e. the first output terminal of the decision sub-circuit 3), the second input terminal 4-i2 of the data output buffer sub-circuit 4 is coupled to the first data terminal i _ din0, and the 3 rd input terminal 4-i3 to the N +2 th input terminal 4-i (N +2) of the data output buffer sub-circuit 4 are coupled to the second output terminal 3 of the N data decision sub-circuits respectively₁-o2 to 3_NO2 (i.e. 2 nd output to N +1 th output of decision sub-circuit 3), the data output buffer sub-circuit 4 being arranged to: buffering inputs from the first input terminal 4-i1 and the second input terminal 4-i2A signal inputted from the first input terminal 4-i1 is converted into a preset clock domain and outputted through a first output terminal 4-o1, a signal inputted from the second input terminal 4-i2 is converted into the preset clock domain and outputted through a second output terminal 4-o2, and an enable signal determining whether synchronization is completed according to the comparison result inputted from the N data decision sub-circuits and outputted through a third output terminal 4-o 3.

Fig. 5 is a schematic diagram of an input phase delay sub-circuit in a synchronous circuit according to an embodiment, in the synchronous circuit according to the embodiment, the input phase delay sub-circuit 1 may include N sets of D flip-flops RT L _ REG _1 to RT L _ REG _ N, each set of D flip-flops may include an input terminal D, an output terminal Q, and a clock input terminal C, an input terminal D of a1 st set of D flip-flops RT L _ REG _1 is a first input terminal 1-i1 of the input phase delay sub-circuit 1, an input terminal D _ m of an m-th set of D flip-flops is coupled to an output terminal Q _ m-1 of an m-1 th set of D flip-flops, a clock input terminal C _ m of an m-th set of D flip-flops is coupled to a first clock signal terminal i _ 200, and N output terminals Q _1 to Q _ N of the N sets of the N D flip-flops are N output terminals 1-o1 to 1-oN of the input phase delay sub-circuit.

In this embodiment, each group of D flip-flops includes a plurality of D flip-flops, the number of the D flip-flops in each group is related to the bit number of the second signal at the second data end, for example, when the second signal is 16 bits, each group of D flip-flops includes 16D flip-flops, and the coupling manner of each D flip-flop in the group of D flip-flops is the same. Each D flip-flop comprises a clock input C, an input D and an output Q, the D flip-flop being triggered, for example, by a rising edge, the value of the input D being applied to the output Q when the signal input at the clock input C of the D flip-flop is on the rising edge, and the value of the output Q being maintained when the signal is not on the rising edge.

Fig. 5 is an exemplary structure of an input phase delay sub-circuit, and those skilled in the art will readily understand that the implementation of the sub-circuit is not limited thereto as long as the function thereof can be realized.

Fig. 6 is a schematic structural diagram of a header accumulation sub-circuit in a synchronization circuit according to an embodiment. As shown in fig. 6The Kth data frame header accumulation sub-circuit 2_KThe method can comprise the following steps:

a Kth accumulator RT L _ ADD _ K, a Kth frame header RT L _ ROM _ K, a 2K-1 gate RT L _ MUX _2K-1, a 2K gate RT L _ MUX _2K, and an N + K group D flip-flops RT L _ REG _ N + K, wherein,

the input end of the Kth frame header memory RT L _ ROM _ K is the input end 2 of the Kth data frame header accumulation sub-circuit_KI1, wherein the output Q _ N + K of the N + K group D flip-flop RT L _ REG _ N + K is the Kth data frame header accumulation sub-circuit 2_KOutput terminal 2 of_K-o1；

An output of the Kth frame header RT L _ ROM _ K is coupled to the second input I1_2K-1 of the 2K-1 gate RT L _ MUX _2K-1, a first input I0_2K-1 of the 2K-1 gate RT L0 _ MUX _2K-1 is coupled to the first voltage terminal VDD, an output O _2K-1 of the 2K-1 gate RT L _ MUX _2K-1 is coupled to an enable terminal CE _ N + K of the N + K set of D flip-flops RT L _ REG _ N + K, a clock input C _ N + K of the N + K set of D flip-flops RT L _ REG _ N + K is coupled to the first clock signal terminal I _ clk200, a clock input C _ N + K of the N + K set of D flip-flops RT L _ 2_ REG _ K + K is coupled to the first clock signal terminal I _ N _ CLK200, an output of the N + K set of N flip-D flip-flops RT L _ N + K4 _ N + K is coupled to the first clock signal terminal I _ N + K of the 2K gate RT 3527, a second input RT 27K _ MUX, a second input RT 35K _ K _ MUX 75, a second gate RT 27, a second input RT 3_ K _ MUX _ K _ MUX _ K _ MUX _ K _ MUX _ K _ MUX _ K _ MUX _ K _ MUX _ CLK _ K _ MUX _ CLK _ MUX _ K _ MUX _ K _ CLK _ MUX _ K _ MUX _ CLK _ MUX _ K _ CLK _ MUX _ CLK _.

In this embodiment, the N + K-th group of D flip-flops are similar to the aforementioned 1 st to N-th groups of D flip-flops and include a plurality of D flip-flops, the number of the D flip-flops is related to the bit number of the second signal at the second data end, for example, when the second signal is 16 bits, the N + K-th group of D flip-flops includes 16D flip-flops, and the coupling manner of each D flip-flop in the group of D flip-flops is the same. Each D flip-flop comprises a clock input C, an input D and an output Q, said D flip-flop being triggered, for example, by a rising edge, the value of the input D being applied to the output Q when the signal input by the clock input C is on a rising edge, and the value of the output Q being maintained when it is not on a rising edge. The number of flip-flops included in each subsequent group of D flip-flops and the coupling manner of the D flip-flops in the same group are similar, and are not described again.

In this embodiment, when the gate terminal S _2K-1 of the gate RT L _ MUX _2K-1 is 000, the signal output of the second input terminal I1_2K-1 is selected, when the gate terminal S _2K-1 is 011, the signal output of the first input terminal I0_2K-1 is selected, when the gate terminal S _2K of the gate RT L _ MUX _2K is 000, the signal output of the second input terminal I1_2K is selected, and when the gate terminal S _2K is 011, the signal output of the first input terminal I0_2K is selected.

Fig. 6 shows an exemplary structure of a header accumulation sub-circuit, and those skilled in the art will readily understand that the implementation manner of the sub-circuit is not limited thereto as long as the function thereof can be achieved.

Fig. 7 is a schematic structural diagram of a data output decision sub-circuit in the synchronization circuit according to an embodiment. As shown in fig. 7, the mth data output decision sub-circuit 3_mMay include an mth comparator RT L _ EQ _ m, a 2N + m +1D flip-flop RT L _ REQ _2N + m +1, and a 2N + m +2 gate RT L _ MUX _2N + m +2, wherein:

an output end Em _ O of the mth comparator RT L _ EQ _ m is coupled to an input end D _2N + m +1 of the 2N + m +1D flip-flop RT L _ REQ _2N + m +1, a clock input end C _2N + m +1 of the 2N + m +1D flip-flop RT L _ REQ _2N + m +1 is coupled to a first clock signal end i _ clk200, and an output end Q _2N + m +1 of the 2N + m +1D flip-flop RT L _ REQ _2N + m +1 is coupled to a 2N + m +2 gate RT L _ MUX _2N + m +2 gate end S _2N + m + 2;

the mth comparator RT L _ EQ _ m has a first input end Em _ I0 for the mth data output decision sub-circuit 3_mFirst input terminal 3_m-I1, the second input Em _ I1 of the mth comparator RT L _ EQ _ m determining sub-circuit 3 for the mth data output_mSecond input terminal 3_m-I2, the first input I0_2N + m +2 of the 2N + m +1 th gate RT L _ MUX _2N + m +1 being the m-th numberAccording to the output decision sub-circuit 3_mThird input terminal 3_m-I3, the second input I1_2N + m +2 of the 2N + m + 2-th gate RT L _ MUX _2N + m +2 being the m-th data output decision sub-circuit 3_mFourth input terminal 3_m-i4, the output O _2N + m +2 of the 2N + m-th gate RT L _ MUX _2N + m +2 being the m-th data output decision sub-circuit 3_mFirst output terminal 3_m-o 1. In this embodiment, when the gate terminal S _2N + m +2 of the gate S _2N + m +2 is 0, the signal output of the second input terminal I1_2N + m +2 is selected, and when the gate terminal S _2K-1 is 1, the signal output of the first input terminal I0_2N + m +2 is selected. Of course, this is merely an example and other types of gates may be selected.

In another embodiment, the output Q _2N + m +1 of the 2N + m +1D flip-flop RT L _ REQ _2N + m +1 is the m data output decision sub-circuit 3_mSecond output terminal 3_m-o2。

Fig. 7 is an exemplary structure of a data output decision sub-circuit, and those skilled in the art will readily understand that the implementation of the sub-circuit is not limited thereto as long as the function thereof can be realized.

Fig. 8 is a schematic diagram of a data output buffer sub-circuit in the synchronization circuit according to an embodiment, as shown in fig. 8, the data output buffer sub-circuit 4 includes a 3N + 2D flip-flop RT L _ REG _3N +2, a 3N + 3D flip-flop RT L _ REG _3N +3, a 3N +4D flip-flop RT L _ REG _ SYNC, a 3N +3 gate RT L _ MUX _3N +3 to a 4N gate RT L _ MUX _4N, wherein,

the clock input terminal C _3N +2 of the 3N + 2D flip-flop RT L _ REG _3N +2, the clock input terminal C _3N +3 of the 3N + 3D flip-flop RT L _ REG _3N +3, and the clock input terminal C of the 3N +4D flip-flop RT L _ REG _ SYNC are coupled to a second clock signal terminal i _ clk;

the first input terminals I0_3N +3 to I0_4N of the 3N +3 th to 4N gates RT L _ MUX _3N +3 to RT L _ MUX _4N are coupled to the first voltage terminal VDD;

the output end O _3N + k of the 3N + k gate RT L _ MUX _3N + k is coupled to the second input end I1_3N + k +1 of the 3N + k +1 gate, k is 3 to N-1, the output end O _4N of the 4N gate RT L _ MUX _4N is coupled to the SET end SET of the 3N +4D flip-flop RT L _ REG _ SYNC, wherein the SET end is a SET-1 end, that is, when the SET is valid, the output end Q of the 3N +4D flip-flop RT L _ REG _ SYNC is SET to 1.

The input terminal D _3N +2 of the 3N + 2D flip-flop RT L _ REG _3N +2 is the first input terminal 4-I1 of the data output buffer sub-circuit 4, the output terminal Q _3N +2 of the 3N + 2D flip-flop RT L _ REG _3N +2 is the first output terminal 4-o1 of the data output buffer sub-circuit 4 (the first output terminal 4-o1 is coupled to the port o _ dout1), the input terminal D _3N +3 of the 3N + 3D flip-flop RT L _ REG _3N +3 is the second input terminal 4-I2 of the data output buffer sub-circuit 4, the output terminal Q _3N +3 of the 3N + 3D flip-flop RT L _ REG _3N +3 is the second output terminal 4-o2 of the data output buffer sub-circuit 4 (the second output terminal 4-o2 is coupled to the output terminal Q _3N + 3D flip-flop RT 6326 of the data output buffer sub-circuit 4, the third output buffer sub-circuit 4N 3N +3 MUX 0, the output buffer sub-3N +3 MUX 3N +3 output buffer sub-3 MUX 3N 3 sub-3 circuit 4 is coupled to the output terminal 0, the output buffer sub-3 MUX sub-RT 3 and the output buffer sub-3 MUX 3N 3 MUX 3N +3 output terminal 0, the output buffer sub-3N 3 MUX3 output buffer sub-3 and the output terminal 3N 3 MUX3 sub-3 MUX3 sub-RT 3 MUX 3N +3 sub-3 (the output terminal 0, the second output terminal 3 MUX 3D buffer sub-3 MUX3 sub.

Fig. 8 is an exemplary structure of a data output buffer sub-circuit, and those skilled in the art will readily understand that the implementation manner of the sub-circuit is not limited thereto as long as the function thereof can be realized.

In an exemplary embodiment, N may be 4, and the output signal of the m-th output terminal 1-om of the input phase delay sub-circuit is phase-delayed by 90 × m degrees with respect to the second signal. That is, the output signal of the first output terminal 1-o1 is phase-delayed 90 degrees with respect to the second signal, the output signal of the second output terminal 1-o2 is phase-delayed 180 degrees with respect to the second signal, the output signal of the third output terminal 1-o2 is phase-delayed 270 degrees with respect to the second signal, and the output signal of the fourth output terminal 1-o2 is phase-delayed 360 degrees with respect to the second signal.

In an exemplary embodiment, a frequency of the first clock signal terminal i _ clk200 may be N times a frequency of the second clock signal terminal i _ clk. For example, if N is 4, the frequency of the second clock signal is 50M, and the frequency of the first clock signal is 200M.

Fig. 9 is a schematic diagram of a synchronization circuit according to an embodiment, where N may be 4 in the embodiment. As shown in fig. 9, in this embodiment, the synchronization circuit may include: an input phase delay sub-circuit 1, 5 data frame header accumulation sub-circuits (1 st to 5 th data frame header accumulation sub-circuits), 4 data output decision sub-circuits (1 st to 4 th data output decision sub-circuits), and a data output buffer sub-circuit 4. The input phase delay sub-circuit 1 generates 90 degrees, 180 degrees, 270 degrees, 360 degrees phase delay data relative to the second input data, four paths of delay data are respectively input to the 1 st 4 th data frame header accumulation sub-circuit, the first input data are input to the 5 th data frame header accumulation sub-circuit, when the accumulated value reaches the set value, the 4 data output judgment sub-circuits judge according to the output result of the data frame header accumulation sub-circuit, including: judging the output result of the 1 st data frame header accumulation sub-circuit and the output result of the 5 th data frame header accumulation sub-circuit, judging the output result of the 2 nd data frame header accumulation sub-circuit and the output result of the 5 th data frame header accumulation sub-circuit, judging the output result of the 3 rd data frame header accumulation sub-circuit and the output result of the 5 th data frame header accumulation sub-circuit, judging the output result of the 4 th data frame header accumulation sub-circuit and the output result of the 5 th data frame header accumulation sub-circuit, if one judgment result is equal in output, outputting the synchronized data to the data output cache sub-circuit 4, and completing synchronization.

In this embodiment, the input phase delay sub-circuit 1 may include 4 sets of D flip-flops RT L _ REG _1 to RT L _ REG _4, each set of D flip-flops may include an input terminal D _ i, an output terminal Q _ i and a clock input terminal C _ i, the clock input terminal C _ i of each set of D flip-flops is coupled to the first clock signal terminal i _ clk200, the input terminal D _4 of the 4 th set of D flip-flops RT L _ REG _4 is coupled to the output terminal Q _3 of the 3 rd set of D flip-flops RT L _ REG _3, the input terminal D _3 of the 3 rd set of D flip-flops RT L _ REG _3 is coupled to the output terminal Q _2 of the 2 nd set of D flip-flops RT L _ REG _2, and the 2 nd set of DAn input terminal D _2 of the transmitter RT L _ REG _2 is coupled to an output terminal Q _1 of the 1 st set of D flip-flops RT L _ REG _1, and an input terminal D _1 of the 1 st set of D flip-flops RT L _ REG _1 is coupled to a second data terminal idin1[15: 0%]. The 4 output terminals Q _1 to Q _4 of the 4D flip-flops are the 4 output terminals 1-o1 to 1-o4 of the input phase delay sub-circuit, respectively coupled to the node A₁To node A₄. Node A₅Is coupled to a first data terminal idin0[15: 0]]. Wherein, the first data terminal idin0[15: 0]]For example, 16 bits, and a second data terminal idin1[15: 0]]For example 16 bits, and accordingly each group of D flip-flops comprises 16D flip-flops, i.e. 16-bit D flip-flops. The first signal (output data of a first chip IC) and the second signal (output data of a second chip IC) collect data for pixels of two readout ICs, respectively. The input phase delay sub-circuit generates phase delay data of 90 degrees, 180 degrees, 270 degrees and 360 degrees relative to the input data, and the phase delay data are respectively input to the 1 st to 4 th data frame head accumulation sub-circuits. The operating clock, i.e., the first clock signal i _ clk200, is 200MHz, and the sum of the PCB wiring delay and the chip internal wiring delay does not exceed 5ns at maximum, so the simulation setup phase delay is 360 degrees at maximum. The second clock signal i _ clk is 50M. Here, by way of example only, in other embodiments, the first clock signal and the second clock signal may be at other frequencies.

The 1 st data frame header accumulation sub-circuit may include a1 st accumulator RT L _ ADD1, a1 st frame header memory RT L _ ROM1, a1 st gate RT L _ MUX1, a 2 nd gate RT L _ MUX2, and a 5 th group D flip-flop RT L _ REG 5;

the 2 nd data frame header accumulation sub-circuit may include a 2 nd accumulator RT L _ ADD2, a 2 nd frame header memory RT L _ ROM2, a 3 rd gate RT L _ MUX3, a 4 th gate RT L _ MUX4, and a 6 th group D flip-flop RT L _ REG 6;

the 3 rd data frame header accumulation sub-circuit may include a 3 rd accumulator RT L _ ADD3, a 3 rd frame header memory RT L _ ROM3, a 5 th gate RT L _ MUX5, a 6 th gate RT L _ MUX6, and a 7 th group D flip-flop RT L _ REG 7;

the 4 th data frame header accumulation sub-circuit may include a 4 th accumulator RT L _ ADD4, a 4 th frame header memory RT L _ ROM4, a 7 th gate RT L _ MUX7, an 8 th gate RT L _ MUX8, and an 8 th group D flip-flop RT L _ REG 8;

the 5 th data frame header accumulation sub-circuit may include a 5 th accumulator RT L _ ADD5, a 5 th frame header memory RT L _ ROM5, a 9 th gate RT L _ MUX9, a 10 th gate RT L _ MUX10, and a 9 th group D flip-flop RT L _ REG 9;

taking the 1 st data frame header accumulation sub-circuit as an example to illustrate the connection relationship of the data frame header accumulation sub-circuit, the input terminal of the 1 st frame header memory RT L _ ROM1 is coupled to the node A₁An output terminal of the 1 frame header memory RT L _ ROM1 is coupled to the second input terminal I1_1 of the 1 st gate RT L _ MUX _1, a first input terminal I0_1 of the 1 st gate RT L0 _ MUX _1 is coupled to the first voltage terminal VDD, an output terminal O _1 of the 1 st gate RT L1 _ MUX _1 is coupled to the enable terminal CE _5 of the 5 th group D flip-flop RT L _ REG _5, a clock input terminal C _5 of the 5 th group D flip-flop RT L _ REG _5 is coupled to the first clock signal terminal I _ clk200, an input terminal D _5 of the 5 th group D flip-flop RT L _ 4_ 5 is coupled to the output terminal O _2 of the 2 th gate RT 72 _ MUX _2, a first input terminal L _ 3_ 2 of the 2 gate RT 72 _ MUX _5 is coupled to the second voltage terminal I _ VSS, an input terminal RT 72 _ 5_ RT 72 _ RT _ MUX _5 of the 2 nd group D flip-RT 72 _ MUX _5, a gate RT 72 _ 5_ MUX _5, a first input terminal RT 72 _ 5_ RT _ 5_ MUX _ 5_ RT _ 5_ RT _ 5_ RT _ 5_ RT _ 5_ RT _ 5_ RT _ MUX _ 5_₁When the input data of the RT L _ ROM1 is equal to the first data in the frame header memory RT L _ ROM1, the count of the accumulator RT L _ ADD1 is increased by one, and when the count of the accumulator RT L _ ADD1 reaches 3, the count of the accumulator RT L _ ADD1 is cleared to wait for the next count.

The 1 st data output decision sub-circuit may include a1 st comparator RT L _ EQ1, a 10 th flip-flop RT L _ REG _10, and an 11 th gate RT L _ MUX _11, and the 1 st comparisonA first input terminal E1_ I0 coupled to the node B₁A second input terminal E1_ I1 coupled to the node B₅An output terminal E1_ O is coupled to an input terminal D _10 of the 10D flip-flop RT L _ REG _10, a clock input terminal C _10 of the 10D flip-flop RT L _ REG _10 is coupled to the first clock signal terminal I _ clk200, an output terminal Q _10 of the 10D flip-flop RT L _ REG _10 is coupled to a gate terminal S _11 of the 11 th gate RT L _ MUX _11, and a first input terminal I0)11 of the 11 th gate RT L _ MUX _11 is coupled to the node A₁A second input terminal I1_11 coupled to the first output terminal of the 2 nd data output decision sub-circuit, i.e., the output terminal O _12 of the 12 th gate RT L _ MUX _12, and a1 st data output decision sub-circuit coupled to the output terminal of the node B₁Of the node B (i.e. the output signal of the 1 st data frame header accumulation sub-circuit) and the node B₅The output signal of the 5 th data frame header accumulation sub-circuit is compared with the input signal, if the output signal of the data frame header accumulation sub-circuit is equal to the input signal, the data is synchronized, and then the data from the node A is synchronized₁And (4) outputting the signal.

The 2 nd data output decision sub-circuit may include a 2 nd comparator RT L _ EQ2, an 11D th flip-flop RT L _ REG _11 and a 12 th gate RT L _ MUX _12, and a first input E2_ I0 of the 2 nd comparator is coupled to the node B₂A second input terminal E2_ I1 coupled to the node B₅An output terminal E2_ O is coupled to an input terminal D _11 of the 11D flip-flop RT L _ REG _11, a clock input terminal C _11 of the 11D flip-flop RT L _ REG _11 is coupled to the first clock signal terminal I _ clk200, an output terminal Q _11 of the 11D flip-flop RT L _ REG _11 is coupled to a gate terminal S _12 of the 12 th gate RT L _ MUX _12, and a first input terminal I0_12 of the 12 th gate RT L _ MUX _12 is coupled to the node A₂A second input terminal I1_12 coupled to the first output terminal of the 3 rd data output decision sub-circuit, i.e., the output terminal O _13 of the 13 th gate RT L _ MUX _12, and a 2 nd data output decision sub-circuit coupled to the output terminal of the node B₂Of the node B (i.e. the output signal of the 2 nd data frame header accumulation sub-circuit) and the node B₅The output signal of the 5 th data frame header accumulation sub-circuit is compared with the input signal, if the output signal of the data frame header accumulation sub-circuit is equal to the input signal, the data is synchronized, and then the data from the node A is synchronized₂And (4) outputting the signal.

The 3 rd data output decision sub-circuit may include a 3 rd comparator RT L _ EQ3, a 12D flip-flop RT L _ REG _12 and a 13 th gate RT L _ MUX _13, wherein a first input E3_ I0 of the 3 rd comparator is coupled to the node B₃A second input terminal E3_ I1 coupled to the node B₅An output terminal E3_ O is coupled to an input terminal D _12 of the 12D flip-flop RT L _ REG _12, a clock input terminal C _12 of the 12D flip-flop RT L _ REG _12 is coupled to the first clock signal terminal I _ clk200, an output terminal Q _12 of the 12D flip-flop RT L _ REG _12 is coupled to a gate terminal S _13 of the 13 th gate RT L _ MUX _13, and a first input terminal I0_13 of the 13 th gate RT L _ MUX _13 is coupled to the node A₃A second input terminal I1_13 coupled to the first output terminal of the 4 th data output decision sub-circuit, i.e., the output terminal O _14 of the 14 th gate RT L _ MUX _14, and a 3 rd data output decision sub-circuit coupled to the output terminal of the node B₃Of the node B (i.e. the output signal of the 3 rd data frame header accumulation sub-circuit) and the node B₅The output signal of the 5 th data frame header accumulation sub-circuit is compared with the input signal, if the output signal of the data frame header accumulation sub-circuit is equal to the input signal, the data is synchronized, and then the data from the node A is synchronized₃And (4) outputting the signal.

The 4 th data output decision sub-circuit may include a 4 th comparator RT L _ EQ4, a 13 th flip-flop RT L _ REG _13 and a 14 th gate RT L _ MUX _14, and a first input E4_ I0 of the 4 th comparator is coupled to the node B₄A second input terminal E4_ I1 coupled to the node B₅An output terminal E4_ O is coupled to an input terminal D _13 of the 13D flip-flop RT L _ REG _13, a clock input terminal C _13 of the 13D flip-flop RT L _ REG _13 is coupled to the first clock signal terminal I _ clk200, an output terminal Q _13 of the 13D flip-flop RT L _ REG _13 is coupled to a gate terminal S _14 of the 14 th gate RT L _ MUX _14, and a first input terminal I0_14 of the 14 th gate RT L _ MUX _14 is coupled to the node A₄The second input terminal I1_14 is coupled to the first data terminal A₅. The 4 th data output decision sub-circuit comes from the node B₄Of the node B (i.e. the output signal of the 4 th DATA FRAG ACCUMULATION SUB-CIRCUIT) and the node B₅Is (i.e. the output signal of the 5 th DATA FRAG HEAD ACCUMULATION SUB-CIRCUIT)) Comparing, comparing the output signal and input signal of data frame head accumulation sub-circuit, if they are equal, indicating that the data is completed synchronization, then the output signal and input signal from node A are compared₄And (4) outputting the signal.

The data output buffer sub-circuit 4 may include a 14 th group D flip-flop RT L _ REG _14, a 15 th group D flip-flop RT L _ REG _15, a 16 th group D flip-flop RT L _ REG _ SYNC, a 15 th gate RT L _ MUX _15, and a 16 th gate RT L _ MUX _16, wherein,

a clock input terminal C _14 of the 14 th group D flip-flop RT L _ REG _14, a clock input terminal C _15 of the 15 th group D flip-flop RT L _ REG _15, and a clock input terminal C of the 16 th group D flip-flop RT L _ REG _ SYNC are coupled to a second clock signal terminal i _ clk;

the first input terminal I0_15 of the 15 th gate RT L _ MUX _15 and the first input terminal I0_16 of the 16 th gate RT L _ MUX _16 are coupled to the first voltage terminal VDD;

a second input terminal I1_15 of the 15 th gate RT L _ MUX _15 is coupled to the output terminal Q _12 of the 12 th flip-flop RT L _ REG _12, and a gate terminal S _12 of the 15 th gate RT L _ MUX _15 is coupled to the output terminal Q _11 of the 11 th flip-flop RT L _ REG _ 11;

the second input terminal I1_16 of the 16 th gate RT L _ MUX _16 is coupled to the output terminal O _15 of the 15 th gate RT L _ MUX _15, the gate terminal S _16 of the 16 th gate RT L _ MUX _16 is coupled to the output terminal Q _10 of the 10 th flip-flop RT L _ REG _10, and the output terminal O _16 of the 16 th gate RT L _ MUX _16 is coupled to the SET terminal SET of the 16 th flip-flop RT L _ REG _ SYNC;

an input end D of the 16D flip-flop RT L _ REG _ SYNC is coupled to an output end Q _13 of the 13D flip-flop RT L _ REG _13, and an output end of the 16D flip-flop RT L _ REG _ SYNC outputs an enable signal o _ dout _ en;

an input terminal D _15 of the 15 th group D flip-flop RT L _ REG _15 is coupled to a first data terminal i _ din0[15:0], and an output terminal Q _15 outputs a signal obtained by converting the first signal into a predetermined clock domain;

an input terminal D _14 of the 14 th group D flip-flop RT L _ REG _14 is coupled to an output terminal O _11 of the 11 th gate RT L _ MUX _11, and an output terminal Q _14 of the 14 th group D flip-flop RT L _ REG _14 outputs a synchronization signal after being converted to a predetermined clock domain.

The data output buffer sub-circuit 4 buffers a signal input from the 11 th gate RT L _ MUX _11 and a signal input from the first data terminal I _ din0[15:0], converts the signal input from the 11 th gate RT L _ MUX _11 to a preset clock domain and then outputs through the output terminal Q _14 of the 14 th group D flip-flop RT L _ REG _14, converts the signal input from the first data terminal I _ din0[15:0] to the preset clock domain and then outputs through the output terminal Q _15 of the 15 th group D flip-flop RT L _ REG _15, and determines whether to enable the output of the SYNC signal through the output terminal Q L according to a comparison result of the second input terminal I1_15 of the 15 th gate RT L _ MUX _15, the gate terminal S _15 of the 15 th gate RT L _ MUX _15, the gate terminal S _16 of the 16 th gate RT L _ MUX _16, the input terminal S _16 of the 16 th group D flip-flop RT L _ SYNC _ D flip-flop t 25.

Fig. 10 is a simulation diagram of the input phase delay sub-circuit 1 according to an embodiment. As shown in fig. 10, the signals input from the second data terminals i _ din1[15:0] are delayed to r _ din1_ d0[15:0], r _ din1_ d1[15:0], r _ din1_ d2[15:0], and r _ din1_ d3[15:0], and are delayed by 90 degrees, 180 degrees, 270 degrees, and 360 degrees, respectively, with respect to the signals input from the second data terminals i _ din1[15:0 ].

Fig. 11 is a simulation diagram of the header accumulation sub-circuit and the data output decision sub-circuit according to an embodiment. As shown in fig. 11, the accumulation results output by the 1 st to fifth data frame header accumulation sub-circuits are r _ cnt0[2:0], r _ cnt1[2:0], r _ cnt2[2:0], r _ cnt3[2:0], r _ cnt4[2:0], and 4 data output decision sub-circuits compare r _ cnt0[2:0], r _ cnt1[2:0], r _ cnt2[2:0], r _ cnt3[2:0], and r _ cnt4[2:0] respectively to obtain comparison results r _ din1_ en0, r _ din1_ en1, r _ din1_ en2, r _ din1_ en3 in this embodiment, r _ cnt3[2:0] is the same as r _ cnt4[2:0], r _ din1_ en3 output from the 4 th data output decision sub-circuit is high, indicating that synchronization is achieved, the delay signal r _ din1_ d3[15:0] input to the 4 th data frame header accumulation sub-circuit is a synchronized signal.

Fig. 12 to 15 are simulation diagrams of two regenerative delays differing by 90 degrees, 180 degrees, 270 degrees and 360 degrees, respectively.

FIG. 12 is a simulation of two readout delays 90 degrees apart, i.e., i _ din0[15:0] and i _ din1[15:0] differ by 90 degrees, as shown in FIG. 12, the frame header data is 55aa, i.e., the first data is 55aa, and after synchronization by the synchronization circuit provided in the present embodiment, i _ dout0[15:0] and i _ dout1[15:0] eliminate the delay and achieve synchronization, the enable signal o _ dout _ en is used to indicate whether synchronization is completed, and in the present embodiment, o _ dout _ en is high to indicate completion of synchronization, wherein i _ din _ en in FIG. 12 is an enable signal that can be input to the enable terminal (not shown in FIG. 9) of the 16D flip-flop RT L _ REG _ en and the enable terminals of the other D flip-flops to control whether the synchronization circuit is operating, and the subsequent SYNC signals can not be input to the I _ din en., which is not illustrated in FIG. 13.

FIG. 13 is a simulation of two readout ic delays 180 degrees apart. As shown in FIG. 13, the two readout ics are delayed by 180 degrees, i.e., i _ din0[15:0] and i _ din1[15:0] differ by 180 degrees. After the synchronization is performed by the synchronization circuit provided by the embodiment of the application, the delay is eliminated by i _ dout0[15:0] and i _ dout1[15:0], so that the synchronization is achieved. The enable signal o _ dout _ en is used to indicate whether synchronization is completed, and in this embodiment, when o _ dout _ en is high, synchronization is completed.

FIG. 14 is a simulation of two regenerative delays differing by 270 degrees. As shown in FIG. 14, the two readout ic delays are 270 degrees, i.e., i _ din0[15:0] and i _ din1[15:0] differ by 270 degrees. After the synchronization is performed by the synchronization circuit provided by the embodiment of the application, the delay is eliminated by i _ dout0[15:0] and i _ dout1[15:0], so that the synchronization is achieved. The enable signal o _ dout _ en is used to indicate whether synchronization is completed, and in this embodiment, when o _ dout _ en is high, synchronization is completed.

FIG. 15 is a simulation of two readout ic delays 90 degrees apart. As shown in FIG. 15, the two readout ics are delayed by 360 degrees, i.e., i _ din0[15:0] and i _ din1[15:0] differ by 360 degrees. After the synchronization is performed by the synchronization circuit provided by the embodiment of the application, i _ dout0[15:0] and i _ dout1[15:0] eliminate delay, so that synchronization is achieved, and the enable signal o _ dout _ en is used for indicating whether synchronization is completed.

The synchronization circuit provided by the embodiment of the application can be applied to high-resolution PIN screen readout ic, so that data delay among multiple pieces of readout ic is eliminated, or applied to readout ic in other screens, or applied to other scenes needing data synchronization.

In the above embodiments, only the synchronization of two signals is taken as an example for explanation. In other embodiments, if synchronization of multiple signals is required, one of the multiple signals may be used as a reference signal, and the other signals and the reference signal may be synchronized by the synchronization circuit in the above embodiments, i.e., using a plurality of the above synchronization circuits. In addition, in the plurality of synchronous circuits, some changes can be made to the data output buffer sub-circuit, only a signal obtained after the reference signal is converted into the preset clock domain is output in one synchronous circuit, and the signals obtained after the reference signal is converted into the preset clock domain are not output in the other synchronous circuits; alternatively, the total enable signal may be obtained directly from the comparison result of the outputs of the data output decision sub-circuits in all the synchronization circuits, and so on.

Based on the inventive concept of the foregoing embodiments, an embodiment of the present application further provides a synchronization method for a synchronization circuit, which is applied to the foregoing one or more synchronization circuits, and fig. 16 is a flowchart of the synchronization method for the synchronization circuit provided in the embodiment of the present application, where the synchronization circuit includes: as shown in fig. 16, the synchronization method of the synchronization circuit provided in the embodiment of the present application includes the following steps:

step 1601, after performing phase delay on a second signal input by a second data end, the input phase delay sub-circuit respectively outputs a delay signal to the 1 st to nth data frame header accumulation sub-circuits through the N output ends, and respectively outputs a delay signal to the first to nth data frame header accumulation sub-circuits, and the phase delay amounts of output signals of different output ends are different;

step 1602, when the input delay signal is equal to the first data, each of the 1 st to nth data frame header accumulation sub-circuits performs a count, respectively outputs 1 st to nth count results to the decision sub-circuit, and resets and recounts after the count number reaches N times; the (N + 1) th data frame header accumulation sub-circuit counts once when the first signal of the first data end is equal to the first data and outputs an (N + 1) th counting result to the decision sub-circuit;

in step 1603, the decision sub-circuit compares the 1 st to nth counting results with the N +1 st counting result, and outputs the delay signal input to the nth data frame header accumulation sub-circuit as a synchronization signal when the nth counting result is equal to the N +1 st counting result.

The synchronization method provided by this embodiment performs phase delay of different delay amounts on one of the signals, and counts frame header data to find out a delayed signal synchronized with the other signal, thereby implementing signal synchronization.

Based on the inventive concept of the above embodiments, an embodiment of the present application further provides a display device, including: the display device comprises a display substrate 10, a readout circuit 20 and a synchronization circuit 30, wherein the readout circuit 20 is coupled to the display substrate 10, the synchronization circuit 30 is coupled to the readout circuit 20, and the synchronization circuit 30 is configured to receive a data signal output by the readout circuit 20, synchronize the data signal and output the data signal to the readout circuit 20. The display device provided by the embodiment synchronizes signals of the reading circuit, eliminates delay and improves the uniformity of pixels.

The synchronization circuit is provided in the above embodiments, and the implementation principle and the implementation effect thereof are similar, and are not described herein again.

The display device can be any product or component with a display function, such as an O L ED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

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Synchronous circuit, synchronous method thereof and display device

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