阅读说明：本技术 一种晶圆的退火方法 (Wafer annealing method ) 是由 邵迎亚 曲厚任 鲍丙辉 于 2020-05-06 设计创作，主要内容包括：本发明提出一种晶圆的退火方法,包括：提供一晶圆,所述晶圆包括多个区域,所述多个区域同心设置在所述晶圆上；对所述多个区域进行升温处理,所述升温处理具有多个升温阶段,每个所述升温阶段相应的升温速率不同,其中,所述多个区域在每个所述升温阶段中的温度不同；对所述多个区域进行保温处理；对所述多个区域采用氮气吹冷方式进行降温处理。本发明提出的晶圆的退火方法可以提高晶圆的电性均匀性。(The invention provides an annealing method of a wafer, which comprises the following steps: providing a wafer, wherein the wafer comprises a plurality of areas, and the areas are concentrically arranged on the wafer; performing temperature rise treatment on the plurality of areas, wherein the temperature rise treatment has a plurality of temperature rise stages, the temperature rise rate of each temperature rise stage is different, and the temperatures of the plurality of areas in each temperature rise stage are different; carrying out heat preservation treatment on the plurality of areas; and cooling the plurality of areas in a nitrogen blowing manner. The annealing method of the wafer can improve the electrical uniformity of the wafer.)

1. A method for annealing a wafer, comprising:

providing a wafer, wherein the wafer comprises a plurality of areas, and the areas are concentrically arranged on the wafer;

performing temperature rise treatment on the plurality of areas, wherein the temperature rise treatment has a plurality of temperature rise stages, the temperature rise rate of each temperature rise stage is different, and the temperatures of the plurality of areas in each temperature rise stage are different;

carrying out heat preservation treatment on the plurality of areas;

and cooling the plurality of areas in a nitrogen blowing manner.

2. The annealing method according to claim 1, characterized in that: the plurality of zones include a first zone to a seventh zone, and the temperature difference between two adjacent zones is 1-4 ℃.

3. The annealing method according to claim 2, characterized in that: the first area to the seventh area are sequentially arranged from the center to the edge of the wafer.

4. The annealing method according to claim 2, characterized in that: the plurality of temperature rise stages comprise a first stage to a fifth stage, and the temperature rise rates of the first stage to the fifth stage are sequentially a third stage, a fourth stage, a first stage, a fifth stage and a second stage from large to small.

5. The annealing method according to claim 4, characterized in that: the heating rate of the first stage is 33 ℃/s, the heating rate of the second stage is 10 ℃/s, the heating rate of the third stage is 75 ℃/s, the heating rate of the fourth stage is 50 ℃/s, and the heating rate of the fifth stage is 25 ℃/s.

6. The annealing method according to claim 5, characterized in that: the temperature rise time from the first stage to the fifth stage is 10-12s, 9-10s, 5-6s, 0.5-1s and 3-5s respectively.

7. The annealing method according to claim 5, characterized in that: the temperatures of the first area to the seventh area after each temperature rise stage are respectively as follows:

the temperatures of the first to seventh regions after the first stage are respectively: 390-410 ℃, 389-409 ℃, 388-408 ℃, 387-407 ℃, 386-406 ℃, 385-405 ℃ and 384-404 ℃;

the temperatures of the first area to the seventh area after the second stage are respectively as follows: 485-505 ℃, 484-504 ℃, 483-503 ℃, 482-502 ℃, 481-501 ℃, 480-500 ℃ and 479-499 ℃;

the temperatures of the first area to the seventh area after the third stage are respectively as follows: 870 ℃ plus 890 ℃, 869 ℃ plus 889 ℃, 868 ℃ plus 888 ℃, 867 ℃ plus 887 ℃, 866 ℃ plus 886 ℃, 865 ℃ plus 885 ℃ and 864 ℃ plus 884 ℃;

the temperatures of the first area to the seventh area after the fourth stage are respectively as follows: 920-;

the temperatures of the first area to the seventh area after the fifth stage are respectively as follows: 1020-; wherein the temperature near the center of the wafer is greater than the temperature away from the center of the wafer.

8. The annealing method according to claim 7, characterized in that: and after the first stage and before the second stage, the heat preservation is carried out for 10-20s in the first area to the seventh area.

9. The annealing method according to claim 1, characterized in that: the heat preservation time is 10-15 s.

10. The annealing method according to claim 1, characterized in that: the cooling rate was 35 ℃/s.

Technical Field

The invention relates to the technical field of semiconductors, in particular to an annealing method of a wafer.

Background

Wafers are one of the most important materials in the semiconductor industry, and products with specific electrical functions can be formed by forming various circuit device structures on the wafers. In the existing production process, due to the fact that the uniformity of manufacturing equipment has certain difference, even if the uniformity of each process is very small, after the processes are overlapped, after the wafers are tested, the fact that the electrical distribution of the wafers is uneven can be obviously seen, the yield is reduced, and the electric leakage of the edges of the wafers is serious. In the prior art, the problem is mostly solved by adjusting a Critical dimension (CD for short) through a yellow light process, but the yellow light process only has an obvious electrical property improvement effect on a small-sized device, and the effect gradually fails along with the increase of the dimension.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, the present invention provides an annealing method for a wafer to improve the electrical uniformity of the wafer and to increase the yield of the product.

To achieve the above and other objects, the present invention provides a method for annealing a wafer, comprising:

providing a wafer, wherein the wafer comprises a plurality of areas, and the areas are concentrically arranged on the wafer;

performing temperature rise treatment on the plurality of areas, wherein the temperature rise treatment has a plurality of temperature rise stages, the temperature rise rate of each temperature rise stage is different, and the temperatures of the plurality of areas in each temperature rise stage are different;

carrying out heat preservation treatment on the plurality of areas;

and cooling the plurality of areas in a nitrogen blowing manner.

Further, the plurality of zones include a first zone to a seventh zone, and the temperature difference between two adjacent zones is 1-4 ℃.

Further, the first area to the seventh area are arranged in sequence from the center to the edge of the wafer.

Further, the plurality of temperature rise stages include a first stage to a fifth stage, and the temperature rise rates of the first stage to the fifth stage are sequentially a third stage, a fourth stage, a first stage, a fifth stage and a second stage from large to small.

Further, the temperature increase rate of the first stage is 33 ℃/s, the temperature increase rate of the second stage is 10 ℃/s, the temperature increase rate of the third stage is 75 ℃/s, the temperature increase rate of the fourth stage is 50 ℃/s, and the temperature increase rate of the fifth stage is 25 ℃/s.

Further, the temperature rise time from the first stage to the fifth stage is 10-12s, 9-10s, 5-6s, 0.5-1s and 3-5s respectively.

Further, the temperatures of the first area to the seventh area after each of the temperature raising stages are respectively as follows:

the temperatures of the first to seventh regions after the first stage are respectively: 390-410 ℃, 389-409 ℃, 388-408 ℃, 387-407 ℃, 386-406 ℃, 385-405 ℃ and 384-404 ℃;

the temperatures of the first area to the seventh area after the second stage are respectively as follows: 485-505 ℃, 484-504 ℃, 483-503 ℃, 482-502 ℃, 481-501 ℃, 480-500 ℃ and 479-499 ℃;

the temperatures of the first area to the seventh area after the third stage are respectively as follows: 870 ℃ plus 890 ℃, 869 ℃ plus 889 ℃, 868 ℃ plus 888 ℃, 867 ℃ plus 887 ℃, 866 ℃ plus 886 ℃, 865 ℃ plus 885 ℃ and 864 ℃ plus 884 ℃;

the temperatures of the first area to the seventh area after the fourth stage are respectively as follows: 920-;

the temperatures of the first area to the seventh area after the fifth stage are respectively as follows: 1020-; wherein the temperature near the center of the wafer is greater than the temperature away from the center of the wafer.

Further, after the first stage and before the second stage, the first to seventh zones are subjected to heat preservation for 10-20 s.

Further, the heat preservation time is 10-15 s.

Further, the cooling rate is 35 ℃/s.

The invention provides an annealing method of a wafer, which is characterized in that the wafer is divided into a plurality of areas, the areas are heated in a staged manner, the heating rate of each stage is different, the temperature of each area in each heating stage is also different, and the temperature close to the center of the wafer is higher than the temperature far away from the center of the wafer, so that the electrical uniformity of the wafer is improved, the difference between chips on the wafer is improved, the electric leakage condition of the wafer is reduced, and the product yield is improved. Meanwhile, the annealing method has wide applicability, and different zone temperatures can be set according to the adjustment of the manufacturing process.

Drawings

FIG. 1: the annealing method of the wafer in this embodiment is a flowchart.

FIG. 2: a schematic diagram of a plurality of regions of a wafer in this embodiment is shown.

FIG. 3: another schematic diagram of a plurality of regions of a wafer in this embodiment is shown.

FIG. 4: the schematic diagram of the multiple temperature raising stages of the wafer in this embodiment.

FIG. 5: the temperature values of the respective areas after step S2 is completed in this embodiment.

FIG. 6: the schematic diagram of the heat preservation stage and the temperature reduction stage of the first area in this embodiment.

FIG. 7A: the resistance curve of the wafer in this embodiment is illustrated.

FIG. 7B: the repeated test patterns of the resistance of the wafer in this embodiment.

FIG. 8: the wafer leakage test graph in this embodiment.

FIG. 9: the flow chart of the rapid thermal processing method of the wafer in this embodiment.

FIG. 10: a schematic diagram of the annealing apparatus in this embodiment.

FIG. 11: the top view of the wafer fixing device in this embodiment.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

In this embodiment, the wafer may be a wafer supported by all semiconductor materials, such as a silicon wafer, a sapphire wafer, and a silicon carbide wafer. Taking silicon wafers as an example, the dimensions of the silicon wafers can be 2 inches, 4 inches, 6 inches, 8 inches or 12 inches, and the like.

Ion implantation is a process of implanting charged and energetic particles into a wafer. The main benefits of ion implantation over diffusion processes are more accurate control of impurity doping, repeatability and lower process temperatures. The ion implantation process is that ions are accelerated by an electric field in a vacuum system, and the movement direction of the ions is changed by a magnetic field, so that the ions are controlled to be implanted into the wafer at certain energy, and a surface layer (i.e. an implantation layer) with special properties is formed in a selected area, thereby achieving the purpose of doping. Its main side effect is the semiconductor lattice fracture or damage caused by ion collisions. To remove this damage, the wafer must be heat treated at an appropriate time and temperature to remove lattice defects and internal stresses in the wafer, restore lattice integrity, and allow the implanted dopant atoms to diffuse to substitutional sites, creating electrical properties. Rapid thermal processing may be used to activate the doping elements in the semiconductor material and restore the amorphous structure resulting from ion implantation to a complete lattice structure.

As shown in fig. 1, the present embodiment provides a method for annealing a wafer, including:

s1: providing a wafer, wherein the wafer comprises a plurality of areas, and the areas are concentrically arranged on the wafer;

s2: performing temperature-raising treatment on the plurality of areas, wherein the temperature-raising treatment has a plurality of temperature-raising stages, the temperature-raising rate of each temperature-raising stage is different, and the temperatures of the plurality of areas in each temperature-raising stage are different;

s3: carrying out heat preservation treatment on the plurality of areas;

s4: and cooling the plurality of areas in a nitrogen blowing manner.

As shown in fig. 2, in step S1, in the present embodiment, the wafer 100 is divided into a plurality of regions, and the plurality of regions are distributed along the center of the wafer 100 toward the edge, and in the present embodiment, the wafer 100 may be divided into seven regions, for example, a circular region and six annular regions, and the seven regions are sequentially arranged from the center of the wafer 100 toward the edge. Specifically, the first region 101 is a circular region, and the second to seventh regions 102 to 107 are annular regions. The second region 102 is disposed around the outer periphery of the first region 101, the third region 103 is disposed around the outer periphery of the second region 102, the fourth region 104 is disposed around the outer periphery of the third region 103, the fifth region 105 is disposed around the outer periphery of the fourth region 104, the sixth region 106 is disposed around the outer periphery of the fifth region 105, and the seventh region 107 is disposed around the outer periphery of the sixth region 106. By dividing the wafer 100 into seven regions, which are independent of each other, each region can be temperature controlled separately.

As shown in fig. 2, the radius of the first region 101 is equal to the inner diameter of the second region 102, and the inner diameter of the outer annular region is equal to the outer diameter of the inner annular region adjacent thereto. For example, the inner diameter of the second region 102 is equal to the radius of the first region 101, the outer diameter of the second region 102 is equal to the inner diameter of the third region 103, the outer diameter of the third region 103 is equal to the inner diameter of the fourth region 104, and so on. In order to avoid a more pronounced temperature transition between two adjacent zones.

As shown in fig. 3, in some embodiments, the wafer 100 may be provided with a plurality of zones according to the distribution of the heaters in the furnace, for example, the wafer may be divided into four zones, i.e., a first zone 101 to a fourth zone 104, the first zone 101 is a circular zone, and the second zone 102 to the fourth zone 104 are annular zones. The three annular and circular zones are concentrically arranged and distributed along the periphery of the first zone 101. In some embodiments, the wafer 100 may be further divided into two, three, five or six regions, and it should be noted that the number of regions is not limited thereto in other embodiments.

As shown in fig. 2 and 4, fig. 4 is a schematic diagram showing temperature rising curves of the respective regions, where it is to be noted that a temperature rising curve L1 represents a temperature rising process of the first region 101, a temperature rising curve L7 represents a temperature rising process of the seventh region 107, and temperature rising curves of the other second region 102 to the sixth region 106 are not shown in fig. 4, in step S2, when the wafer 100 is placed in the annealing furnace body, the wafer 100 is subjected to a temperature rising process through a plurality of temperature rising stages, and the plurality of regions of the wafer 100 may be subjected to a temperature rising process through five temperature rising stages, for example, so as to perform an annealing process.

As shown in fig. 2 and 4, in the present embodiment, when the wafer 100 is placed in the annealing furnace body, the first stage a1 temperature raising process is first performed, the temperature raising rate is 33 ℃/s, for example, and the time can be 10-12s, for example, 11s, so that each region reaches the preset temperature, and the temperature of the wafer 100 gradually decreases from the first region 101 to the seventh region 107. For example, after the first stage A1, the temperature of the first zone 100 may be at 390-410 deg.C, such as 396 deg.C; the temperature of the second zone 102 may be at 389-409 deg.C, such as 395 deg.C; the temperature of the third region 103 may be 388-408 ℃, for example 394 ℃; the temperature of the fourth zone 104 may be 387-; the temperature of the fifth zone 105 may be at 386-406 deg.C, such as 392 deg.C; the temperature of the sixth zone 106 may be at 385-405 deg.C, such as 391 deg.C; the temperature of the seventh zone 107 may be 384-. In the present embodiment, after the first temperature-raising period a1, the temperatures of the first area 101 to the seventh area 107 gradually decrease, and the temperature difference between the two adjacent areas is 1 ℃.

As shown in fig. 2 and 4, after the first stage a1 is completed, the temperature may be maintained for 10-20s, for example, for 15s, and then the wafer 100 is subjected to a second stage a2 temperature raising process, where the temperature raising rate is, for example, 10 ℃/s, the temperature raising time may be, for example, 9-10s, for example, 10.2s, and after the second stage a2, the temperature of the first region 101 may be 485-; the temperature of the second region 102 may be at 484-504 deg.C, such as 497 deg.C; the temperature of the third zone 103 may be 483-503 deg.C, such as 496 deg.C; the temperature of the fourth region 104 may be at 482-502 deg.C, for example 495 deg.C; the temperature of the fifth region 105 may be 481-501 deg.C, such as 494 deg.C; the temperature of the sixth zone 106 may be at 480-; the temperature of the seventh zone 107 may be at 479-499 deg.c, such as 492 deg.c. In the present embodiment, after the second stage a2, the temperatures of the first area 101 to the seventh area 107 gradually decrease, and the temperature difference between the two adjacent areas is 1 ℃.

As shown in fig. 2 and 4, after the second stage a2 is completed, the third stage A3 temperature raising process is performed on the wafer 100, the temperature raising rate is, for example, 75 ℃/s, the temperature raising time can be, for example, 5-6s, for example, 5.2s, and after the third stage A3, the temperature of the first region 101 can be 870-; the temperature of the second region 102 may be at 869-889 deg.C, such as 887 deg.C; the temperature of the third region 103 may be 868-888 deg.C, such as 886 deg.C; the temperature of the fourth zone 104 may be at 867-887 deg.C, such as 885 deg.C; the temperature of the fifth region 105 may be at 866-886 deg.C, such as 884 deg.C; the temperature of the sixth zone 106 may be at 865-885 deg.C, such as 883 deg.C; the temperature of the seventh zone 107 may be 864-884 deg.C, such as 882 deg.C. In the present embodiment, after the third stage a3, the temperatures of the first area 101 to the seventh area 107 gradually decrease, and the temperature difference between the two adjacent areas is 1 ℃.

As shown in fig. 2 and 4, after the third stage A3 is completed, a fourth stage a4 temperature raising process is performed on the wafer 100, wherein the temperature raising rate is, for example, 50 ℃/s, the temperature raising time can be, for example, 0.5-1s, for example, 0.84s, and after the fourth stage a4, the temperature of the first region 101 can be at 920-940 ℃, for example, 930 ℃; the temperature of the second zone 102 may be 919-939 ℃, for example 929 ℃; the temperature of the third zone 103 may be 918-938 deg.c, for example 928 deg.c; the temperature of the fourth region 104 may be 917-; the temperature of the fifth zone 105 may be 916-; the temperature of the sixth zone 106 may be at 915-935 deg.C, for example 925 deg.C; the temperature of the seventh zone 107 may be 914-934 deg.C, for example 924 deg.C. In the present embodiment, after the fourth stage a4, the temperatures of the first area 101 to the seventh area 107 gradually decrease, and the temperature difference between the two adjacent areas is 1 ℃.

As shown in fig. 2 and 4, after the fourth stage a4 is completed, a fifth stage a5 temperature raising process is performed on the wafer 100, wherein the temperature raising rate is, for example, 25 ℃/s, the temperature raising time can be, for example, 3-5s, for example, 4s, and after the fifth stage a5, the temperature of the first region 101 can be at 1020-1040 ℃, for example, 1030 ℃; the temperature of the second region 102 may be 1019-1039 ℃, for example 1029 ℃; the temperature of the third region 103 can be 1018-; the temperature of the fourth zone 104 may be 1017-; the temperature of the fifth region 105 may be at 1016-1036 deg.C, such as 1026 deg.C; the temperature of the sixth zone 106 may be 1015-; the temperature of the seventh zone 107 may be 1014-1034 deg.C, for example 1024 deg.C. In the present embodiment, after the fifth stage a5, the temperatures of the first area 101 to the seventh area 107 gradually decrease, and the temperature difference between the two adjacent areas is 1 ℃.

As shown in fig. 2 and 4, the temperature-raising curve L represents the temperature-raising process of the first area 101, and the temperature-raising curve L represents the temperature-raising process of the seventh area 107, after five temperature-raising stages, the temperature of the first area 101 is the highest, the temperature of the seventh area 107 is the lowest, that is, the temperature gradually decreases from the first area 101 to the seventh area 107, that is, the temperature near the center of the wafer 100 is higher than the temperature far away from the center of the wafer 100. as can be seen from the temperature-raising curves L or L, the temperature-raising rate of the third temperature-raising stage A3 is higher than that of the fourth temperature-raising stage A4, the temperature-raising rate of the fourth temperature-raising stage A4 is higher than that of the first temperature-raising stage a1, the temperature-raising rate of the first temperature-raising stage a1 is higher than that of the fifth temperature-raising stage A5, and the temperature-raising rate of the fifth temperature-raising stage a 483.

As shown in fig. 5, fig. 5 shows temperature values of the respective regions after step S2. It can be seen that the temperature decreases from the first region 101 to the seventh region 107, i.e. the temperature of the first region 101 is the highest, e.g. 1040 c, and the temperature of the seventh region 107 is the lowest, e.g. 1014 c.

As shown in fig. 6, in the present steps S3-S4, after step S2 is completed, that is, after each region in the wafer 100 is heated to the corresponding temperature, a heat preservation process may be performed, the heat preservation time may be 10-15S, for example, 12S, and then a cooling process is performed, that is, each region of the wafer 100 is cooled, for example, by using a nitrogen cold blow, and the cooling rate of the wafer 100 is, for example, 35 ℃/S. Fig. 6 shows only the heat-retention stage and the temperature-lowering stage of the first region 101.

In this embodiment, the wafer 100 is heated through five temperature raising stages, and in some embodiments, the wafer 100 may also be heated through three or four temperature raising stages, where it should be noted that the number of the temperature raising stages provided in the present invention is not limited thereto.

As shown in fig. 7A to 7B, in fig. 7A, curve 1 is a test curve obtained by the annealing method in the present embodiment, and curve 2 is a standard test curve obtained by the prior art. Comparing the curve 1 and the curve 2, it can be known that, due to the temperature control method of the plurality of regions, that is, the temperature of the wafer gradually decreases from the central region to the edge region of the wafer, and the plurality of temperature rise stages are provided, the temperature rise rate of each temperature rise stage is different, so that the trend that the resistance value of the wafer gradually rises from the center to the edge is presented, the change rule of the resistance in the wafer is met, and meanwhile, the thermal budget of the edge region of the surface of the wafer is reduced. As shown in fig. 7B, the curves obtained by the three verification tests are substantially consistent, and the annealing method in this embodiment has good coincidence, high sensitivity, and good reproducibility. The resistance trend curve in this embodiment is a curve formed by connecting points on the surface of the wafer from near to far according to the distance from the center of the wafer, and measuring the resistance of the corresponding point.

As shown in fig. 8, the curves 3 and 4 are the test curves obtained in the prior art for the leakage test chart of the wafer obtained through three methods, where the curve 3 is the test curve obtained without setting the multi-exposure process, the curve 4 is the test curve obtained with setting the multi-exposure process, and the curve 5 is the test curve obtained by the annealing method in this embodiment. As can be seen from comparing the three sets of curves, the curve 5 is located below the curves 3 and 4, that is, the uniformity of the electrical property of the wafer surface obtained by the annealing method in this embodiment is good, the leakage of the current in each region is reduced, that is, the leakage of the entire wafer is significantly reduced, thereby improving the yield of the wafer.

As shown in fig. 9, the present embodiment provides a rapid thermal processing method for a wafer, including:

s101: providing a wafer, wherein the wafer comprises a plurality of areas which are concentrically arranged, and the areas are distributed along the center of the wafer to the edge;

s102: and carrying out rapid thermal treatment on the wafer.

As shown in fig. 2, in step S101, the wafer 100 includes a plurality of regions, the plurality of regions are distributed from the center to the edge of the wafer 100 in a concentric manner, specifically, the second region 102 is disposed around the outer periphery of the first region 101, the third region 103 is disposed around the outer periphery of the second region 102, the fourth region 104 is disposed around the outer periphery of the third region 103, and so on, the wafer 100 is divided into a circular region and six annular regions, the plurality of regions in this embodiment are independent from each other, and each region can be heated separately or simultaneously.

In step S102, when the wafer is subjected to the rapid thermal processing, temperatures of a plurality of regions on the wafer are different, and a temperature of a center of the wafer is higher than a temperature of an edge of the wafer.

In this embodiment, the rapid thermal process may include four or five temperature-raising stages, for example, the annealing temperature used in the rapid thermal process is 900-.

In the embodiment, the wafer is subjected to rapid thermal treatment, so that the edge temperature of the wafer can be reduced, the electrical uniformity of the wafer can be improved, and the yield of products can be improved.

As shown in fig. 10, the present embodiment further provides an annealing apparatus 200, where the annealing apparatus 200 includes a chamber 201, a plurality of heating units 202 are disposed on a top of the chamber 201, and the plurality of heating units 202 are configured to perform separate annealing processes on a plurality of regions of a wafer to be annealed. A wafer holder 203 is further disposed at the bottom of the chamber 201, and one or more wafers are loaded on the wafer holder 203.

As shown in fig. 10-11, in the present embodiment, a wafer 100 is carried on the wafer fixing device 203, and each wafer 100 includes a plurality of concentrically disposed regions distributed along the center of the wafer 100 toward the edge of the wafer 100. In the present embodiment, the heating units 202 are used to heat the regions of the wafer 100 for annealing, and the heating units 202 may be, for example, lasers or lamps. It should be noted that the plurality of areas may be heated by the plurality of heating units 202, so that the temperatures of the plurality of areas are different, and the temperature at the center of the wafer 100 is higher than the temperature at the edge of the wafer 100. In the present embodiment, the annealing temperature of the wafer 100 may reach 950-. In some embodiments, the wafer fixture 203 may, for example, carry a plurality of wafers 100 thereon.

In summary, the present invention provides an annealing method for a wafer, in which the wafer is heated through a plurality of heating stages, and the temperature of the surface of the wafer gradually decreases from the center to the edge from the first heating stage, so as to improve the electrical uniformity of the wafer, improve the difference between the chips on the wafer, reduce the leakage of electricity, and improve the yield of the wafer.

The above description is only a preferred embodiment of the present application and a description of the applied technical principle, and it should be understood by those skilled in the art that the scope of the present invention related to the present application is not limited to the technical solution of the specific combination of the above technical features, and also covers other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, for example, the technical solutions formed by mutually replacing the above features with (but not limited to) technical features having similar functions disclosed in the present application.

Other technical features than those described in the specification are known to those skilled in the art, and are not described herein in detail in order to highlight the innovative features of the present invention.