阅读说明：本技术 电源转换器稳定控制的方法和装置 (Method and device for stably controlling power converter ) 是由 阿米尔·巴巴扎德 克里斯·M·杨 于 2019-12-10 设计创作，主要内容包括：本发明公开了电源转换器稳定控制的方法和装置。该装置和相关方法关联开关信号的频率调制。经调制后,可在保持预定N个周期数上平均频率恒定的同时实现快速瞬态响应。在一例证中,量子电荷调制器可包含补偿处理器,后者经配置后可以通过执行操作以响应瞬态,保持N个周期上平均开关频率,来补偿误差信号和生成补偿信号。补偿信号可以是真实相偏差△T<Sub>SW</Sub>的函数,该真实相偏差为瞬态前具有循环周期T<Sub>SW</Sub>的稳定脉冲模制信号与瞬态后具有循环周期T<Sub>SW_M</Sub>的测得脉冲模制信号之差。可以应用遗忘因子,来计算相偏差。量子电荷调制器可提供针对功率级组件变更的无补偿、稳定和高性能响应。(In one example, a quantum charge modulator may include a compensation processor configured to compensate an error signal and generate a compensation signal by performing an operation to maintain an average switching frequency over N cycles in response to a transient, the compensation signal may be a true phase deviation △ T SW Has a cycle period T before the transient SW Has a cycle period T after the transient state and a stable pulse molding signal SW_M The difference between the measured pulse molding signals. A forgetting factor can be applied to calculate the phase deviation. Quantum charge modulationThe device can provide uncompensated, stable, and high performance response to power stage component changes.)

1. An apparatus, comprising:

a feedback error compensator configured to generate a first compensation signal in response to an error signal associated with a parameter of a controlled circuit of the digital feedback system;

a compensation processor configured to perform an operation by responding to the transient state, maintain the average switching frequency over a predetermined N cycles, thereby compensating the error signal and generating a second compensation signal; wherein the second compensation signal is a calculated phase deviation delta_calcIs calculated as a function of_calcIs the true phase deviation Δ T_SWHas a cycle period T before the transient_SWHas a cycle period T after the transient state and a stable pulse molding signal_{SW_M}The difference between the measured pulse-molding signals; and

a combining module configured to combine the first compensation signal and the second compensation signal to generate a control signal received by the digital feedback system; wherein the digital feedback system outputs a control signal generated in response to a period of the measured pulse-molding signal.

2. The apparatus of claim 1, wherein operations comprise:

(a) determining the true phase deviation Δ T_SW；

(b) If Δ T_SWLess than or equal to the predetermined threshold THR1, Δ is updated_calc0; and is

(c) If Δ T_SWGreater than THR1, for the first predetermined number of cycles NC1, by adding Δ T_SWUpdating Δ in each cycle_calc。

3. The apparatus of claim 2, wherein operations further comprise:

(d) if after the first predetermined number of cycles NC1, Δ T_SWGreater than THR1, the Δ in each cycle is updated by multiplying by a user predetermined forgetting factor for a second predetermined number of cycles NC2_calc(ii) a And

(e) if after NC1 cycles, Δ T_SWTHR1 or less, operations (a) - (d) of NC1 cycle are repeated.

4. The apparatus of claim 3, wherein the apparatus is a portable electronic deviceThe second predetermined number of cycles NC2 further includes a plurality of sub-cycles, and the compensation processor configuration may update Δ during each of the sub-cycles_calcTo associate a corresponding forgetting factor.

5. The apparatus of claim 3, wherein operations further comprise:

(f) if after a predetermined number of cycles NC2, Δ_calcIs greater than THR1, Δ is updated for a third predetermined number of cycles NC3_calc0; and

(g) if after NC2 cycles, Δ_calcIs equal to or less than THR1, the operations (a) - (d) of the NC1 cycle are repeated.

6. The apparatus of claim 1, wherein the compensation processor further comprises:

an error calculation circuit, configured to respond to the error signal, having a cycle period T_SWHas a cycle period T_{SW_M}Is measured, a delta is calculated_calc。

7. The apparatus of claim 6 wherein the error calculation circuit is further configured to calculate Δ in response to a user predetermined forgetting factor_calc。

8. The apparatus of claim 1, wherein the phase deviation Δ T_SW＝∑Δ_i.Δ_i＝Δ_i-1+(T_SW-T_{SW_Mi}) Where i is the ith pulse of the measured pulse modulated signal after the transient, i is 1,2, … N.

9. The phase apparatus of claim 1 wherein the compensation processor further comprises a fast gain path circuit configured to receive the error signal and to generate the amplified voltage error signal.

10. The apparatus of claim 9, the fast gain path circuit further comprising a low pass filter configured to filter the error signal and an amplification circuit configured to amplify the filtered error signal.

11. The apparatus of claim 10, the amplification circuit further comprising a first selection circuit configured to enable or disable the fast gain path circuit.

12. The apparatus of claim 11, wherein the amplification circuit further comprises an amplifier configured to amplify the filtered error signal using a first gain value when the voltage error signal is positive and to amplify the voltage error signal using a second gain value when the voltage error signal is negative.

13. The apparatus of claim 12, wherein the first gain value is different from the second gain value.

14. A method of configuring a quantum charge modulator, comprising:

generating a first compensation signal by a feedback error compensator in response to an error signal associated with a controlled circuit parameter of the digital feedback system;

compensating the error signal by performing an operation to maintain the average switching frequency over a predetermined number N of cycles in response to the transient, thereby generating a second compensation signal via the compensation processor; and

combining the first compensation signal and the second compensation signal to generate a control signal received by the digital feedback system; wherein the digital feedback system outputs a control signal generated in response to a period of the measured pulse-molding signal.

Wherein the second compensation signal is a calculated phase deviation delta_calcIs calculated as a function of_calcIs the true phase deviation Δ T_SWHas a cycle period T before the transient_SWHas a cycle period T after the transient state and a stable pulse molding signal_{SW_M}The difference between the measured pulse molding signals.

15. The method of claim 14, wherein performing the operations further comprises:

(a) determining the true phase deviation Δ T_SW；

(b) If Δ T_SWLess than or equal to the predetermined threshold THR1, Δ is updated_calc0; and

(c) if Δ T_SWGreater than THR1, for the first predetermined number of cycles NC1, by adding Δ T_SWUpdating delta_calc。

16. The method of claim 15, wherein performing the operations further comprises:

(d) if after the first predetermined number of cycles NC1, Δ T_SWGreater than THR1, Δ may be updated by multiplying by a user predetermined forgetting factor for a second predetermined number of cycles NC2_calc(ii) a And

(e) if after the first predetermined number of cycles NC1, Δ T_SWTHR1 or less, operations (a) - (d) of NC1 cycle are repeated.

17. The method of claim 16, wherein when the second predetermined number of cycles NC2 further includes a plurality of sub-cycles, updating Δ by the compensation processor in each of the plurality of sub-cycles_calcTo associate a corresponding forgetting factor.

18. The method of claim 16, wherein operations performing further comprises:

(f) if after NC2 cycles, Δ_calcIs greater than THR1, Δ is updated for a third predetermined number of cycles NC3_calc0; and

(g) if after NC2 cycles, Δ_calcIs equal to or less than THR1, the operations (a) - (d) of the NC1 cycle are repeated.

19. The method of claim 16The compensation processor includes an error calculation circuit configured to respond to an error signal and having a cycle period T_SWHas a cycle period T_{SW_M}Is measured, a delta is calculated_calc。

20. The method of claim 14, wherein the phase deviation Δ Τ_SW＝∑Δ_i.Δ_i＝Δ_i-1+(T_SW-T_{SW_Mi}) Where i is the ith pulse of the measured pulse modulated signal after the transient, i is 1,2, … N.

Technical Field

Various implementations relate generally to power converters.

Background

Electronic devices receive power in a variety of ways. For example, consumer electronic devices may receive power from a wall outlet (e.g., mains power) or various types of portable sources (e.g., batteries, renewable energy sources, generators). Devices powered by batteries have a run time that depends on the battery capacity and the average current consumption. Manufacturers of battery powered devices strive to reduce the average battery current of their products in order to provide longer device life between battery replacement or charging operations. In some examples, manufacturers of mains-powered equipment strive to improve the power efficiency of their products in order to minimize thermal loads and/or maximize the per watt performance of the consumed power.

In some electronic devices, the input supply voltage (e.g., battery input, rectified mains supply, intermediate dc power) may be converted to a different voltage via various types of voltage conversion circuitry. A switching mode power supply as a voltage conversion circuit is favored for its high efficiency and is therefore often applied to various types of electronic equipment.

Switched mode power supplies employ switching devices that switch voltages with very low resistance when on and very high resistance when off. The switch mode power supply may charge the output inductor for a period of time and may discharge some or all of the inductor energy for a subsequent period of time. The output energy may be transferred to an output capacitor bank, which may provide filtering to generate a dc output voltage. In a buck derived switched mode power supply, the steady state output voltage is approximated as the input voltage multiplied by the duty cycle, which is the continuous on time of the freewheeling switch divided by the total on and off time of the freewheeling switch for one switching cycle.

Disclosure of Invention

The present invention is directed to a method and apparatus for stabilizing control of a power converter to overcome one or more of the problems of the prior art.

One aspect of the present invention is to provide an apparatus, comprising:

a feedback error compensator configured to generate a first compensation signal in response to an error signal associated with a parameter of a controlled circuit of the digital feedback system;

a compensation processor configured to perform an operation by responding to the transient state, maintain the average switching frequency over a predetermined N cycles, thereby compensating the error signal and generating a second compensation signal; wherein the second compensation signal is a calculated phase deviation delta_calcIs calculated as a function of_calcIs the true phase deviation Δ T_SWHas a cycle period T before the transient_SWHas a cycle period T after the transient state and a stable pulse molding signal_{SW_M}The difference between the measured pulse-molding signals; and

a combining module configured to combine the first compensation signal and the second compensation signal to generate a control signal received by the digital feedback system; wherein the digital feedback system outputs a control signal generated in response to a period of the measured pulse-molding signal.

Wherein the operations include:

(f) determining the true phase deviation Δ T_SW；

(g) If Δ T_SWLess than or equal to the predetermined threshold THR1, Δ is updated_calc0; and is

(h) If Δ T_SWGreater than THR1, for the first predetermined number of cycles NC1, by adding Δ T_SWUpdating Δ in each cycle_calc。

Wherein the operations further comprise:

(i) if after the first predetermined number of cycles NC1, Δ T_SWGreater than THR1, the Δ in each cycle is updated by multiplying by a user predetermined forgetting factor for a second predetermined number of cycles NC2_calc(ii) a And

(j) if after NC1 cycles, Δ T_SWTHR1 or less, operations (a) - (d) of NC1 cycle are repeated.

Wherein the second predetermined number of cycles NC2 further comprises a plurality of sub-cycles, and the compensation processor configuration may update the delta in each of the sub-cycles_calcTo associate a corresponding forgetting factor.

Wherein the operations further comprise:

(f) if after a predetermined number of cycles NC2, Δ_calcIs greater than THR1, Δ is updated for a third predetermined number of cycles NC3_calc0; and

(g) if after NC2 cycles, Δ_calcIs equal to or less than THR1, the operations (a) - (d) of the NC1 cycle are repeated.

Wherein the compensation processor further comprises:

an error calculation circuit, configured to respond to the error signal, having a cycle period T_SWHas a cycle period T_{SW_M}Is measured, a delta is calculated_calc。

Wherein the error calculation circuit is further configured to calculate delta in response to a user predetermined forgetting factor_calc。

Wherein the phase deviation Delta T_SW＝∑Δ_i.Δ_i＝Δ_i-1+(T_SW-T_{SW_Mi}) Where i is the ith pulse of the measured pulse modulated signal after the transient, i is 1,2, … N.

Wherein the compensation processor further includes a fast gain path circuit configured to receive the error signal and generate an amplified voltage error signal.

Wherein the fast gain path circuit further includes a low pass filter configured to filter the error signal and an amplification circuit configured to amplify the filtered error signal.

Wherein the amplification circuit further comprises a first selection circuit configured to enable or disable the fast gain path circuit.

Wherein the amplifying circuit further comprises an amplifier configured to amplify the filtered error signal using a first gain value when the voltage error signal is positive and to amplify the filtered error signal using a second gain value when the voltage error signal is negative.

Wherein the first gain value is different from the second gain value.

Another aspect of the present invention is to provide a method for configuring a quantum charge modulator, including:

generating a first compensation signal by a feedback error compensator in response to an error signal associated with a controlled circuit parameter of the digital feedback system;

compensating the error signal by performing an operation to maintain the average switching frequency over a predetermined number N of cycles in response to the transient, thereby generating a second compensation signal via the compensation processor; and

combining the first compensation signal and the second compensation signal to generate a control signal received by the digital feedback system; wherein the digital feedback system outputs a control signal generated in response to a period of the measured pulse-molding signal.

Wherein the second compensation signal is a calculated phase deviation delta_calcIs calculated as a function of_calcIs the true phase deviation Δ T_SWHas a cycle period T before the transient_SWHas a cycle period T after the transient state and a stable pulse molding signal_{SW_M}The difference between the measured pulse molding signals.

Wherein the performing further comprises:

(a) determining the true phase deviation Δ T_SW；

(b) If Δ T_SWLess than or equal to the predetermined threshold THR1, Δ is updated_calc0; and

(c) if Δ T_SWGreater than THR1, for the first predetermined number of cycles NC1, by adding Δ T_SWUpdating delta_calc。

Wherein the performing further comprises:

(d) if after the first predetermined number of cycles NC1, Δ T_SWGreater than THR1, Δ may be updated by multiplying by a user predetermined forgetting factor for a second predetermined number of cycles NC2_calc(ii) a And

(e) if after the first predetermined number of cycles NC1, Δ T_SWTHR1 or less, operations (a) - (d) of NC1 cycle are repeated.

Wherein when the second predetermined number of cycles NC2 further includes a plurality of sub-cycles, Δ is updated by the compensation processor in each of the plurality of sub-cycles_calcTo associate a corresponding forgetting factor.

Wherein the operation execution further comprises:

(f) if after NC2 cycles, Δ_calcIs greater than THR1, Δ is updated for a third predetermined number of cycles NC3_calc0; and

(g) if after NC2 cycles, Δ_calcIs equal to or less than THR1, the operations (a) - (d) of the NC1 cycle are repeated.

Wherein the compensation processor includes an error calculation circuit configured to respond to the error signal and having a cycle period T_SWHas a cycle period T_{SW_M}Is measured, a delta is calculated_calc。

Wherein the phase deviation Delta T_SW＝∑Δ_i.Δ_i＝Δ_i-1+(T_SW-T_{SW_Mi}) Where i is the ith pulse of the measured pulse modulated signal after the transient, i is 1,2, … N.

These features and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments, which are illustrated in the various drawing figures.

Drawings

Fig. 1 depicts a typical quantum charge modulator compensated power converter configured to dynamically compensate in response to output transients.

Fig. 2 depicts a typical quantum charge modulator in a power converter.

Fig. 3 depicts a typical amplification circuit in a quantum charge modulator.

Fig. 4A depicts a typical behavior of a switching pulse in response to a load change in a single cycle.

Fig. 4B depicts a typical behavior of a switching pulse in response to a load change over N cycles.

Fig. 5A depicts typical simulation results of voltage recovery time in response to a rising load transient.

Fig. 5B depicts typical simulation results of voltage recovery time in response to a falling load transient.

Fig. 6 depicts a flow chart of an exemplary calculation method for the deviation between a real switching pulse and an ideal switching pulse.

Like reference symbols in the various drawings indicate like elements.

Detailed Description

Apparatus, and an associated method, involves modulating a frequency of a switching signal that achieves a fast transient response while keeping an average frequency constant over a predetermined number N of cycles. In one example, the quantum charge modulator may include a compensation processor configured to compensate the error signal and to maintain an average switching frequency over N cycles in response to transients by performing operations to generate a compensation signal. The compensation signal may be a real phase deviation Δ T_SWAs a function of the period T of the cycle before the transient_SWHas a transient post-cycle period T_{SW_M}The difference between the measured pulse modulated signals. A forgetting factor may be applied to calculate the phase deviation. The quantum charge modulator may provide uncompensated, stable, and high performance response to power stage component variations.

Various implementations may realize one or more advantages. For example, quantum charge modulators may enable power converters with stable and robust performance over a wide range of operations. The quantum charge modulator can also enable the power converter to make a fast transient response, and restrain load disturbance, such as: power stage component changes made to the user or unintentional changes due to aging and temperature variations. Some implementations may provide a simple and cost-effective power supply by applying a forgetting factor when calculating and compensating for errors, such as: the output voltage of a digital feedback system (e.g., a switched mode power supply) is erroneous. The error compensation path circuit has an error calculation circuit and an error compensator, which makes the power converter easy to use and convenient to tune. In some implementations, a forgetting factor may be advantageous to accelerate transient correction. In some implementations, the quantum charge modulator may also minimize overshoot, undershoot and/or ringing in response to load transients (e.g., step changes) in the load current. Some implementations may provide a low cost and easily designed power supply by reducing on-chip area and power consumption via quantum charge modulation. In some implementations, the power supply with the quantum charge modulator may have a higher control loop bandwidth. In some implementations, the power supply controller feedback system may have a fast enough response to transients while applying a quantum charge modulation approach that remains stable (e.g., no oscillation). The design and compensation process can thus be advantageously simplified.

The details of various implementations are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description and drawings, and from the claims.

For ease of understanding, this document structure is organized as follows. The first step, with reference to fig. 1, is briefly introduced: a typical quantum charge modulator compensated power converter is configured to dynamically compensate in response to output transients. In a second step, with reference to fig. 2-4B, the discussion turns to an exemplary implementation of the quantum charge modulator structure and the definition of the deviation between the ideal switching pulse and the real switching pulse. With reference to fig. 5A-5B, further explanatory discussion and experimental data are presented to explain the transient response improvement achieved by implementing a quantum charge modulator. Finally, with reference to fig. 6, a further explanatory discussion is presented to explain the method of calculating the deviation between the true switching pulse and the ideal switching pulse.

Fig. 1 depicts: a typical quantum charge modulator compensated power converter is configured to dynamically compensate in response to output transients. In this depicted example, the system 100 includes an electrical load system 105. The electrical load system 105 includes one or more interleaved power supplies 110, which are implemented in the computer 105 to supply one or more loads 115. In some examples, the load 115 may be specified to operate with a limited voltage disturbance input voltage. The power supply 110 includes a power converter 120. The power converter 120 regulates the current or voltage supplied to the load 115. The power converter 120 is configured to dynamically modulate the frequency of the switching signal to achieve a fast transient response while keeping the average frequency constant over a predetermined number N of cycles.

More particularly, toThe power converter 120 includes a Digital Pulse Width Modulator (DPWM)125 that controls the input to the associated power switches and reduces the output capacitance. In one example, DPWM 125 may receive constant on-time signal T_onAnd generates one or more pulse modulated signals (e.g., PWM1, PWM2, PWM3) having f_swThe duty cycle is commanded at frequency. The power converter 120 also includes a power stage 130 connected in series with the DPWM 125. The power stage 130 receives one or more clock signals from the DPWM 125. In some implementations, the power stage 130 may include a number of power switches. The power stage provides power to the load circuit 135. The load circuit has an output voltage signal (V)_out)140。

Power converter 120 also includes subtraction node 145. The subtraction node 145 receives the output voltage signal (V)_out)140 and a reference voltage signal 150. The subtraction node 145 subtracts the output voltage signal 140 from the reference voltage signal 150 and generates an error voltage signal (V)_err)155 a. In some implementations, the reference voltage signal 150 may remain constant. In other implementations, adjustments may be made to the reference voltage signal 150. The error voltage signal (V) is received by an analog-to-digital converter (ADC)160_err)155 a. ADC160 converts the error voltage signal (V)_err)155a to a digital error voltage signal 155b and sends the digital error voltage signal to a Quantum Charge Modulator (QCM) 165. the QCM 165 generates a control signal 165b and is responsive to load transients to control the DPWM 125. in various implementations, the QCM 165 may modulate the compensated signal output by a conventional linear time invariant (L TI) (e.g., a Proportional Integrator (PI)), Proportional Integral Derivative (PID) compensator module, e.g., as a function of the difference between the measured period after a transient and the pre-transient steady state operating period.

In the depicted example, power converter 120 also includes an oscillator 170. Power converter 120 is a digitally controlled power converter and oscillator 170 may be a digital Voltage Controlled Oscillator (VCO). The VCO 170 may start in Constant On Time (COT) controlAnd (5) the function of the counter. The VCO 170 receives the compensation signal from the QCM 165 and modulates the frequency of the pulse width modulated signal. In the depicted example, the VCO application has a clock frequency F_clkThe digital counter of (2).

In the depicted example, power converter 120 also includes an interleaving management block 175. The interlace management block 175 manages and splits the frequency of the pwm signal. For example, interlace management block 175 specifies a first pulse as a first phase and a second pulse as a second phase. The interleave management block 175 sends the split frequency to the DPWM 125.

The quantum charge modulator 165, digital VCO 170, and interlace management block 175 may operate as, for example, constant on-time controls. In some implementations, the quantum charge modulator 165 may be applied to systems operating at variable switching frequencies. In some implementations, a quantum charge modulator 165 may be applied to further enhance the transient response for systems operating under constant frequency control. In certain implementations, the electric load system 105 may include (by way of example and not limitation) one server, several closed-loop speed control motors.

Fig. 2 depicts a typical quantum charge modulator in a power converter. In the depicted example, the quantum charge modulator 165 includes a slow path circuit 205. The slow path circuit 205 includes a feedback error compensator 210. In some implementations, the feedback error compensator may include a proportional-integrator (PI) response. The feedback error compensator 210 receives the digital error voltage signal 155b from the ADC 160. In the depicted example, the feedback error compensator 210 may, for example, obtain an integral gain to drive the steady-state feedback error to zero in response to transients. The feedback error compensator 210 generates a first compensated signal 215.

The quantum charge modulator 165 also includes a fast gain path circuit 220, the slow path circuit 205 ensures that the output is adjusted to a DC set point over time, and the fast path circuit 220 ensures that the output is adjusted to the DC set point for fast transients the fast gain path circuit 220 receives the digital error voltage signal 155b from the ADC 160. in the depicted example, the fast gain path circuit 220 includes a low pass filter (L PF)225, the low pass filter 225 is used to clean noise generated by the digital error voltage signal 155b, the fast gain path circuit 220 also includes an amplification circuit 230, the amplification circuit 230 amplifies the noise cleaned digital error voltage signal 155c by gain and generates an amplified error signal 235. referring to FIG. 3, one example of an amplification circuit in the fast gain path circuit 220 is further elaborated.

The quantum charge modulator 165 also includes an error compensation path circuit 240. The error compensation path circuit 240 includes an error calculation circuit 245. The error calculation circuit 245 receives the digital error voltage signal 155b and the real switching signal T after the transient state_{SW_M}(e.g. load transient), ideal switching signal T before transient_SW(e.g., in steady state) and several N phases. The digital error voltage signal 155b measures the deviation of the output voltage signal 140 from a reference voltage signal 150 (e.g., a dc set point). In some implementations, the error calculation circuit 245 can be designed to have a first predetermined calculation threshold, Thr. The error calculation circuit 245 calculates the error only if the error is greater than a calculation threshold. In some implementations, the error calculation circuit 245 can also be designed to receive a forgetting factor FF. The forgetting factor FF may be a predetermined user-defined value (e.g., 60%). The forgetting factor can advantageously speed up the compensation by ignoring some portion of the error. In some implementations, the forgetting factor may be adaptively adjusted based on the error. Referring to fig. 4A and 4B, an example of calculating the error is explained in further detail. Referring to fig. 6, an example of applying a forgetting factor to calculate an error is described in further detail.

The error compensation path circuit 240 further comprises an error compensator 250. The error compensator 250 generates an under-compensated signal 255 having a modulation slope to change the frequency of the switching signal to compensate for the calculated error.

The quantum charge modulator 165 also includes a first summing node 260. The first summing junction 260 receives the amplified error signal 235 and the under-compensated signal 255 and outputs a second compensated signal 265. The quantum charge modulator 165 also includes a second summing node 270. The second summing junction 270 receives the first compensation signal 215 and the second compensation signal 265 to output the control signal 165 b.In some implementations, the first summing junction 260 and the second summing junction 270 may be combined. VCO 170 receives control signal 165 b. For example, the control signal 165b may be modulated to have a second slope m1 that is different from the first slope m of the steady-state signal. The frequency of the switching signal is then modulated. In steady state, the amplified error signal 235 and the under-compensated signal 255 are both 0. The control signal 165b generated by the second summing node 270 is equal to the first compensation signal 215 (e.g., -V_ID/T_SW*N_ph). When a transition occurs, if the error compensation path circuit 240 is not active, the first compensation signal 215 and the amplified error signal 235 will generate a signal equal to (-V)_ID/T_{SW_m}*N_ph) Control signals (e.g.: control signal 165 b). If the error compensation path circuit 240 is activated, it may modulate the control signal 165b by adding the under-compensated signal 255. The under-compensated signal 255 may be (-V)_ID/T_{SW_m}*N_ph+V_ID/(T_{SW_m}+△)*N_ph) And the sum of the first compensation signal 215 and the amplified error signal 235 may be V_ID/T_{SW_m}*N_ph。

FIG. 3 depicts an exemplary amplification circuit in a quantum charge modulator, amplification circuit 230 includes comparator 305, comparator 305 receives a digital error voltage signal to cancel noise 155c from L PF 225. comparator 305 compares digital error voltage signal to cancel noise 155c to a second predetermined threshold.

The amplification circuit 230 also includes a start block 310. The enable block 310 may be controlled to enable or disable the amplification circuit 230 in response to a user command signal En _ G. In the depicted example, the enable block 310 is an enable amplifier. The user command signal En _ G contains 0 or 1. When the user wants to activate the amplification circuit 230, the user may input a 1 to activate block 310. When a user wants to disable the amplification circuit 230, the user may enter a 0 to enable block 310. The noise-canceled digital error voltage signal 155c is amplified by either a 0 or a 1. In some implementations, the user may disable the fast gain path circuit 220 when it is desired to apply the standard compensation method under certain circumstances. For example: troubleshooting and/or system characterization. In the depicted example, enable block 310 is disposed between comparator 305 and gain amplifier 315. The gain amplifier 315 amplifies the error by a gain. In some implementations, the gain amplifier 315 may have different gains to amplify different error values. In the depicted example, gain amplifier 315 may have a first gain value 320 and a second gain value 325. First gain value 320 and second gain value 325 are received by dual-input multiplexer 330. Multiplexer 330 selects the gain value to apply to gain amplifier 315. The selection is controlled by the sign of the error. In the depicted example, the amplification circuit 230 also includes a symbol block 335. The symbol block is connected to a comparator 305 to identify the error symbol. When the error is positive, the symbol block 335 may control the multiplexer 330 to select the first gain value 320. When the error is negative, the sign block 335 may control the multiplexer to select the second gain value 325. Gain amplifier 315 applies the selected gain value to amplify the error and generate amplifier error signal 235. In some implementations, the first gain value 320 may be different than the second gain value 325.

Fig. 4A depicts a typical behavior of a switching pulse in response to a load change in one cycle. In this depicted example, the Ideal pulse width modulated signal Ideal _ PWM changes its pulse frequency when a load transient occurs. The Ideal _ PWM signal has a stable pulse period T_SW. The true power switching signal PWM has the same phase and frequency relationship as Ideal _ PWM. As the load increases, more power needs to be delivered to the load. When the error compensator 250 finds an error, the true power switching signal PWM may increase its frequency. For example, the first pulse P of the Ideal _ PWM signal₁Can be moved to the left with a first period T_{SW_M1}. For example, the first pulse P is shifted₁So as to have a first positive deviation △ from the ideal pulse width modulated signal₁，T_SW-T_{SW_M1}＝△₁. Assuming sufficient power after a cycle, the error compensator 250 will shift the second pulse P₂To compensate for the first deviation △₁. More specifically, the error compensator 250 applies the second pulse P₂Moves to the right by a first negative offset △₁Generating a second period T_{SW_M2}To keep the average stable. T is_{SW_M2}＝T_SW+△₁. The average pulse frequency remains constant.

Fig. 4B depicts a typical behavior of a switching pulse in response to a load change over N cycles. In the depicted example, the ideal pulse width modulated signal changes its pulse frequency when a large load transient occurs. A single cycle is not sufficient to complete a fall due to the presence of a heavy load transient. The ideal pulse width modulation signal has stable pulse period T_SW. As the load increases, more power needs to be delivered to the load. When the compensation circuit finds an error, the ideal pulse width modulated signal may increase its frequency. For example, the ideal pulse width modulated signal may be shifted to the left by the first pulse P₁Generating a first period T_{SW_M1}. Moving the first pulse P₁So as to have a first positive deviation △ from the ideal pulse width modulated signal₁。△₁＝T_SW-T_{SW_M1}. Assuming that the power supplied to the load is still insufficient, the compensation circuit will move the second pulse P₂To the left, by a second pulse P₂Generating a second period T_{SW_M2}. Moving the second pulse P₂Generating a second deviation △ from the ideal PWM signal₂。△₂＝2*T_SW-T_{SW_M1}-T_{SW_M2}＝(T_SW-T_{SW_M1})+(T_SW-T_{SW_M2})＝△₁+(T_SW-T_{SW_M2}) Similarly, △₃＝3*T_SW-T_{SW_M1}-T_{SW_M2}-T_{SW_M3}＝(T_SW-T_{SW_M1})+(T_SW-T_{SW_M2})+(T_SW-T_{SW_M3})＝△₂+(T_SW-T_{SW_M3}). For the ith pulse P_i,△_i＝△_i-1+(T_SW-T_{SW_Mi}) I is the ith switch modulated pulse after the transient, i 1,2, … N, the real phase deviation △ T is summed over N cycles_SW＝∑△_i。

To stabilize the system, the error compensator 250 needs to substantially force ∑ T_{SW_Mn}/N＝T_SWOr to actuate △_n0 to keep the system stable for N cycles.

Fig. 5A depicts typical simulation results of voltage recovery time in response to a rising load transient. In response to a rapid rise (e.g., a 200A current rise in the load), the supply voltage drops until the supply regulation feedback loop brings the voltage back to the programmed value. In this simulation, if only the slow path circuit 205 is used, it takes much more time (with ringing) to drop the voltage to the programmed value than if both the slow path circuit 205 and the fast gain path circuit 220 are used. In this example, the power supply implemented by the QCM largely avoids overshoot, undershoot, and ringing.

Fig. 5B depicts typical simulation results of voltage recovery times in response to a rising load transient. In response to a rapid drop (e.g., a 200A current drop in the load), the supply voltage may rise until the supply regulation feedback loop brings the voltage back to the programmed value. In this simulation, if only the slow path circuit 205 is used, it takes much more time (with ringing) to drop the voltage to the programmed value than if both the slow path circuit 205 and the fast gain path circuit 220 are used. By applying both the slow path circuit 205 and the fast gain path circuit 220, the voltage will drop in a shorter time.

The quantum charge modulator 165 may advantageously reduce the recovery time in the presence of load transients. In this example, the power supply implemented by the QCM largely avoids overshoot, undershoot and/or ringing.

FIG. 6 depicts a flow diagram of an exemplary method for calculating the deviation between a true switching pulse and an ideal switching pulse method 600 includes control logic for determining a total deviation △ T of the pulses at 605_SW(e.g.. DELTA.T)_SW-T_{SW_M}|) is less than a user-predetermined first threshold value thr 1. total deviation of pulses △ T_SWIs an ideal switching signal T_SWAnd measuring the switching signal T after a load transient_{SW_M}Pulse deviation therebetween.

If △ T_SWLess than THR1, then at 610, control logic calculates a deviation △_calcIf △ T is equal to 0_SWNot less than THR1, then at 615 the control logic introduces the first variable I and gives the variable an initial value of I-0.

At 620, control logic updates △_calc＝△_calc+△T_SW.△T_SW＝∑△_i.△_i＝△_i-1+(T_SW-T_{SW_Mi}) I is the ith switch modulation pulse after the transient, i is 1,2, … N. At 625, control logic determines whether i equals the first user-defined number of cycles NC 1. If it is not equal to NC1, control logic increments i at 630 and loops back 620.

If it equals NC1, then at 635, control logic decides △_calcIf △ is greater than THR1_calcIs greater than THR1, then at 640 the control logic introduces a second variable j and gives this variable the initial value j-0 at 645 the control logic updates △ by applying a forgetting factor FF (e.g., 20%)_calc，△_calc＝△_calc*FF+△T_SW。

At 650, the control logic determines whether the second variable j equals the second user-defined number of cycles, NC2. if it does not equal NC2, the control logic increments j at 655 and loops back 645. if it equals NC2, the control logic determines △ at 660_calcIs greater than THR 1.

If △ after 635 or 660_calcIs not greater than THR1, then at 665 the control logic introduces a third variablek and the variable is given an initial value of k 0 at 670, the control logic updates △_calc0. At 675, the control logic determines whether the third variable k equals the third user-defined number of cycles NC 3. If the third variable k is not equal to NC3, then at 680, control logic increments k and loops back to 670. If the third variable k is equal to NC3, control logic loops back 605.

If after 660 △_calcIs greater than THR1, control logic loops back 605.

In some embodiments, the second predetermined number of cycles NC2 may include a plurality of sub-cycles, each sub-cycle may take a different value FF.. in some embodiments, the deviation △ T may be based_SWUser can create a look-up table to show △ T with different deviations_SWFF suggested value of (1).

Although various implementations have been described with reference to these figures, other implementations are possible. For example, the quantum charge modulator 165 and corresponding methods may be applied to any digital feedback system. PID control is widely used in industrial process control, and its method can be applied to almost all such uses. This example is adjusting the power supply output voltage, but it may also be applied to, for example, motor speed control to adjust the motor speed to one or more reference values. By way of example, and not limitation, it may also be applied to digital feedback control systems, such as temperature control, torque control, mass or volume flow control. In some implementations, the proposed control method can be applied to systems operating under variable switching frequency (e.g., constant on-time) control. The proposed control method is applicable to constant frequency control. For example, the user may choose to enable or disable the application of the forgetting factor during the calculation. In some implementations, when a forgetting factor is applied for the calculation, the calculation can be divided into several stages. Each stage may employ a different forgetting factor. In some implementations, a look-up table can be built containing information relating to the relationship between the calculated error and the suggested forgetting factor. For example, a small forgetting factor may be selected when the error is large.