阅读说明：本技术 Crc错误警示同步 (CRC error alert synchronization ) 是由 T·K·马伊 V·J·万卡雅拉 于 2021-03-24 设计创作，主要内容包括：本公开涉及CRC错误警示同步。一种存储器装置包含循环冗余检查CRC电路,所述CRC电路经配置以指示在从主机装置到所述存储器装置的数据发射中是否已检测到错误。所述CRC电路包含同步计数器,所述同步计数器经配置以使计数与系统时钟同步且发射所述计数。所述CRC电路还包含脉冲宽度控制电路,所述脉冲宽度控制电路经配置以从所述同步计数器接收所述经同步计数且至少部分地基于所述经同步计数产生脉冲宽度控制。此外,所述CRC电路包含同步电路,所述同步电路经配置以接收所述脉冲宽度控制且至少部分地基于所述脉冲宽度控制产生错误警示信号。(The disclosure relates to CRC error alert synchronization. A memory device includes a cyclic redundancy check, CRC, circuit configured to indicate whether an error has been detected in a data transmission from a host device to the memory device. The CRC circuit includes a synchronous counter configured to synchronize a count with a system clock and transmit the count. The CRC circuit also includes a pulse width control circuit configured to receive the synchronized count from the synchronization counter and generate a pulse width control based at least in part on the synchronized count. Further, the CRC circuit includes a synchronization circuit configured to receive the pulse width control and generate an error alert signal based at least in part on the pulse width control.)

1. A memory device, comprising:

a cyclic redundancy check, CRC, circuit configured to indicate whether an error has been detected in a data transmission from a host device to the memory device, wherein the CRC circuit comprises:

a synchronization counter configured to synchronize a count with a system clock and transmit the count;

a pulse width control circuit configured to receive the synchronized count from the synchronization counter and generate a pulse width control based at least in part on the synchronized count; and

a synchronization circuit configured to receive the pulse width control and generate an error alert signal based at least in part on the pulse width control.

2. The memory device of claim 1, wherein the CRC circuit comprises a CRC detection circuit configured to:

receiving data from the host device;

receiving a checksum from the host device;

detecting a CRC error in the data based on the checksum; and

transmitting a CRC error signal in response to the detected CRC error.

3. The memory device of claim 2, wherein the synchronization counter comprises a plurality of flip-flops that count pulses of a local clock based at least in part on the system clock.

4. The memory device of claim 3, wherein the synchronization counter is configured to receive the CRC error signal from the CRC detection circuit and synchronize the CRC error signal to the system clock to generate the local clock.

5. The memory device of claim 4, wherein the synchronization counter comprises a flip-flop configured to:

receiving the CRC error signal at an input pin of the flip-flop;

receiving the system clock at a clock pin of the flip-flop; and

the local clock is output from the output of the flip-flop at each pulse of the system clock.

6. The memory device of claim 5, wherein the synchronous counter comprises a four-bit counter configured to count pulses of the local clock.

7. The memory device of claim 1, wherein the pulse width control circuit comprises a first plurality of nand gates configured to receive bits from the synchronous counter at the first plurality of nand gates.

8. The memory device of claim 7, wherein the pulse width control circuit comprises a first plurality of switches configured to switch between a true version and a complementary version of the bits.

9. The memory device of claim 7, wherein the pulse width control circuit comprises a first NOR gate configured to receive outputs from the first plurality of NAND gates.

10. The memory device of claim 9, wherein the pulse width control circuit comprises a first flip-flop configured to:

receiving an output of the first NOR gate at an input of the first flip-flop;

capturing the output of the first NOR gate with each pulse from a local clock of the synchronous counter; and

a CRC error blocking signal is output that blocks new CRC errors for a certain period of time.

11. The memory device of claim 10, wherein the pulse width control circuit comprises a second plurality of nand gates configured to receive the bit from the synchronous counter at the second plurality of nand gates.

12. The memory device of claim 11, wherein the pulse width control circuit comprises a second plurality of switches configured to switch between a true version and a complementary version of the bits.

13. The memory device of claim 12, wherein the pulse width control circuit comprises a second nor gate configured to receive an output from the second plurality of nand gates.

14. The memory device of claim 13, wherein the pulse width control circuit comprises a second flip-flop configured to:

receiving an output of the second NOR gate at an input of the second flip-flop;

capturing the output of the second NOR gate with each pulse of the local clock; and

outputting a CRC error alert pulse width signal, the CRC error alert pulse width signal controlling the width of a CRC error alert pulse.

15. The memory device of claim 14, wherein the time period is greater than the width of the CRC error alert pulse.

16. A cyclic redundancy check, CRC, circuit, comprising:

a CRC detection circuit configured to generate a CRC error signal to indicate whether an error has been detected in a data transmission from a host device to a memory device, wherein the CRC circuit comprises:

a synchronization counter configured to synchronize pulses of the CRC error signal with a system clock, generate a local clock based on the pulses of the CRC error signal and the system clock, and transmit bits of a counter of the local clock;

a pulse width control circuit configured to receive the bit and a local clock from the synchronous counter and to generate a pulse width control based at least in part on the bit and the local clock; and

a synchronization circuit configured to receive the pulse width control and generate an error alert signal based at least in part on the pulse width control.

17. The CRC circuit of claim 16, wherein the synchronization circuit is configured to synchronize the error alert signal with the system clock.

18. The CRC circuit of claim 16, wherein the pulse width control comprises a CRC error alert pulse width signal configured to set a pulse width of the error alert signal, and a CRC alert blocking signal configured to block new CRC errors in a period longer than the pulse width of the error alert signal.

19. A method, comprising:

detecting a CRC error in data received from the host device using a CRC detection circuit;

generating a CRC error signal based on the detection of the CRC error;

synchronizing pulses of the CRC error signal with a system clock using a synchronization counter to generate a local clock based on the pulses of the CRC error signal and the system clock;

receiving bits of a counter of the local clock and the local clock from the synchronous counter using a pulse width control circuit;

generating, using the pulse width control circuit, a pulse width control based at least in part on the bit and the local clock; and

a synchronization circuit is used to receive the pulse width control and generate an error alert signal based at least in part on the pulse width control.

20. The method of claim 19, wherein generating the error alert signal comprises synchronizing the error alert signal to the system clock.

Technical Field

Embodiments of the present disclosure generally relate to the field of semiconductor devices. More particularly, embodiments of the present disclosure relate to synchronization of Cyclic Redundancy Check (CRC) alerts in memory devices.

Background

The memory device may write data to the memory device using a write command. Typically, a Cyclic Redundancy Check (CRC) is a feature in Dynamic Random Access Memory (DRAM) memory devices. The CRC is an error detection code to detect unexpected changes of original data. In other words, the CRC may be able to detect changes in the data to be written in the write command during transmission. When there is a mismatch between the write data and the checksum bits provided by the host device/controller, an error (i.e., a CRC error) has occurred. In response to the CRC error, the memory device may drive the alert signal to a value (e.g., "0") for the number of clock cycles defined by the specification for the memory device. For example, the number of clock cycles may be between 12-20 clock cycles on a double data rate type 5(DDR5) Dynamic Random Access Memory (DRAM) device and 6-10 clock cycles on a double data rate type 4(DDR4) DRAM device. Furthermore, the maximum duration of time that the alert signal is held to that value may be used to prevent holding too long in the event of many back-to-back CRC errors. Thus, the memory device may skip the drive alert for some occurrences of CRC errors. However, the memory device and the host device should coordinate/predict when the memory device will skip or drive the alert after the first CRC error. When skipped/driven alerts are not properly coordinated or predicted, the design verification automation process may degrade, verification time increases, and/or general coordination between the host device and the memory device may be inhibited.

Embodiments of the present disclosure may be directed to one or more of the problems set forth above.

Disclosure of Invention

In one aspect, the present disclosure relates to a memory device comprising: a Cyclic Redundancy Check (CRC) circuit configured to indicate whether an error has been detected in a data transmission from a host device to the memory device, wherein the CRC circuit comprises: a synchronization counter configured to synchronize a count with a system clock and transmit the count; a pulse width control circuit configured to receive the synchronized count from the synchronization counter and generate a pulse width control based at least in part on the synchronized count; and a synchronization circuit configured to receive the pulse width control and generate an error alert signal based at least in part on the pulse width control.

In another aspect, the present disclosure is directed to a Cyclic Redundancy Check (CRC) circuit comprising: a CRC detection circuit configured to generate a CRC error signal to indicate whether an error has been detected in a data transmission from a host device to a memory device, wherein the CRC circuit comprises: a synchronization counter configured to synchronize pulses of the CRC error signal with a system clock, generate a local clock based on the pulses of the CRC error signal and the system clock, and transmit bits of a counter of the local clock; a pulse width control circuit configured to receive the bit and a local clock from the synchronous counter and to generate a pulse width control based at least in part on the bit and the local clock; and a synchronization circuit configured to receive the pulse width control and generate an error alert signal based at least in part on the pulse width control.

In yet another aspect, the present disclosure relates to a method comprising: detecting a CRC error in data received from the host device using a CRC detection circuit; generating a CRC error signal based on the detection of the CRC error; synchronizing pulses of the CRC error signal with a system clock using a synchronization counter to generate a local clock based on the pulses of the CRC error signal and the system clock; receiving bits of a counter of the local clock and the local clock from the synchronous counter using a pulse width control circuit; generating, using the pulse width control circuit, a pulse width control based at least in part on the bit and the local clock; and receiving the pulse width control using a synchronization circuit and generating an error alert signal based at least in part on the pulse width control.

Drawings

FIG. 1 is a simplified block diagram illustrating certain features of a memory device having a Cyclic Redundancy Check (CRC) circuit, according to an embodiment of the present disclosure;

FIG. 2 is a block diagram of a CRC circuit of the memory device of FIG. 1 with a CRC detection circuit and a CRC alert circuit, according to an embodiment of the present disclosure;

FIG. 3 is a graph showing a CRC error detection signal and a CRC alert signal using the CRC circuit of FIG. 2, according to an embodiment of the present disclosure;

FIG. 4 is a graph showing a CRC error detection signal and a CRC alert signal using the CRC circuit of FIG. 2, according to an embodiment of the present disclosure;

FIG. 5 is a graph showing a CRC error detection signal and a CRC alert signal using the CRC circuit of FIG. 2, according to an embodiment of the present disclosure;

FIG. 6 is a block diagram of the CRC circuit of FIG. 1 with a synchronization counter, a pulse width (pw) control circuit, and a synchronization circuit configured to synchronize the CRC alert to a master clock of the memory device, in accordance with embodiments of the present disclosure;

FIG. 7 is a circuit diagram of the synchronous counter of FIG. 6 according to an embodiment of the present disclosure;

FIG. 8 is a circuit diagram of the pulse width control circuit of FIG. 6 according to an embodiment of the present disclosure;

FIG. 9 is a circuit diagram of the synchronization circuit of FIG. 6, according to an embodiment of the present disclosure;

FIG. 10 is a chart showing a CRC error detection signal and a CRC alert signal using the CRC circuit of FIG. 6, according to an embodiment of the present disclosure; and

fig. 11 is a graph illustrating a CRC error detection signal and a CRC alert signal using the CRC circuit of fig. 6, according to an embodiment of the present disclosure.

Detailed Description

One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

In some embodiments, CRC circuitry may be used to perform system level parity error detection and/or CRC detection to determine when errors exist due to ambiguities that occur when clock combining and/or clock domain crossing. The CRC alert circuit may be used to send an alert from the memory device to the host device when an error occurs. In some embodiments, the CRC alert circuit may use an asynchronous ripple counter. For example, in slower clock speed specifications (e.g., DDR4), an asynchronous ripple counter may be sufficient. This is especially true when the memory device does not synchronize CRC errors with the internal clock of the memory device. CRC errors and lack of synchronization of internal clocks can prevent consistent predictions, especially for different process, voltage, and temperature (PVT) values. Thus, as discussed below, the CRC alert circuit may include a high clock frequency synchronous counter. For example, a 4-bit synchronous counter may be used to meet the n clock cycles (e.g., where n is between 12-20 clock cycles for DDR5) timing that drives the CRC alert signal. In addition, the CRC circuit may implement a high speed counter with relatively fast transistor logic gates. Further, the CRC circuit may synchronize the CRC error with an internal clock of the memory device to generate a predictable and consistent block interval for skipping CRC alerts. By accurately and consistently predicting when a DRAM device will drive or skip an alert, design verification automation processes are enhanced and verification time is reduced.

Turning now to the figures, FIG. 1 is a simplified block diagram illustrating certain features of a memory device 10. Specifically, the block diagram of FIG. 1 is a functional block diagram illustrating certain functionality of the memory device 10. According to one embodiment, the memory device 10 may be a double data rate type 5(DDR5) Synchronous Dynamic Random Access Memory (SDRAM) device. The various features of DDR5SDRAM allow for reduced power consumption, more bandwidth, and more storage capacity than previous generations of Double Data Rate (DDR) SDRAM. However, some of the CRC alert discussion herein may be applicable to other memory devices, such as DDR type 4(DDR4) SDRAM devices.

The memory device 10 may include a number of memory banks 12. For example, the bank 12 may be a DDR5SDRAM bank. The bank of memory 12 may be provided on one or more chips (e.g., SDRAM chips) arranged on a dual in-line memory module (DIMMS). Each DIMM may include a number of SDRAM memory chips (e.g., x8 or x16 memory chips), as will be appreciated. Each SDRAM memory chip may include one or more banks 12 of memory. The memory device 10 represents a portion of a single memory chip (e.g., an SDRAM chip) having a number of banks 12 of memory. For DDR5, memory banks 12 may be further arranged to form bank groups. For example, for an 8 gigabyte (Gb) DDR5SDRAM, a memory chip may include 16 banks 12 of memory arranged into 8 bank groups, each bank group including 2 banks of memory. For a 16Gb DDR5SDRAM, for example, a memory chip may include 32 banks 12 of memory arranged into 8 bank groups, each bank group including 4 banks of memory. Various other configurations, organizations, and sizes of the memory banks 12 on the memory device 10 may be utilized depending on the application and design of the overall system.

Memory device 10 may include a command interface 14 and an input/output (I/O) interface 16. Command interface 14 is configured to provide a number of signals, such as signal 15, from an external device (not shown), such as a processor or controller. The processor or controller may provide various signals 15 to the memory device 10 to facilitate the transmission and reception of data to be written to or read from the memory device 10.

As will be appreciated, the command interface 14 may include a number of circuits, such as a clock input circuit 18 and a command address input circuit 20, to ensure proper handling of the signal 15 from the host device 21. Host device 21 may include a processor and/or other device to write data to and/or receive data from memory device 10. For example, host device 21 may drive at least some operations of memory device 10. The command interface 14 may receive one or more clock signals from an external device. Generally, Double Data Rate (DDR) memories utilize a differential pair of system clock signals, referred to herein as the true clock signal (Clk _ t) and the inverted (bar) clock signal (Clk _ b). The positive clock edge of the DDR refers to the point where the rising true clock signal Clk _ t crosses the falling inverted clock signal Clk _ b, while the negative clock edge indicates the transition of the falling true clock signal Clk _ t and the rise of the inverted clock signal Clk _ b. Commands (e.g., read commands, write commands, etc.) are typically input on the positive edge of a clock signal, and data is transmitted or received on both the positive and negative clock edges.

The clock input circuit 18 receives the true clock signal (Clk _ t) and the inverted clock signal (Clk _ b) and generates the internal clock signal Clk. The internal clock signal CLK is supplied to an internal clock generator, such as a Delay Locked Loop (DLL) circuit 30. The DLL circuit 30 generates a phased internal clock signal LCLK based on the received internal clock signal CLK. The phase-controlled internal clock signal LCLK is supplied to, for example, the I/O interface 16, and is used as a timing signal for determining the output timing of the read data.

The internal clock signal/phase CLK may also be provided to various other components within the memory device 10 and may be used to generate various additional internal clock signals. For example, an internal clock signal CLK may be provided to the command decoder 32. The command decoder 32 may receive command signals from the command bus 34 and may decode the command signals to provide various internal commands. For example, the command decoder 32 may provide command signals to the DLL circuit 30 through the bus 36 to coordinate the generation of the phased internal clock signal LCLK. The phased internal clock signal LCLK may be used to clock data, for example, through IO interface 16.

Further, the command decoder 32 may decode commands such as read commands, write commands, mode register set commands, activate commands, etc., and provide access to the particular bank of memory 12 corresponding to the commands via the bus path 40. As will be appreciated, the memory device 10 may include various other decoders, such as a row decoder and a column decoder, to facilitate access to the memory bank 12. In one embodiment, each memory rank 12 includes a rank control block 22 that provides the necessary decoding (e.g., row and column decoders) as well as other features such as timing control and data control to facilitate execution of commands to and from the memory rank 12.

The memory device 10 performs operations such as read commands and write commands based on command/address signals received from an external device such as a processor. In one embodiment, the command/address bus may be a 14-bit bus (CA <13:0>) to accommodate command/address signals. The command/address signals are clocked to the command interface 14 using the clock signals (Clk _ t and Clk _ b). The command interface may include a command address input circuit 20 configured to receive and transmit commands through, for example, a command decoder 32 to provide access to the bank of memory 12. In addition, the command interface 14 may receive a chip select signal (CS _ n). The CS _ n signal enables the memory device 10 to process commands on the incoming CA <13:0> bus. Access to a particular bank 12 within memory device 10 is encoded on the CA <13:0> bus by a command.

In addition, the command interface 14 may be configured to receive a number of other command signals. For example, command/address (CA ODT) signals on the die terminals may be provided to facilitate proper impedance matching within the memory device 10. For example, a RESET command (RESET _ n) may be used during power up to RESET the command interface 14, status registers, state machine, and so forth. Command interface 14 may also receive command/address inversion (CAI) signals that may be provided to invert the state of command/address signals CA <13:0> on the command/address bus, e.g., depending on the command/address routing of the particular memory device 10. An image (MIR) signal may also be provided to facilitate the image function. Based on the configuration of the multiple memory devices in a particular application, the MIR signals can be used to multiplex the signals so that they can be swapped for achieving a particular routing of the signals to the memory device 10. Various signals to facilitate testing of the memory device 10 may also be provided, such as a Test Enable (TEN) signal. For example, the TEN signal may be used to put the memory device 10 into a test mode for connectivity testing.

The command interface 14 may also be used to provide an ALERT signal (ALERT _ n) to the system processor or controller for certain errors that may be detected. For example, an ALERT signal (ALERT _ n) may be transmitted from the memory device 10 if a Cyclic Redundancy Check (CRC) error is detected. Other alert signals may also be generated. Further, the bus and pins used to transmit the ALERT signal (ALERT _ n) from the memory device 10 may be used as input pins during certain operations, such as the connectivity test mode performed using the TEN signal as described above.

As illustrated in FIG. 1, the I/O interface 16, the command decoder 32, and/or the data path 46 may include a CRC circuit 48 that may be used to evaluate received data to determine whether a transmission error is detected as a CRC error. CRC circuit 48 may also be used to drive an alert signal. For example, CRC circuit 48 may be used to consistently predict CRC pulse driving and skipping even at different process, voltage, and temperature (PVT) values.

Data may be sent to and from memory device 10 using the command and timing signals discussed above by transmitting and receiving data signals 44 through IO interface 16. More specifically, data may be sent to or retrieved from the memory bank 12 through a data path 46 including a plurality of bidirectional data buses. Data IO signals, commonly referred to as DQ signals, are typically transmitted and received in one or more bidirectional data buses. For certain memory devices, such as DDR5SDRAM memory devices, the IO signal may be divided into upper and lower bytes. For example, for an x16 memory device, the IO signals may be divided into upper and lower IO signals (e.g., DQ <15:8> and DQ <7:0>) corresponding to, for example, the upper and lower bytes of data signals.

To allow for higher data rates within the memory device 10, certain memory devices, such as DDR memory devices, may utilize a data strobe signal, commonly referred to as the DQS signal. The DQS signal is driven by an external processor or controller that sends data (e.g., for write commands) or by the memory device 10 (e.g., for read commands). For read commands, the DQS signal is effectively an additional data output (DQ) signal having a predetermined pattern. For write commands, the DQS signal is used as a clock signal to capture corresponding input data. Like the clock signals (Clk _ t and Clk _ b), the DQS signal may be provided as a differential pair of data strobe signals (DQS _ t and DQS _ b) to provide differential pair signaling during reads and writes. For certain memory devices, such as DDR5SDRAM memory devices, the DQS signal of the differential pair may be divided into upper and lower data strobe signals (e.g., UDQS _ t and UDQS _ b; LDQS _ t and LDQS _ b) corresponding to, for example, the upper and lower bytes of data sent to and from the memory device 10.

An impedance (ZQ) calibration signal may also be provided to memory device 10 through IO interface 16. The ZQ calibration signal may be provided to a reference pin and used to tune the output driver and ODT values by adjusting the pull-up and pull-down resistors of the memory device 10 in changes in PVT values. Because PVT characteristics may affect the ZQ resistor values, a ZQ calibration signal may be provided to the ZQ reference pin for adjusting the resistance to calibrate the input impedance to a known value. As will be appreciated, a precision resistor is typically coupled between the ZQ pin on the memory device 10 and GND/VSS external to the memory device 10. This resistor serves as a reference for adjusting the drive strength of the internal ODT and IO pins.

In addition, a LOOPBACK signal (LOOPBACK) may be provided to memory device 10 through IO interface 16. The loopback signal may be used during a test or debug phase to place the memory device 10 in a mode in which signals loop back through the memory device 10 through the same pin. For example, the loopback signal may be used to set the memory device 10 to test the data output (DQ) of the memory device 10. Loopback may include both data pins and strobes or may include only data pins. This is generally intended to monitor data captured by memory device 10 at IO interface 16.

As will be appreciated, various other components such as power supply circuitry (for receiving external VDD and VSS signals), mode registers (to define various modes of programmable operation and configuration), read/write amplifiers (to amplify signals during read/write operations), temperature sensors (for sensing the temperature of the memory device 10), and the like, may also be incorporated into the memory device 10. Accordingly, it should be understood that only the block diagram of FIG. 1 is provided to highlight certain functional features of memory device 10 to facilitate the subsequent detailed description.

Fig. 2 is a simplified block diagram of CRC circuit 48 of fig. 1. As illustrated, CRC circuit 48 receives a data signal 50 (e.g., a DQ signal) and one or more CRC bits 52 from a host device at CRC detection circuit 54. CRC detection circuit 54 may also receive one or more additional signals such as a CRC enabled mode register value, a CRC setting, and the like. CRC detection circuit 54 uses data signal 50 and CRC bits 52 to detect whether a CRC error has occurred. Thus, the CRC detection circuit 54 outputs a CRC error (CRCerr) signal 56 indicating whether the CRC detection circuit 54 has detected a CRC error.

The CRC ALERT circuit 58 receives the CRCerr signal 56 and outputs an ALERT (errart) signal 60 (e.g., ALERT _ n) to the host device to indicate detection of a CRC error. The CRC alert circuit 58 may include a counter 62 for predicting and/or controlling the transmission of the errart signal 60. The counter 62 may be synchronized with the master clock (Clk _ t) of the memory device 10 or may be delay based and asynchronous with the master clock. However, due to the specified pulse width of the CRCerr signal 56 specified in the specification (e.g., DDR4 or DDR5) and the lack of synchronization of the CRC alert with the master clock of the memory device 10, subsequent CRC errors may not be able to be consistently sent and/or captured in the CRC alert circuit 58.

For example, fig. 3 illustrates a graph 68 using the asynchronous counter 62 that yields consistent results, with every other error skipped. Graph 68 includes a line 70 representing the master clock of memory device 10. Plot 68 also includes a line 72 corresponding to CRCerr signal 56 indicating when a CRC error has been detected in CRC detection circuit 54. Plot 68 also includes a line 74 corresponding to ErrAlert signal 60, which is configured to indicate to the host device that a CRC error has been detected. Using the asynchronous counter 62, the crcert signal 56 and the errallert signal 60 may be delay-based.

In the simulation performed to generate the graph 68, the CRCerr signal 56 occurs every n (e.g., 6) cycles of the line 70. In some specifications (e.g., the DDR4 specification) the memory device 10 may set the pulse width 76 to a number (e.g., 6-10) cycles of the line 70. In graph 68, every other pulse of the CRCerr signal 56 is used to transmit a pulse on the errerlert signal 60 while skipping the other pulses. For example, pulse 78 of CRCerr signal 56 is used to transmit pulse 80 of errallert signal 60 having pulse width 76. Since the errerlert signal 60 is still asserted when the pulse 82 of the CRCerr signal 56 is received, the pulse 82 is skipped. Similarly, the pulse 82 of the CRCerr signal 56 is used to transmit the pulse 84 of the errerlert signal 60 while skipping the pulse 86 of the CRCerr signal 56 and the pulse 88 of the CRCerr signal 56 is used to transmit the pulse 90 of the errerlert signal 60. Thus, the output of the ErrAlert signal 60 is consistent and predictable as to which errors are skipped and which are recorded.

Fig. 4 illustrates a graph 100 using the asynchronous counter 62 that yields inconsistent results. Graph 100 includes line 70. In addition, graph 100 includes a line 102 corresponding to the CRCerr signal 56 indicating when a CRC error has been detected in CRC detection circuit 54. Graph 100 also includes a line 103 corresponding to ErrAlert signal 60 configured to indicate to the host device that a CRC error has been detected.

In the simulation performed to generate the graph 100, the CRCerr signal 56 occurs every m (e.g., 7) cycles of the line 70. In some specifications (e.g., the DDR4 specification) the memory device 10 may set the pulse width 104 to a number (e.g., 6-10) cycles of the line 70. In graph 100, pulse 106 of CRCerr signal 56 is used to transmit pulse 108 of errart signal 60 having pulse width 104. The next pulse 110 of the CRCerr signal 56 is used to transmit a pulse 112 of the errerlert signal 60. Since the errerlert signal 60 is still asserted when the pulse 114 of the CRCerr signal 56 is received, the pulse 114 is skipped. However, the pulses 116 of the CRCerr signal 56 are used to transmit the pulses 118 of the errerlert signal 60. Thus, the output of the ErrAlert signal 60 is inconsistent and unpredictable as to which errors are skipped and which are recorded, with pulses 106, 110 and 116 being recorded and pulse 114 being skipped.

Fig. 5 illustrates a graph 120 using the asynchronous counter 62 that yields inconsistent results. Graph 120 includes line 70. In addition, graph 120 includes a line 121 corresponding to the CRCerr signal 56 indicating when a CRC error has been detected in the CRC detection circuit 54. Graph 120 also includes a line 122 corresponding to ErrAlert signal 60, which is configured to indicate to the host device that a CRC error has been detected.

In the simulation performed to generate the graph 120, the CRCerr signal 56 occurs every m (e.g., 8) cycles of the line 70. In some specifications (e.g., the DDR4 specification) the memory device 10 may set the pulse width 123 to a number (e.g., 6-10) cycles of the line 70. In graph 120, pulse 124 of CRCerr signal 56 is used to transmit pulse 126 of errart signal 60 having pulse width 123. The next pulse 128 of the CRCerr signal 56 is used to transmit a pulse 130 of the errart signal 60, and the pulse 132 of the CRCerr signal 56 is used to transmit a pulse 134 of the errart signal 60. Since the errerlert signal 60 is still asserted when the pulse 136 of the CRCerr signal 56 is received, the pulse 136 is skipped. However, the pulse 138 of the CRCerr signal 56 is used to transmit the pulse 140 of the errerlert signal 60. Thus, the output of the ErrAlert signal 60 is inconsistent and unpredictable as to which errors are skipped and which are recorded, with pulses 124, 128, 132, and 138 being recorded and pulse 136 being skipped.

One method of increasing consistency in the operation of CRC circuit 48 includes using a synchronous counter that synchronizes the count to the master clock that controls the pulse width of errallert signal 60. For example, fig. 6 illustrates a block diagram of a CRC alert circuit 58 using a master Clock (CLK)150 (e.g., CLK _ t in fig. 1) having a synchronous counter 152 that generates a count 154 that is synchronous with CLK 150. The PW control circuit 156 is used to set the pulse width control 158 for the errallert signal 60. The synchronization circuit 160 synchronizes the CRCerr signal 56 with the CLK 150 and outputs the errallert signal 60 using the pulse width control 158.

Fig. 7 is a schematic diagram of an embodiment of the sync counter 152. As illustrated, the synchronous counter 152 includes a clock circuit 170 that receives CLK 150 at a clock pin of a flip-flop 174. Flip-flop 174 also receives a CRC enable signal (CRCErrD)178 that enables or disables CRC functionality. The flip-flop 174 also uses a power on (PwrUp) signal 176 to reset the flip-flop 174 after power cycling of the memory device 10. Based on CRCErrD 178 and CLK 150, flip-flop 174 outputs a local clock true (CKT)180 and/or a local clock complement (CKC)182 using one or more inverters/amplifiers 183. By using flip-flop 174, CKT 180 and CKC 182 are output only when CRC is enabled, thereby reducing power consumption of CRC circuit 148 when CRC is not enabled for memory device 10.

The synchronous counter 152 uses CKT 180 and CKC 182 to control the latching of flip-flops 186, 188, 190, and 192, which are used to implement the synchronous counter 152 as a four-bit counter that is synchronized with CLK 150 via CKT 180 and CKC 182. However, in some embodiments, the synch counter 152 may include any suitable number of bits and corresponding flip-flops. The flip-flops 186, 188, 190, and 192 may also use the reset signal (ResetF signal) 184 to reset the count. In some embodiments, ResetF signal 184 may be generated in PW control circuit 156.

In the synchronous counter 152, the output (Count <0>)194 of the flip-flop 186 is inverted using an inverter 196 to generate a CountF <0>198 that is fed back into the flip-flop 186 to invert the Count <0>194 on the next clock cycle. Count <0>194 and Count f <0>198 are transmitted to a multiplexer 200 that selectively passes Count <0>194 or Count f <0>198 as inputs to flip-flop 188. The output Count <1>202 is used to generate a CountF <1>204 that is inverted using inverter 205. The multiplexer 200 is controlled using Count <1>202 and/or CountF <1> 204.

Synch counter 152 also transmits Count <0>194 and Count <1>202 to nand gate 207 to generate Count0and1F signal 206. The Count0and1F signal 206 is transmitted to an inverter 208 to generate a Count0and1 signal 210.

The multiplexer 211 receives the Count0and1F signal 206 and the Count0and1 signal 210 and transmits an output to the flip-flop 190. The output Count <2>212 is output from the flip-flop 190 based on the output from the multiplexer 211. Count <2>212 is used to generate CountF <2>214 using inverter 216. The output of the multiplexer 211 is controlled using Count <2>212 and/or CountF <2> 214.

CountF <2>214 also transmits to NOR gate 218, which also receives a Voltage (VSS)220 (e.g., 0V). The output of the NOR gate 218 is transmitted along with the Count0and1 signal 210 to the NAND gate 222 to generate the Count012F signal 224. The Count012F signal 224 and voltage 220 are also transmitted to a multiplexer 226 used to generate an input to the flip-flop 192. The output Count <3>228 and the complementary CountF <3>230 are used to control the output of the multiplexer 226. Inverter 232 may be used to generate CountF <3>230 from Count <3> 228. Count <3>228, Count <2>212, Count F <2>214, Count <1>202, Count F <1>204, Count <0>194, and Count F <0>198 may be part of the Count 154 passed from the synchronous counter 152 to the PW control circuit 156.

As previously discussed, the PW control circuit 156 uses the count 154 to set the pulse width control 158 of the errallert signal 60. Fig. 8 is a schematic diagram of an embodiment of PW control circuit 156. The PW control circuit 156 includes a block circuit 233 configured to generate a Q0_ block signal 235, and includes a pulse width circuit 234 configured to generate a Q0_ PW signal 236.

The block circuit 233 receives Count <3>228, Count <2>212, Count <1>202, countF <1>204, Count <0>194, and countF <0> 198. Switch 238 is used to select between transmitting Count <3>228 and a Voltage (VPERI)239 (e.g., a logic high) along with Count <2>212 to nand gate 240. Similarly, switch 242 is used to select between transmit Count <1>202 and CountF <1>204, and switch 244 is used to select between transmit Count <0>194 and CountF <0> 198. Switches 242 and 244 are configured to control which inputs are transmitted to nand gate 246. The outputs of the nand gates 240 and 246 are combined using a nor gate 248. The output of the NOR gate 248 is transmitted to a flip-flop 250 that uses CKT 180 and CKC 182 to strobe the latching of the output of the NOR gate 248 while using the ResetF signal 184 to control the resetting of the flip-flop 250. The flip-flop 250 outputs a Q0_ block signal 235.

Pulse width circuitry 234 receives Count <3>228, Count <2>212, Count F <2>214, Count <1>202, Count F <1>204, Count <0>194, and Count F <0> 198. Switch 252 is configured to select between voltage 239 and Count <3>228, and switch 254 is configured to select between Count <2>212 and CountF <2> 214. The outputs of switch 252 and switch 254 are transmitted to nand gate 256. Similarly, switch 258 is used to select between transmit Count <1>202 and CountF <1>204, and switch 260 is used to select between transmit Count <0>194 and CountF <0> 198. Switches 258 and 260 are configured to control which inputs are transmitted to nand gate 262. The outputs of the nand gates 256 and 262 are combined using a nor gate 264. The output of the NOR gate 264 is transmitted to a flip-flop 266 that uses CKT 180 and CKC 182 to strobe the latching of the output of the NOR gate 264 while controlling the resetting of the flip-flop 266 using the ResetF signal 184. Flip-flop 266 outputs Q0_ pw signal 236. The Q0_ block signal 235 counts more clock cycles than the Q0_ pw signal 236. This additional count ensures that the duration of blocking new CRC errors using the Q0_ block signal 235 is longer than the pulse width set using the Q0_ pw signal 235 to ensure glitch-free operation. Thus, any new CRC errors will be blocked when the CRC error alert pulse is in progress, which is critical in accurately predicting when the next CRC error will be recognized.

Fig. 9 is a schematic diagram of synchronization circuit 160. Synchronization circuit 160 receives CRCErrEndF 267, which is used to disable sync counter 152 at the end of the CRC detection and alert process. NAND gate 268 receives CRCERREndF 267 and PwrUp signal 176. The output of NAND gate 268 is transmitted to inverter 255 and then to a corresponding set of pins of flip-flops 269, 270 and 271. The flip-flop 269 receives crcerrddf 272. Crcerrddf 272 is a timing signal synchronized with CKT 180 and CKC 182. Crcerrddf 272 is latched into flip-flop 269 using CKT 180 and CKC 182. When latched, crcerrddf 272 is output to flip-flop 270 after a cyclic delay as CRCErrD 1F. Similarly, CRCErrD1F is latched into flip-flop 270 and output to flip-flop 271 as CRCErrD2F after another cycle delay. Similarly, CRCErrD2F is latched into flip-flop 271 and output to switch 273 as CRCErrD3F after another cycle delay. CRCErrD1F, CRCErrD2F, and CRCErrD3F transmit to switch 273 for selecting between CRCErrD1F, CRCErrD2F, and CRCErrD 3F. The selected timing signal with the appropriate amount of delay is used as the ResetF signal 184 to reset/enable/disable the synchronous counter 152, as described above with respect to fig. 7. In some embodiments, the ResetF signal 184 is amplified and/or inverted using inverter 274.

Synchronization circuit 160 also receives Q0_ block signal 234 and CRCErrSet275 at nand gate 276. CRCErrSet275 is used to ignore any new CRC errors when the errerlert signal 60 is active. CRCErrSet275 may be reset by Q0_ pw signal 236. The nand operation of the Q0_ block signal 234 and CRCErrSet275 in nand gate 276 produces CRCErrEndF 267 for use in nand gate 268. CRCErrEndF 267 and PwrUp signals 176 are transmitted to multiplexer 277 along with CRCErrI 278. CRCErrI278 is used to start the synch counter 152 and CRC alert process by enabling the synch counter 152 and counting clock cycles for the errerlert signal 60. The output of multiplexer 277 is passed to the set pin of SR flip-flop 279. The reset pin of SR flip-flop 279 is connected to CRCErrI 278. The output of SR flip-flop 279 is CRCErrD 280 which is a CRC error disable signal. CRCErrD 280 is transmitted to inverter 282 to produce crcerrddf 272. Crcerrbdf 272 is transmitted to inverter 284 to produce CRCErrSet 275. CRCErrSet275 is used to ignore any new CRC errors when the errerlert signal 60 is in progress. Using the above described circuit, CRCErrSet275 is set by CRCErrI278 and reset by Q0_ block 235.

Synchronization circuit 160 also includes a nand gate 286 that receives Q0_ pw signal 236 and CRCErrSet 275. CRCErrSet275 and PwrUP signal 176 are transmitted to multiplexer 288 along with CRCErrI 278. The output of the multiplexer 288 is passed to the set pin of the SR flip-flop 290. The reset pin of the SR flip-flop 290 is connected to CRCErrI 278. The output of the SR flip-flop 290 is transmitted to an inverter 292 configured to output CRCErrF _ PW 294. CRCErrF _ PW 294 determines the pulse width of errallert signal 60. CRCErrF _ PW 294 is set by CRCErrI278 and reset by Q0_ PW signal 236.

CRCErr1clk 296 transmits to flip-flop 298. As mentioned below, CRCErr1clk 296 is a pulse generated from the CRCErr signal 56 and having a width of at least 1 clock cycle, such that CRCErr1clk 296 may be latched and synchronized to CKT 180. Flip-flop 298 is latched using CLK 150 (e.g., the master clock of memory device 10). CLK 150 may also be inverted in inverter 300 to generate CLKf 302, which is used as a differential clock to assist in the latching of CRCErr1CLK 296 in flip-flop 298. Flip-flop 298 outputs CRCErr _1clkd 304, which is a delayed version of CRCErr _1CLK 296 delayed by the clock cycle of CLK 150. CRCErr _1clkd 304 is transmitted to flip-flop 306, which is also latched using CLK 150 and CLKf 302. The PwrUp signal 176 may be used to reset the flip-flops 298 and 306 when the memory device 10 is powered up. The output of the flip-flop 306 is transmitted to a pulse generator 308. For example, pulse generator 308 may be a haplotype pulse generator. The pulse generator 308 outputs crcerrppulsef 310, which is an error signal synchronized to CLK 150. Crcerrppulsef 310 transmits to nor gate 312 to produce CRCErrI 278. Nor gate 312 also receives CRCErrSetDly 314, which is a delayed version of CRCErrSet275 via delay 316. In some embodiments, CRCErrSet275 may be inverted via one or more inverters 318 to generate CRCErrSetDly 314.

The delayed version of crcerrppulsef 310, delayed using delay 322, and PwrUp signal 176 are transmitted to the set pin of SR flip-flop 324. The reset pin of the SR flip-flop 324 receives a pulse generated from the pulse generator 326 based at least in part on the CRCErr signal 56. The pulse generator 326 may comprise a unitary pulse generator. The output of the SR flip-flop 324 is CRCErr1clk 296. CRCErr1clk 296 is transmitted to nand gate 328 along with the inversion of CRCErrSetDly 314 inverted in inverter 327. The output of NAND gate 328 is transmitted to NAND gate 330, which performs a NAND operation along with CRCErrF _ PW 294. The output of nand gate 330 is transmitted to switch 332 to select between the output of nand gate 330 and voltage 220. The selected value in switch 332 is transmitted to inverter 334. The inverted value from inverter 334 is transmitted to switch 336 which is used to select whether to bypass inverter 334 in the generation of ErrAlertF 338. The ErrAlertF 338 may be an inverted or non-inverted version of the ErrAlert signal 60.

Fig. 10 is a graph 400 of CRC detection and alerting using the synchronous counter based CRC circuit 48 of fig. 6. Graph 400 includes a line 402 corresponding to CLK 150. Additionally, graph 400 includes a line 404 corresponding to CRCerr signal 56 indicating when a CRC error has been detected in CRC detection circuit 54. Graph 400 also includes a line 406 corresponding to ErrAlert signal 60, which is configured to indicate to the host device that a CRC error has been detected.

In the simulation performed to generate graph 400, the CRCerr signal 56 occurs every x (e.g., 9) cycles of line 402. In some specifications (e.g., the DDR5 specification), memory device 10 may set pulse width 407 to a number (e.g., 9-17) cycles of line 402. In graph 400, pulse 408 of CRCerr signal 56 is used to transmit pulse 410 of errart signal 60 having pulse width 407.

The pulse 412 is skipped because the Q0_ block signal 235 is still asserted when the pulse 412 of the crcer signal 56 is received. However, the pulse 414 of the CRCerr signal 56 is used to transmit the pulse 416 of the errerlert signal 60. Similar to pulse 412, pulse 418 is skipped and pulse 420 of CRCerr signal 56 is used to transmit pulse 422 of errerlert signal 60. Thus, graph 400 reflects a consistent and predictable CRC error alert scheme that skips every other CRC error.

Fig. 11 is a graph 430 of CRC detection and alerting using the synchronous counter based CRC circuit 48 of fig. 6. Graph 400 includes a line 402 corresponding to CLK 150. In addition, graph 430 includes a line 432 corresponding to the CRCerr signal 56 indicating when a CRC error has been detected in CRC detection circuit 54. Graph 430 also includes a line 434 corresponding to ErrAlert signal 60, which is configured to indicate to the host device that a CRC error has been detected.

In the simulation performed to generate graph 430, the CRCerr signal 56 occurs every y (e.g., 18) cycles of line 402. In some specifications (e.g., the DDR5 specification), the memory device 10 may set the pulse width 435 to a number of cycles of the line 402. In graph 430, pulse 436 of CRCerr signal 56 is used to transmit pulse 438 of errallert signal 60 having pulse width 435.

The next pulse 440 of the CRCerr signal 56 is used to transmit pulse 442 of the errart signal 60; pulse 444 of CRCerr signal 56 is used to transmit pulse 446 of errerlert signal 60; pulse 448 of CRCerr signal 56 is used to transmit pulse 450 of errallert signal 60; and pulses 452 of CRCerr signal 56 to transmit pulses 454 of errallert signal 60. Thus, graph 430 reflects a consistent and predictable CRC error alert scheme that records each CRC error.

Although the foregoing discusses CRC error detection and alerting, in some embodiments, the foregoing concepts may be applied to other error detection schemes. For example, the foregoing discussion may be applied to parity error detection and warning circuitry. Additionally or alternatively, in some embodiments, the concepts discussed may be used with any verification error detection and warning scheme.

Also, while the circuits discussed include discussing signals having logic high or logic low values, some embodiments may include opposite polarities. In addition, certain circuits (e.g., NAND) may be replaced with equivalent circuits (e.g., inverting inputs to an OR gate) to achieve similar logic results.

While the disclosure may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. It should be understood, however, that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure as defined by the following appended claims.

The technology presented and claimed herein is referenced and applied to material objects and concrete examples of a practical nature which arguably improve upon the art and which are therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to the end of this specification contains one or more elements denoted as "means for [ performing ] [ function ]. or" step for [ performing ] [ function ]. then it is desirable to interpret such elements at 35u.s.c.112 (f). However, for any claim containing elements specified in any other way, it is not intended that such elements be construed at 35u.s.c.112 (f).