阅读说明：本技术 一种适用于无极性多电平电压输入的开关量输入电路 (Switching value input circuit suitable for nonpolar multi-level voltage input ) 是由 罗建平 田坤 杨经超 周坤 王义波 孙祥波 于 2020-05-15 设计创作，主要内容包括：本发明公开了一种适用于无极性多电平电压输入的开关量输入电路,包括第一开关量接口和第二开关量接口,第一开关量接口与整流桥的第一输入端连接,第二开关量接口与整流桥的第二输入端连接；整流桥的第一输入端与二极管的阴极连接,二极管的阳极与第一电源连接,整流桥的第二输入端通过第二光耦隔离采样电路与逻辑门器件的第二输入端连接,整流桥的第一输出端通过第一光耦隔离采样电路与逻辑门器件的第一输入端连接,整流桥的第二输出端与第一电气地连接。本发明为开关量节点的信息采集提供了一个兼容性广的电路设计方案,无需考虑开关量节点的连接极性,适用于多种电平的开关量节点的信息采集。(The invention discloses a switching value input circuit suitable for nonpolar multi-level voltage input, which comprises a first switching value interface and a second switching value interface, wherein the first switching value interface is connected with a first input end of a rectifier bridge; the first input end of the rectifier bridge is connected with the cathode of the diode, the anode of the diode is connected with the first power supply, the second input end of the rectifier bridge is connected with the second input end of the logic gate device through the second optical coupling isolation sampling circuit, the first output end of the rectifier bridge is connected with the first input end of the logic gate device through the first optical coupling isolation sampling circuit, and the second output end of the rectifier bridge is electrically connected with the first output end. The invention provides a circuit design scheme with wide compatibility for the information acquisition of the switching value nodes, does not need to consider the connection polarity of the switching value nodes, and is suitable for the information acquisition of the switching value nodes with various levels.)

1. A switching value input circuit suitable for nonpolar multi-level voltage input comprises a first switching value interface (J1) and a second switching value interface (J2), and is characterized in that the first switching value interface (J1) is connected with a first input end of a rectifier bridge (D2), and the second switching value interface (J2) is connected with a second input end of the rectifier bridge (D2); the first input end of a rectifier bridge (D2) is connected with the cathode of a diode (D1), the anode of the diode (D1) is connected with a first power supply (VDD), the second input end of the rectifier bridge (D2) is connected with the second input end of a logic gate device (U1) through a second optical coupling isolation sampling circuit (2), the first output end of the rectifier bridge (D2) is connected with the first input end of the logic gate device (U1) through a first optical coupling isolation sampling circuit (1), and the second output end of the rectifier bridge (D2) is connected with a first electrical ground (VSS).

2. The switching value input circuit suitable for non-polar multi-level voltage input of claim 1, wherein the first optical coupling isolation sampling circuit (1) comprises a first voltage stabilizing diode (D3), a first current limiting resistor (R1), a first isolation optical coupling (O1) and a second current limiting resistor (R2),

the cathode of the first voltage-stabilizing diode (D3) is connected with the first output end of the rectifier bridge (D2), the anode of the first voltage-stabilizing diode (D3) is connected with a first electrical ground (VSS) through a first current-limiting resistor (D1) and a light-emitting diode of a first isolation optocoupler (O1) in sequence, the collector of a photoelectric receiving triode of the first isolation optocoupler (O1) is connected with one end of a second current-limiting resistor (R2) and the first input end of a logic gate device (U1) respectively, the other end of the second current-limiting resistor (R2) is connected with a second power supply (VCC), and the emitter of the photoelectric receiving triode of the first isolation optocoupler (O1) is connected with a second electrical Ground (GND);

the second optical coupling isolation sampling circuit (2) comprises a second voltage stabilizing diode (D4), a third current limiting resistor (R3), a second isolation optical coupling (O2) and a fourth current limiting resistor (R4),

the cathode of the second voltage-stabilizing diode (D4) is connected with the second output end of the rectifier bridge (D2), the anode of the second voltage-stabilizing diode (D4) is connected with the first electrical ground (VSS) sequentially through the light-emitting diode of the third current-limiting resistor (D3) and the second isolation optocoupler (O2), the collector of the photoelectric receiving triode of the second isolation optocoupler (O2) is connected with one end of the fourth current-limiting resistor (R4) and the second input end of the logic gate device (U1), the other end of the fourth current-limiting resistor (R4) is connected with the second power supply (VCC), and the emitter of the photoelectric receiving triode of the second isolation optocoupler (O2) is connected with the second electrical Ground (GND).

3. The switching value input circuit of claim 2, wherein the first input terminal of the logic gate device (U1) is at a low level, and the second input terminal of the logic gate device (U1) is at a low level, the output terminal of the logic gate device (U1) is at a high level;

when the first input end of the logic gate device (U1) is in low level and the second input end of the logic gate device (U1) is in high level, the output end of the logic gate device (U1) is in high level;

when the first input end of the logic gate device (U1) is in a high level and the second input end of the logic gate device (U1) is in a low level, the output end of the logic gate device (U1) is in a low level;

when the first input terminal of the logic gate device (U1) is at a high level, and the second input terminal of the logic gate device (U1) is at a high level, the output terminal of the logic gate device (U1) is at a high level.

Technical Field

The invention relates to the technical field of digital signal acquisition of secondary equipment of an intelligent substation, in particular to a switching value input circuit suitable for nonpolar multi-level voltage input.

Background

With the rapid development of intelligent power grids in China, switching values in a comprehensive automation system of a transformer substation are more and more, and collected signals comprise tripping position signals of a circuit breaker, a disconnecting switch and a grounding switch, position signals of a tap joint of the transformer, action signals of various relay protection and automatic devices and the like.

At present, the state of switching value node is judged to traditional switching value node's information acquisition mode relies on the on-state of opto-coupler, and this acquisition circuit can only carry out information acquisition to the state of the switching value of single level to this acquisition circuit needs the polarity direction of strict requirement node, otherwise, can appear unable the collection under the condition that the node polarity connects conversely, more probably leads to the acquisition circuit damage. In addition, the node voltages acquired by the switching values of the transformer substation are different, and are 24V, 110V, 220V and the like, so that the conventional switching value acquisition circuit needs to perform corresponding adjustment according to the node voltages of the switching values, and the adjustment is time-consuming and labor-consuming. The switching value input circuit suitable for multi-level voltage input can well solve the problems.

Disclosure of Invention

The invention aims to solve the defects in the prior art and provides a switching value input circuit suitable for nonpolar multi-level voltage input.

In order to solve the technical problems, the technical scheme adopted by the invention is as follows:

a switching value input circuit suitable for nonpolar multilevel voltage input comprises a first switching value interface and a second switching value interface, wherein the first switching value interface is connected with a first input end of a rectifier bridge, and the second switching value interface is connected with a second input end of the rectifier bridge; the first input end of the rectifier bridge is connected with the cathode of the diode, the anode of the diode is connected with the first power supply, the second input end of the rectifier bridge is connected with the second input end of the logic gate device through the second optical coupling isolation sampling circuit, the first output end of the rectifier bridge is connected with the first input end of the logic gate device through the first optical coupling isolation sampling circuit, and the second output end of the rectifier bridge is electrically connected with the first output end.

The first optical coupler isolation sampling circuit comprises a first voltage stabilizing diode, a first current limiting resistor, a first isolation optical coupler and a second current limiting resistor,

the cathode of the first voltage stabilizing diode is connected with the first output end of the rectifier bridge, the anode of the first voltage stabilizing diode is connected with a first electrical ground through a first current limiting resistor and the light emitting diode of a first isolating optocoupler in sequence, the collector of the photoelectric receiving triode of the first isolating optocoupler is connected with one end of a second current limiting resistor and the first input end of the logic gate device respectively, the other end of the second current limiting resistor is connected with a second power supply, and the emitter of the photoelectric receiving triode of the first isolating optocoupler is connected with the second electrical ground;

the second optical coupling isolation sampling circuit comprises a second voltage stabilizing diode, a third current limiting resistor, a second isolation optical coupling and a fourth current limiting resistor,

the cathode of the second voltage stabilizing diode is connected with the second output end of the rectifier bridge, the anode of the second voltage stabilizing diode is connected with the first electrical ground sequentially through the third current limiting resistor and the light emitting diode of the second isolating optocoupler, the collector of the photoelectric receiving triode of the second isolating optocoupler is connected with one end of the fourth current limiting resistor and the second input end of the logic gate device respectively, the other end of the fourth current limiting resistor is connected with the second power supply, and the emitter of the photoelectric receiving triode of the second isolating optocoupler is connected with the second electrical ground.

When the input of the first input end of the logic gate device is low level and the input of the second input end of the logic gate device is low level, the output end of the logic gate device is high level;

when the input of the first input end of the logic gate device is low level and the input of the second input end of the logic gate device is high level, the output end of the logic gate device is high level;

when the input of the first input end of the logic gate device is high level and the input of the second input end of the logic gate device is low level, the output end of the logic gate device is low level;

when the first input end of the logic gate device is in high level and the second input end of the logic gate device is in high level, the output end of the logic gate device is in high level.

Compared with the prior art, the invention has the following beneficial effects:

the circuit can be adaptive to switching value interfaces of various levels, the application range of the switching value acquisition node is expanded, the trouble that equipment needs to be replaced due to the fact that the voltages of the switching value acquisition node are not matched is reduced, and the universality and the convenience of the equipment are enhanced.

The circuit can realize the self-adaptation of the polarity of the switching value node, effectively reduces the complexity of manual wiring, avoids the problem of error acquisition of the switching value information caused by the reverse connection of the polarity of the switching value node, and improves the working efficiency.

Drawings

FIG. 1 is a circuit block diagram of the present invention;

FIG. 2 is a circuit block diagram of the rectifier bridge of the present invention;

FIG. 3 is a first opto-isolator sampling circuit configuration diagram according to the present invention;

FIG. 4 is a diagram of a second opto-isolator sampling circuit according to the present invention;

FIG. 5 is a block diagram of a logic gate device of the present invention;

FIG. 6 is an equivalent circuit diagram of the present invention without switching value;

FIG. 7 is an equivalent circuit diagram of the present invention with forward active switching value open;

FIG. 8 is an equivalent circuit diagram of the present invention with reverse active switching value open;

FIG. 9 is an equivalent circuit diagram of the present invention with the amount of the closed switch connected;

fig. 10 is a truth table for a logic gate device.

Detailed Description

The present invention will be described in further detail with reference to examples for the purpose of facilitating understanding and practice of the invention by those of ordinary skill in the art, and it is to be understood that the present invention has been described in the illustrative embodiments and is not to be construed as limited thereto.

As shown in fig. 1, a switching value input circuit suitable for non-polar multi-level voltage input includes a first switching value interface J1 and a second switching value interface J2, where the first switching value interface J1 is connected to a first input terminal of a rectifier bridge D2, and the second switching value interface J2 is connected to a second input terminal of the rectifier bridge D2; the first input end of the rectifier bridge D2 is connected with the cathode of the diode D1, the anode of the diode D1 is connected with a first power supply VDD, the second input end of the rectifier bridge D2 is connected with the second input end of the logic gate device U1 through the second optical coupling isolation sampling circuit 2, the first output end of the rectifier bridge D2 is connected with the first input end of the logic gate device U1 through the first optical coupling isolation sampling circuit 1, and the second output end of the rectifier bridge D2 is connected with a first electrical ground VSS.

The first optical coupling isolation sampling circuit 1 comprises a first voltage stabilizing diode D3, a first current limiting resistor R1, a first isolation optical coupling O1 and a second current limiting resistor R2,

the cathode of the first voltage-stabilizing diode D3 is connected with the first output end of the rectifier bridge D2, the anode of the first voltage-stabilizing diode D3 is connected with the first electrical ground VSS through the first current-limiting resistor D1 and the light-emitting diode of the first isolating optocoupler O1 in sequence, the collector of the photoelectric receiving triode of the first isolating optocoupler O1 is connected with one end of the second current-limiting resistor R2 and the first input end of the logic gate device U1 respectively, the other end of the second current-limiting resistor R2 is connected with the second power VCC, and the emitter of the photoelectric receiving triode of the first isolating optocoupler O1 is connected with the second electrical ground GND;

the second optical coupling isolation sampling circuit 2 comprises a second voltage-stabilizing diode D4, a third current-limiting resistor R3, a second isolation optical coupling O2 and a fourth current-limiting resistor R4,

the cathode of the second zener diode D4 is connected to the second output terminal of the rectifier bridge D2, the anode of the second zener diode D4 is connected to the first electrical ground VSS through the light emitting diode of the third current limiting resistor D3 and the second isolating optocoupler O2 in sequence, the collector of the photoelectric receiving triode of the second isolating optocoupler O2 is connected to one end of the fourth current limiting resistor R4 and the second input terminal of the logic gate device U1, the other end of the fourth current limiting resistor R4 is connected to the second power VCC, and the emitter of the photoelectric receiving triode of the second isolating optocoupler O2 is connected to the second electrical ground GND.

As shown in fig. 10, when the first input terminal of the logic gate device U1 is at low level and the second input terminal of the logic gate device U1 is at low level, the output terminal of the logic gate device U1 is at high level;

when the input of the first input end of the logic gate device U1 is low level and the input of the second input end of the logic gate device U1 is high level, the output end of the logic gate device U1 is high level;

when the input of the first input end of the logic gate device U1 is high level and the input of the second input end of the logic gate device U1 is low level, the output end of the logic gate device U1 is low level;

when the first input terminal of the logic gate device U1 is at a high level and the second input terminal of the logic gate device U1 is at a high level, the output terminal of the logic gate device U1 is at a high level. When the first switching value interface J1 and the second switching value interface J2 are not connected with any switching value node, the equivalent circuit of the switching value input circuit is as shown in fig. 6; at this time, no voltage source is driven on the line of the second switching value interface J2 connected to the second optical coupler isolation sampling circuit 2, so the second digital signal IN2 output by the second isolation optical coupler O2 will be at a high level. According to the truth table of the logic device U1 shown IN fig. 10, no matter what level the first digital signal IN1 output by the first isolating optocoupler O1 is, the switching value state information DIN finally output by the logic gate device U1 will be high, indicating that the switching value state is off.

When the disconnected switching value node is connected between the first switching value interface J1 and the second switching value interface J2, and the forward voltage of the switching value node is connected to the first switching value interface J1, the equivalent circuit of the switching value input circuit is as shown in fig. 7; although the external voltage exists at the switching value node, the line of the second switching value interface J2 connected to the second optical coupler isolation sampling circuit 2 is still not driven by any voltage source, so the second digital signal IN2 output by the second isolation optical coupler O2 will be at a high level. According to the truth table of the logic device U1 shown IN fig. 10, no matter the external switching value node voltage is equal to or affects the state of the first digital signal IN1 output by the first isolating optocoupler O1, the switching value state information DIN finally output by the logic gate device U1 will still be high, indicating that the switching value state is off.

When the disconnected switching value node is connected between the first switching value interface J1 and the second switching value interface J2, and the forward voltage of the switching value node is connected to the second interface J2, the equivalent circuit of the switching value input circuit is as shown in fig. 8; a voltage source of the second switching value interface J2 returns to the first switching value interface J1 through the second optical coupler isolation sampling circuit 2 and the rectifier bridge D2 to form a complete fifth loop 5 for driving the first isolation optical coupler O2, and a second digital signal IN2 output by the second isolation optical coupler O2 at the moment is at a low level; meanwhile, a voltage source of the second switching value interface J2 is transmitted to the first optical coupler isolation sampling circuit 1 through the rectifier bridge D2, and then returns to the first switching value interface J1 through the rectifier bridge D2, so that a complete fourth loop 4 for driving the first isolation optical coupler O1 is formed; similarly, a first power supply VDD of the switching value circuit is transmitted to the first optical coupler isolation sampling circuit 1 through the diode D1 and the rectifier bridge D2, and reaches a first electrical ground VSS corresponding to the first power supply VDD of the switching value circuit, and the first power supply VDD and the first electrical ground VSS form a power supply source to form a complete first loop 1 for driving the first isolation optical coupler O1; the first isolating optocoupler O1 at this time is driven by the first loop 1 and the fourth loop 4 together, so that the first digital signal IN1 output by the first isolating optocoupler O1 is at a low level. As shown in the truth table of the logic device U1 shown in fig. 10, the switching value state information DIN output by the logic gate device U1 at this time is high, indicating that the switching value state at this time is an off state.

When a closed switching value node is connected between the first switching value interface J1 and the first switching value interface J2, an equivalent circuit of the switching value input circuit at this time is as shown in fig. 9; due to the closing of the switching value node, the first switching value interface J1 and the second switching value interface J2 are equivalently connected by a section of conducting wire, a first power supply VDD of the switching value circuit is transmitted to the first switching value interface J1 and the second switching value interface J2 through a diode D1 to the second optical coupler isolation sampling circuit 2, and reaches the first electrical ground VSS of the switching value circuit to form a complete second loop 2 for driving the second isolation optical coupler O2, and at the moment, a second digital signal IN2 output by the second isolation optical coupler O2 is at a low level; similarly, a first power supply VDD of the switching value circuit is transmitted to the first optical coupler isolation sampling circuit 1 through the diode D1 and the rectifier bridge D2, and reaches the first electrical ground VSS of the switching value circuit, so as to form a complete first loop 1 for driving the first isolation optical coupler O1, but the parameters of the voltage stabilizing diode D3 and the first current limiting resistor R1 determine that the first isolation optical coupler O1 cannot be completely switched on, and the first digital signal IN1 output by the first isolation optical coupler O1 at this time is at a high level. As shown in the truth table of the logic device U1 shown in fig. 10, the switching value state information DIN output by the logic gate device U1 at this time is low, indicating that the switching value state at this time is a closed state.

In summary, the design circuit can correctly identify the state information of the switching value node. The state information of the active switching value node and the passive switching value node can be normally identified, and the state information identification of various active switching value nodes is supported.

The specific embodiments described herein are merely illustrative of the spirit of the invention. Various modifications or additions may be made to the described embodiments or alternatives may be employed by those skilled in the art without departing from the spirit or ambit of the invention as defined in the appended claims.